1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
29 #include <rte_spinlock.h>
31 #include <rte_bus_pci.h>
33 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
39 #include "mlx5_glue.h"
41 /* Support tunnel matching. */
42 #define MLX5_FLOW_TUNNEL 5
44 struct mlx5_rxq_stats {
45 #ifdef MLX5_PMD_SOFT_COUNTERS
46 uint64_t ipackets; /**< Total of successfully received packets. */
47 uint64_t ibytes; /**< Total of successfully received bytes. */
49 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
50 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
53 struct mlx5_txq_stats {
54 #ifdef MLX5_PMD_SOFT_COUNTERS
55 uint64_t opackets; /**< Total of successfully sent packets. */
56 uint64_t obytes; /**< Total of successfully sent bytes. */
58 uint64_t oerrors; /**< Total number of failed transmitted packets. */
63 /* Compressed CQE context. */
65 uint16_t ai; /* Array index. */
66 uint16_t ca; /* Current array index. */
67 uint16_t na; /* Next array index. */
68 uint16_t cq_ci; /* The next CQE. */
69 uint32_t cqe_cnt; /* Number of CQEs. */
72 /* Multi-Packet RQ buffer header. */
73 struct mlx5_mprq_buf {
74 struct rte_mempool *mp;
75 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
76 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
77 } __rte_cache_aligned;
79 /* Get pointer to the first stride. */
80 #define mlx5_mprq_buf_addr(ptr) ((ptr) + 1)
82 enum mlx5_rxq_err_state {
83 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
84 MLX5_RXQ_ERR_STATE_NEED_RESET,
85 MLX5_RXQ_ERR_STATE_NEED_READY,
88 /* RX queue descriptor. */
89 struct mlx5_rxq_data {
90 unsigned int csum:1; /* Enable checksum offloading. */
91 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
92 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
93 unsigned int crc_present:1; /* CRC must be subtracted. */
94 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
95 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
96 unsigned int elts_n:4; /* Log 2 of Mbufs. */
97 unsigned int rss_hash:1; /* RSS hash result is enabled. */
98 unsigned int mark:1; /* Marked flow available on the queue. */
99 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
100 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
101 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
102 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
103 unsigned int :4; /* Remaining bits. */
104 volatile uint32_t *rq_db;
105 volatile uint32_t *cq_db;
108 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
111 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
113 struct rxq_zip zip; /* Compressed context. */
114 uint16_t decompressed;
115 /* Number of ready mbufs decompressed from the CQ. */
117 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
118 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
120 volatile struct mlx5_cqe(*cqes)[];
123 struct rte_mbuf *(*elts)[];
124 struct mlx5_mprq_buf *(*mprq_bufs)[];
126 struct rte_mempool *mp;
127 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
128 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
129 uint16_t idx; /* Queue index. */
130 struct mlx5_rxq_stats stats;
131 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
132 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
133 void *cq_uar; /* CQ user access region. */
134 uint32_t cqn; /* CQ number. */
135 uint8_t cq_arm_sn; /* CQ arm seq number. */
137 rte_spinlock_t *uar_lock_cq;
138 /* CQ (UAR) access lock required for 32bit implementations */
140 uint32_t tunnel; /* Tunnel information. */
141 } __rte_cache_aligned;
143 /* Verbs Rx queue elements. */
144 struct mlx5_rxq_ibv {
145 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
146 rte_atomic32_t refcnt; /* Reference counter. */
147 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
148 struct ibv_cq *cq; /* Completion Queue. */
149 struct ibv_wq *wq; /* Work Queue. */
150 struct ibv_comp_channel *channel;
153 /* RX queue control descriptor. */
154 struct mlx5_rxq_ctrl {
155 struct mlx5_rxq_data rxq; /* Data path structure. */
156 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
157 rte_atomic32_t refcnt; /* Reference counter. */
158 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
159 struct mlx5_priv *priv; /* Back pointer to private data. */
160 unsigned int socket; /* CPU socket ID for allocations. */
161 unsigned int irq:1; /* Whether IRQ is enabled. */
162 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
163 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
164 uint16_t dump_file_n; /* Number of dump files. */
167 /* Indirection table. */
168 struct mlx5_ind_table_ibv {
169 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
170 rte_atomic32_t refcnt; /* Reference counter. */
171 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
172 uint32_t queues_n; /**< Number of queues in the list. */
173 uint16_t queues[]; /**< Queue list. */
178 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
179 rte_atomic32_t refcnt; /* Reference counter. */
180 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
181 struct ibv_qp *qp; /* Verbs queue pair. */
182 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
183 void *action; /* DV QP action pointer. */
185 uint64_t hash_fields; /* Verbs Hash fields. */
186 uint32_t rss_key_len; /* Hash key length in bytes. */
187 uint8_t rss_key[]; /* Hash key. */
190 /* TX queue descriptor. */
192 struct mlx5_txq_data {
193 uint16_t elts_head; /* Current counter in (*elts)[]. */
194 uint16_t elts_tail; /* Counter of first element awaiting completion. */
195 uint16_t elts_comp; /* Counter since last completion request. */
196 uint16_t mpw_comp; /* WQ index since last completion request. */
197 uint16_t cq_ci; /* Consumer index for completion queue. */
199 uint16_t cq_pi; /* Producer index for completion queue. */
201 uint16_t wqe_ci; /* Consumer index for work queue. */
202 uint16_t wqe_pi; /* Producer index for work queue. */
203 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
204 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
205 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
206 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
207 uint16_t tunnel_en:1;
208 /* When set TX offload for tunneled packets are supported. */
209 uint16_t swp_en:1; /* Whether SW parser is enabled. */
210 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
211 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
212 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
213 uint32_t qp_num_8s; /* QP number shifted by 8. */
214 uint64_t offloads; /* Offloads for Tx Queue. */
215 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
216 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
217 volatile void *wqes; /* Work queue (use volatile to write into). */
218 volatile uint32_t *qp_db; /* Work queue doorbell. */
219 volatile uint32_t *cq_db; /* Completion queue doorbell. */
220 struct rte_mbuf *(*elts)[]; /* TX elements. */
221 uint16_t port_id; /* Port ID of device. */
222 uint16_t idx; /* Queue index. */
223 struct mlx5_txq_stats stats; /* TX queue counters. */
225 rte_spinlock_t *uar_lock;
226 /* UAR access lock required for 32bit implementations */
228 } __rte_cache_aligned;
230 /* Verbs Rx queue elements. */
231 struct mlx5_txq_ibv {
232 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
233 rte_atomic32_t refcnt; /* Reference counter. */
234 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
235 struct ibv_cq *cq; /* Completion Queue. */
236 struct ibv_qp *qp; /* Queue Pair. */
239 /* TX queue control descriptor. */
240 struct mlx5_txq_ctrl {
241 struct mlx5_txq_data txq; /* Data path structure. */
242 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
243 rte_atomic32_t refcnt; /* Reference counter. */
244 unsigned int socket; /* CPU socket ID for allocations. */
245 unsigned int max_inline_data; /* Max inline data. */
246 unsigned int max_tso_header; /* Max TSO header size. */
247 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
248 struct mlx5_priv *priv; /* Back pointer to private data. */
249 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
250 void *bf_reg; /* BlueFlame register from Verbs. */
251 uint32_t cqn; /* CQ number. */
252 uint16_t dump_file_n; /* Number of dump files. */
255 #define MLX5_TX_BFREG(txq) \
256 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
260 extern uint8_t rss_hash_default_key[];
262 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
263 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
264 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
265 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
266 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
267 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
268 unsigned int socket, const struct rte_eth_rxconf *conf,
269 struct rte_mempool *mp);
270 void mlx5_rx_queue_release(void *dpdk_rxq);
271 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
272 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
273 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
274 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
275 struct mlx5_rxq_ibv *mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
276 int mlx5_rxq_ibv_verify(struct rte_eth_dev *dev);
277 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
278 uint16_t desc, unsigned int socket,
279 const struct rte_eth_rxconf *conf,
280 struct rte_mempool *mp);
281 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
282 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
283 int mlx5_rxq_verify(struct rte_eth_dev *dev);
284 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
285 int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev);
286 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
287 const uint8_t *rss_key, uint32_t rss_key_len,
288 uint64_t hash_fields,
289 const uint16_t *queues, uint32_t queues_n,
290 int tunnel __rte_unused);
291 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
292 const uint8_t *rss_key, uint32_t rss_key_len,
293 uint64_t hash_fields,
294 const uint16_t *queues, uint32_t queues_n);
295 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
296 int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev);
297 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
298 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
299 uint64_t mlx5_get_rx_port_offloads(void);
300 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
304 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
305 unsigned int socket, const struct rte_eth_txconf *conf);
306 void mlx5_tx_queue_release(void *dpdk_txq);
307 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
308 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
309 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
310 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
311 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
312 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
313 uint16_t desc, unsigned int socket,
314 const struct rte_eth_txconf *conf);
315 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
316 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
317 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
318 int mlx5_txq_verify(struct rte_eth_dev *dev);
319 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
320 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
324 extern uint32_t mlx5_ptype_table[];
325 extern uint8_t mlx5_cksum_table[];
326 extern uint8_t mlx5_swp_types_table[];
328 void mlx5_set_ptype_table(void);
329 void mlx5_set_cksum_table(void);
330 void mlx5_set_swp_types_table(void);
331 uint16_t mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
333 uint16_t mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts,
335 uint16_t mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
337 uint16_t mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts,
339 __rte_noinline uint16_t mlx5_tx_error_cqe_handle(struct mlx5_txq_data *txq,
340 volatile struct mlx5_err_cqe *err_cqe);
341 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
342 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
343 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq,
344 uint8_t mbuf_prepare);
345 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
346 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
347 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
349 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
351 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
353 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
354 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
355 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
356 void mlx5_dump_debug_information(const char *path, const char *title,
357 const void *buf, unsigned int len);
359 /* Vectorized version of mlx5_rxtx.c */
360 int mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev);
361 int mlx5_check_vec_tx_support(struct rte_eth_dev *dev);
362 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
363 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
364 uint16_t mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
366 uint16_t mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
368 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
373 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
374 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
375 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
376 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
377 struct rte_mempool *mp);
378 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
380 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
384 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
385 * 64bit architectures.
388 * value to write in CPU endian format.
390 * Address to write to.
392 * Address of the lock to use for that UAR access.
394 static __rte_always_inline void
395 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
396 rte_spinlock_t *lock __rte_unused)
399 *(uint64_t *)addr = val;
400 #else /* !RTE_ARCH_64 */
401 rte_spinlock_lock(lock);
402 *(uint32_t *)addr = val;
404 *((uint32_t *)addr + 1) = val >> 32;
405 rte_spinlock_unlock(lock);
410 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
411 * 64bit architectures while guaranteeing the order of execution with the
412 * code being executed.
415 * value to write in CPU endian format.
417 * Address to write to.
419 * Address of the lock to use for that UAR access.
421 static __rte_always_inline void
422 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
425 __mlx5_uar_write64_relaxed(val, addr, lock);
428 /* Assist macros, used instead of directly calling the functions they wrap. */
430 #define mlx5_uar_write64_relaxed(val, dst, lock) \
431 __mlx5_uar_write64_relaxed(val, dst, NULL)
432 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
434 #define mlx5_uar_write64_relaxed(val, dst, lock) \
435 __mlx5_uar_write64_relaxed(val, dst, lock)
436 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
440 enum mlx5_cqe_status {
441 MLX5_CQE_STATUS_SW_OWN,
442 MLX5_CQE_STATUS_HW_OWN,
447 * Check whether CQE is valid.
452 * Size of completion queue.
459 static __rte_always_inline enum mlx5_cqe_status
460 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
463 const uint16_t idx = ci & cqes_n;
464 const uint8_t op_own = cqe->op_own;
465 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
466 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
468 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
469 return MLX5_CQE_STATUS_HW_OWN;
471 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
472 op_code == MLX5_CQE_REQ_ERR))
473 return MLX5_CQE_STATUS_ERR;
474 return MLX5_CQE_STATUS_SW_OWN;
478 * Return the address of the WQE.
481 * Pointer to TX queue structure.
483 * WQE consumer index.
488 static inline uintptr_t *
489 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
491 ci &= ((1 << txq->wqe_n) - 1);
492 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
496 * Handle the next CQE.
499 * Pointer to TX queue structure.
502 * The last Tx buffer element to free.
504 static __rte_always_inline uint16_t
505 mlx5_tx_cqe_handle(struct mlx5_txq_data *txq)
507 const unsigned int cqe_n = 1 << txq->cqe_n;
508 const unsigned int cqe_cnt = cqe_n - 1;
511 volatile struct mlx5_cqe *cqe;
512 volatile struct mlx5_err_cqe *err_cqe;
514 .cqe = &(*txq->cqes)[txq->cq_ci & cqe_cnt],
516 int ret = check_cqe(u.cqe, cqe_n, txq->cq_ci);
518 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
519 if (unlikely(ret == MLX5_CQE_STATUS_ERR))
520 last_elts = mlx5_tx_error_cqe_handle(txq, u.err_cqe);
522 /* Do not release buffers. */
523 return txq->elts_tail;
525 uint16_t new_wqe_pi = rte_be_to_cpu_16(u.cqe->wqe_counter);
526 volatile struct mlx5_wqe_ctrl *ctrl =
527 (volatile struct mlx5_wqe_ctrl *)
528 tx_mlx5_wqe(txq, new_wqe_pi);
530 /* Release completion burst buffers. */
531 last_elts = ctrl->ctrl3;
532 txq->wqe_pi = new_wqe_pi;
535 rte_compiler_barrier();
536 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
541 * Manage TX completions.
543 * When sending a burst, mlx5_tx_burst() posts several WRs.
546 * Pointer to TX queue structure.
548 static __rte_always_inline void
549 mlx5_tx_complete(struct mlx5_txq_data *txq)
551 const uint16_t elts_n = 1 << txq->elts_n;
552 const uint16_t elts_m = elts_n - 1;
553 uint16_t elts_free = txq->elts_tail;
555 struct rte_mbuf *m, *free[elts_n];
556 struct rte_mempool *pool = NULL;
557 unsigned int blk_n = 0;
559 elts_tail = mlx5_tx_cqe_handle(txq);
560 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
562 while (elts_free != elts_tail) {
563 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
564 if (likely(m != NULL)) {
565 if (likely(m->pool == pool)) {
568 if (likely(pool != NULL))
569 rte_mempool_put_bulk(pool,
579 rte_mempool_put_bulk(pool, (void *)free, blk_n);
581 elts_free = txq->elts_tail;
583 while (elts_free != elts_tail) {
584 memset(&(*txq->elts)[elts_free & elts_m],
586 sizeof((*txq->elts)[elts_free & elts_m]));
590 txq->elts_tail = elts_tail;
594 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
595 * cloned mbuf is allocated is returned instead.
601 * Memory pool where data is located for given mbuf.
603 static inline struct rte_mempool *
604 mlx5_mb2mp(struct rte_mbuf *buf)
606 if (unlikely(RTE_MBUF_CLONED(buf)))
607 return rte_mbuf_from_indirect(buf)->pool;
612 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
613 * as mempool is pre-configured and static.
616 * Pointer to Rx queue structure.
621 * Searched LKey on success, UINT32_MAX on no match.
623 static __rte_always_inline uint32_t
624 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
626 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
629 /* Linear search on MR cache array. */
630 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
631 MLX5_MR_CACHE_N, addr);
632 if (likely(lkey != UINT32_MAX))
634 /* Take slower bottom-half (Binary Search) on miss. */
635 return mlx5_rx_addr2mr_bh(rxq, addr);
638 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
641 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
644 * Pointer to Tx queue structure.
649 * Searched LKey on success, UINT32_MAX on no match.
651 static __rte_always_inline uint32_t
652 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
654 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
655 uintptr_t addr = (uintptr_t)mb->buf_addr;
658 /* Check generation bit to see if there's any change on existing MRs. */
659 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
660 mlx5_mr_flush_local_cache(mr_ctrl);
661 /* Linear search on MR cache array. */
662 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
663 MLX5_MR_CACHE_N, addr);
664 if (likely(lkey != UINT32_MAX))
666 /* Take slower bottom-half on miss. */
667 return mlx5_tx_mb2mr_bh(txq, mb);
671 * Ring TX queue doorbell and flush the update if requested.
674 * Pointer to TX queue structure.
676 * Pointer to the last WQE posted in the NIC.
678 * Request for write memory barrier after BlueFlame update.
680 static __rte_always_inline void
681 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
684 uint64_t *dst = MLX5_TX_BFREG(txq);
685 volatile uint64_t *src = ((volatile uint64_t *)wqe);
688 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
689 /* Ensure ordering between DB record and BF copy. */
691 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
697 * Ring TX queue doorbell and flush the update by write memory barrier.
700 * Pointer to TX queue structure.
702 * Pointer to the last WQE posted in the NIC.
704 static __rte_always_inline void
705 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
707 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
711 * Convert mbuf to Verb SWP.
714 * Pointer to the Tx queue.
716 * Pointer to the mbuf.
718 * Pointer to the SWP header offsets.
720 * Pointer to the SWP header types.
722 static __rte_always_inline void
723 txq_mbuf_to_swp(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
724 uint8_t *offsets, uint8_t *swp_types)
726 const uint64_t vlan = buf->ol_flags & PKT_TX_VLAN_PKT;
727 const uint64_t tunnel = buf->ol_flags & PKT_TX_TUNNEL_MASK;
728 const uint64_t tso = buf->ol_flags & PKT_TX_TCP_SEG;
729 const uint64_t csum_flags = buf->ol_flags & PKT_TX_L4_MASK;
730 const uint64_t inner_ip =
731 buf->ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6);
732 const uint64_t ol_flags_mask = PKT_TX_L4_MASK | PKT_TX_IPV6 |
737 if (likely(!txq->swp_en || (tunnel != PKT_TX_TUNNEL_UDP &&
738 tunnel != PKT_TX_TUNNEL_IP)))
741 * The index should have:
742 * bit[0:1] = PKT_TX_L4_MASK
743 * bit[4] = PKT_TX_IPV6
744 * bit[8] = PKT_TX_OUTER_IPV6
745 * bit[9] = PKT_TX_OUTER_UDP
747 idx = (buf->ol_flags & ol_flags_mask) >> 52;
748 if (tunnel == PKT_TX_TUNNEL_UDP)
750 *swp_types = mlx5_swp_types_table[idx];
752 * Set offsets for SW parser. Since ConnectX-5, SW parser just
753 * complements HW parser. SW parser starts to engage only if HW parser
754 * can't reach a header. For the older devices, HW parser will not kick
755 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
756 * should be set regardless of HW offload.
758 off = buf->outer_l2_len + (vlan ? sizeof(struct rte_vlan_hdr) : 0);
759 offsets[1] = off >> 1; /* Outer L3 offset. */
760 off += buf->outer_l3_len;
761 if (tunnel == PKT_TX_TUNNEL_UDP)
762 offsets[0] = off >> 1; /* Outer L4 offset. */
765 offsets[3] = off >> 1; /* Inner L3 offset. */
766 if (csum_flags == PKT_TX_TCP_CKSUM || tso ||
767 csum_flags == PKT_TX_UDP_CKSUM) {
769 offsets[2] = off >> 1; /* Inner L4 offset. */
775 * Convert the Checksum offloads to Verbs.
778 * Pointer to the mbuf.
781 * Converted checksum flags.
783 static __rte_always_inline uint8_t
784 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
787 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
788 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
789 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
792 * The index should have:
793 * bit[0] = PKT_TX_TCP_SEG
794 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
795 * bit[4] = PKT_TX_IP_CKSUM
796 * bit[8] = PKT_TX_OUTER_IP_CKSUM
799 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
800 return mlx5_cksum_table[idx];
804 * Count the number of contiguous single segment packets.
807 * Pointer to array of packets.
812 * Number of contiguous single segment packets.
814 static __rte_always_inline unsigned int
815 txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
821 /* Count the number of contiguous single segment packets. */
822 for (pos = 0; pos < pkts_n; ++pos)
823 if (NB_SEGS(pkts[pos]) > 1)
829 * Count the number of contiguous multi-segment packets.
832 * Pointer to array of packets.
837 * Number of contiguous multi-segment packets.
839 static __rte_always_inline unsigned int
840 txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
846 /* Count the number of contiguous multi-segment packets. */
847 for (pos = 0; pos < pkts_n; ++pos)
848 if (NB_SEGS(pkts[pos]) == 1)
853 #endif /* RTE_PMD_MLX5_RXTX_H_ */