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34 #ifndef RTE_PMD_MLX5_RXTX_H_
35 #define RTE_PMD_MLX5_RXTX_H_
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
46 #include <infiniband/mlx5_hw.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_common.h>
59 #pragma GCC diagnostic error "-Wpedantic"
62 #include "mlx5_utils.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
68 struct mlx5_rxq_stats {
69 unsigned int idx; /**< Mapping index. */
70 #ifdef MLX5_PMD_SOFT_COUNTERS
71 uint64_t ipackets; /**< Total of successfully received packets. */
72 uint64_t ibytes; /**< Total of successfully received bytes. */
74 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
75 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
78 struct mlx5_txq_stats {
79 unsigned int idx; /**< Mapping index. */
80 #ifdef MLX5_PMD_SOFT_COUNTERS
81 uint64_t opackets; /**< Total of successfully sent packets. */
82 uint64_t obytes; /**< Total of successfully sent bytes. */
84 uint64_t odropped; /**< Total of packets not sent when TX ring full. */
87 /* Flow director queue structure. */
89 struct ibv_qp *qp; /* Associated RX QP. */
90 struct ibv_exp_rwq_ind_table *ind_table; /* Indirection table. */
91 struct ibv_exp_wq *wq; /* Work queue. */
92 struct ibv_cq *cq; /* Completion queue. */
97 /* Compressed CQE context. */
99 uint16_t ai; /* Array index. */
100 uint16_t ca; /* Current array index. */
101 uint16_t na; /* Next array index. */
102 uint16_t cq_ci; /* The next CQE. */
103 uint32_t cqe_cnt; /* Number of CQEs. */
106 /* RX queue descriptor. */
108 unsigned int csum:1; /* Enable checksum offloading. */
109 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
110 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
111 unsigned int crc_present:1; /* CRC must be subtracted. */
112 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
113 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
114 unsigned int elts_n:4; /* Log 2 of Mbufs. */
115 unsigned int port_id:8;
116 unsigned int rss_hash:1; /* RSS hash result is enabled. */
117 unsigned int mark:1; /* Marked flow available on the queue. */
118 unsigned int :8; /* Remaining bits. */
119 volatile uint32_t *rq_db;
120 volatile uint32_t *cq_db;
123 volatile struct mlx5_wqe_data_seg(*wqes)[];
124 volatile struct mlx5_cqe(*cqes)[];
125 struct rxq_zip zip; /* Compressed context. */
126 struct rte_mbuf *(*elts)[];
127 struct rte_mempool *mp;
128 struct mlx5_rxq_stats stats;
129 } __rte_cache_aligned;
131 /* RX queue control descriptor. */
133 struct priv *priv; /* Back pointer to private data. */
134 struct ibv_cq *cq; /* Completion Queue. */
135 struct ibv_exp_wq *wq; /* Work Queue. */
136 struct fdir_queue *fdir_queue; /* Flow director queue. */
137 struct ibv_mr *mr; /* Memory Region (for mp). */
138 struct ibv_comp_channel *channel;
139 unsigned int socket; /* CPU socket ID for allocations. */
140 struct rxq rxq; /* Data path structure. */
143 /* Hash RX queue types. */
154 /* Flow structure with Ethernet specification. It is packed to prevent padding
155 * between attr and spec as this layout is expected by libibverbs. */
156 struct flow_attr_spec_eth {
157 struct ibv_exp_flow_attr attr;
158 struct ibv_exp_flow_spec_eth spec;
159 } __attribute__((packed));
161 /* Define a struct flow_attr_spec_eth object as an array of at least
162 * "size" bytes. Room after the first index is normally used to store
163 * extra flow specifications. */
164 #define FLOW_ATTR_SPEC_ETH(name, size) \
165 struct flow_attr_spec_eth name \
166 [((size) / sizeof(struct flow_attr_spec_eth)) + \
167 !!((size) % sizeof(struct flow_attr_spec_eth))]
169 /* Initialization data for hash RX queue. */
170 struct hash_rxq_init {
171 uint64_t hash_fields; /* Fields that participate in the hash. */
172 uint64_t dpdk_rss_hf; /* Matching DPDK RSS hash fields. */
173 unsigned int flow_priority; /* Flow priority to use. */
176 enum ibv_exp_flow_spec_type type;
179 struct ibv_exp_flow_spec_tcp_udp tcp_udp;
180 struct ibv_exp_flow_spec_ipv4 ipv4;
181 struct ibv_exp_flow_spec_ipv6 ipv6;
182 struct ibv_exp_flow_spec_eth eth;
183 } flow_spec; /* Flow specification template. */
184 const struct hash_rxq_init *underlayer; /* Pointer to underlayer. */
187 /* Initialization data for indirection table. */
188 struct ind_table_init {
189 unsigned int max_size; /* Maximum number of WQs. */
190 /* Hash RX queues using this table. */
191 unsigned int hash_types;
192 unsigned int hash_types_n;
195 /* Initialization data for special flows. */
196 struct special_flow_init {
197 uint8_t dst_mac_val[6];
198 uint8_t dst_mac_mask[6];
199 unsigned int hash_types;
200 unsigned int per_vlan:1;
203 enum hash_rxq_flow_type {
204 HASH_RXQ_FLOW_TYPE_PROMISC,
205 HASH_RXQ_FLOW_TYPE_ALLMULTI,
206 HASH_RXQ_FLOW_TYPE_BROADCAST,
207 HASH_RXQ_FLOW_TYPE_IPV6MULTI,
208 HASH_RXQ_FLOW_TYPE_MAC,
212 static inline const char *
213 hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type)
216 case HASH_RXQ_FLOW_TYPE_PROMISC:
217 return "promiscuous";
218 case HASH_RXQ_FLOW_TYPE_ALLMULTI:
219 return "allmulticast";
220 case HASH_RXQ_FLOW_TYPE_BROADCAST:
222 case HASH_RXQ_FLOW_TYPE_IPV6MULTI:
223 return "IPv6 multicast";
224 case HASH_RXQ_FLOW_TYPE_MAC:
232 struct priv *priv; /* Back pointer to private data. */
233 struct ibv_qp *qp; /* Hash RX QP. */
234 enum hash_rxq_type type; /* Hash RX queue type. */
235 /* MAC flow steering rules, one per VLAN ID. */
236 struct ibv_exp_flow *mac_flow
237 [MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS];
238 struct ibv_exp_flow *special_flow
239 [MLX5_MAX_SPECIAL_FLOWS][MLX5_MAX_VLAN_IDS];
242 /* TX queue descriptor. */
245 uint16_t elts_head; /* Current index in (*elts)[]. */
246 uint16_t elts_tail; /* First element awaiting completion. */
247 uint16_t elts_comp; /* Counter since last completion request. */
248 uint16_t mpw_comp; /* WQ index since last completion request. */
249 uint16_t cq_ci; /* Consumer index for completion queue. */
250 uint16_t cq_pi; /* Producer index for completion queue. */
251 uint16_t wqe_ci; /* Consumer index for work queue. */
252 uint16_t wqe_pi; /* Producer index for work queue. */
253 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
254 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
255 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
256 uint16_t inline_en:1; /* When set inline is enabled. */
257 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
258 uint16_t tunnel_en:1;
259 /* When set TX offload for tunneled packets are supported. */
260 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
261 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
262 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
263 uint32_t qp_num_8s; /* QP number shifted by 8. */
264 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
265 volatile void *wqes; /* Work queue (use volatile to write into). */
266 volatile uint32_t *qp_db; /* Work queue doorbell. */
267 volatile uint32_t *cq_db; /* Completion queue doorbell. */
268 volatile void *bf_reg; /* Blueflame register. */
270 const struct rte_mempool *mp; /* Cached Memory Pool. */
271 struct ibv_mr *mr; /* Memory Region (for mp). */
272 uint32_t lkey; /* htonl(mr->lkey) */
273 } mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
274 struct rte_mbuf *(*elts)[]; /* TX elements. */
275 struct mlx5_txq_stats stats; /* TX queue counters. */
276 } __rte_cache_aligned;
278 /* TX queue control descriptor. */
280 struct priv *priv; /* Back pointer to private data. */
281 struct ibv_cq *cq; /* Completion Queue. */
282 struct ibv_qp *qp; /* Queue Pair. */
283 unsigned int socket; /* CPU socket ID for allocations. */
284 struct txq txq; /* Data path structure. */
289 extern const struct hash_rxq_init hash_rxq_init[];
290 extern const unsigned int hash_rxq_init_n;
292 extern uint8_t rss_hash_default_key[];
293 extern const size_t rss_hash_default_key_len;
295 size_t priv_flow_attr(struct priv *, struct ibv_exp_flow_attr *,
296 size_t, enum hash_rxq_type);
297 int priv_create_hash_rxqs(struct priv *);
298 void priv_destroy_hash_rxqs(struct priv *);
299 int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type);
300 int priv_rehash_flows(struct priv *);
301 int priv_intr_efd_enable(struct priv *priv);
302 void priv_intr_efd_disable(struct priv *priv);
303 int priv_create_intr_vec(struct priv *priv);
304 void priv_destroy_intr_vec(struct priv *priv);
305 void rxq_cleanup(struct rxq_ctrl *);
306 int rxq_rehash(struct rte_eth_dev *, struct rxq_ctrl *);
307 int rxq_ctrl_setup(struct rte_eth_dev *, struct rxq_ctrl *, uint16_t,
308 unsigned int, const struct rte_eth_rxconf *,
309 struct rte_mempool *);
310 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
311 const struct rte_eth_rxconf *, struct rte_mempool *);
312 void mlx5_rx_queue_release(void *);
313 uint16_t mlx5_rx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
317 void txq_cleanup(struct txq_ctrl *);
318 int txq_ctrl_setup(struct rte_eth_dev *, struct txq_ctrl *, uint16_t,
319 unsigned int, const struct rte_eth_txconf *);
320 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
321 const struct rte_eth_txconf *);
322 void mlx5_tx_queue_release(void *);
323 uint16_t mlx5_tx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
327 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
328 uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
329 uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
330 uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t);
331 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
332 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
333 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
334 int mlx5_rx_descriptor_status(void *, uint16_t);
335 int mlx5_tx_descriptor_status(void *, uint16_t);
336 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
337 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
341 struct ibv_mr *mlx5_mp2mr(struct ibv_pd *, struct rte_mempool *);
342 void txq_mp2mr_iter(struct rte_mempool *, void *);
343 uint32_t txq_mp2mr_reg(struct txq *, struct rte_mempool *, unsigned int);
345 #endif /* RTE_PMD_MLX5_RXTX_H_ */