1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
29 #include <rte_spinlock.h>
31 #include <rte_bus_pci.h>
32 #include <rte_malloc.h>
34 #include <mlx5_glue.h>
36 #include <mlx5_common.h>
38 #include "mlx5_defs.h"
39 #include "mlx5_utils.h"
42 #include "mlx5_autoconf.h"
44 /* Support tunnel matching. */
45 #define MLX5_FLOW_TUNNEL 10
47 /* Mbuf dynamic flag offset for inline. */
48 extern uint64_t rte_net_mlx5_dynf_inline_mask;
50 struct mlx5_rxq_stats {
51 #ifdef MLX5_PMD_SOFT_COUNTERS
52 uint64_t ipackets; /**< Total of successfully received packets. */
53 uint64_t ibytes; /**< Total of successfully received bytes. */
55 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
56 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
59 struct mlx5_txq_stats {
60 #ifdef MLX5_PMD_SOFT_COUNTERS
61 uint64_t opackets; /**< Total of successfully sent packets. */
62 uint64_t obytes; /**< Total of successfully sent bytes. */
64 uint64_t oerrors; /**< Total number of failed transmitted packets. */
69 /* Compressed CQE context. */
71 uint16_t ai; /* Array index. */
72 uint16_t ca; /* Current array index. */
73 uint16_t na; /* Next array index. */
74 uint16_t cq_ci; /* The next CQE. */
75 uint32_t cqe_cnt; /* Number of CQEs. */
78 /* Multi-Packet RQ buffer header. */
79 struct mlx5_mprq_buf {
80 struct rte_mempool *mp;
81 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
82 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
83 struct rte_mbuf_ext_shared_info shinfos[];
85 * Shared information per stride.
86 * More memory will be allocated for the first stride head-room and for
89 } __rte_cache_aligned;
91 /* Get pointer to the first stride. */
92 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
93 sizeof(struct mlx5_mprq_buf) + \
95 sizeof(struct rte_mbuf_ext_shared_info) + \
96 RTE_PKTMBUF_HEADROOM))
98 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
99 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
101 enum mlx5_rxq_err_state {
102 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
103 MLX5_RXQ_ERR_STATE_NEED_RESET,
104 MLX5_RXQ_ERR_STATE_NEED_READY,
107 /* RX queue descriptor. */
108 struct mlx5_rxq_data {
109 unsigned int csum:1; /* Enable checksum offloading. */
110 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
111 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
112 unsigned int crc_present:1; /* CRC must be subtracted. */
113 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */
114 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
115 unsigned int elts_n:4; /* Log 2 of Mbufs. */
116 unsigned int rss_hash:1; /* RSS hash result is enabled. */
117 unsigned int mark:1; /* Marked flow available on the queue. */
118 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
119 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
120 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
121 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
122 unsigned int strd_headroom_en:1; /* Enable mbuf headroom in MPRQ. */
123 unsigned int lro:1; /* Enable LRO. */
124 unsigned int :1; /* Remaining bits. */
125 volatile uint32_t *rq_db;
126 volatile uint32_t *cq_db;
129 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
132 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
134 struct rxq_zip zip; /* Compressed context. */
135 uint16_t decompressed;
136 /* Number of ready mbufs decompressed from the CQ. */
138 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
139 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
141 volatile struct mlx5_cqe(*cqes)[];
144 struct rte_mbuf *(*elts)[];
145 struct mlx5_mprq_buf *(*mprq_bufs)[];
147 struct rte_mempool *mp;
148 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
149 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
150 uint16_t idx; /* Queue index. */
151 struct mlx5_rxq_stats stats;
152 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */
153 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
154 void *cq_uar; /* CQ user access region. */
155 uint32_t cqn; /* CQ number. */
156 uint8_t cq_arm_sn; /* CQ arm seq number. */
158 rte_spinlock_t *uar_lock_cq;
159 /* CQ (UAR) access lock required for 32bit implementations */
161 uint32_t tunnel; /* Tunnel information. */
162 } __rte_cache_aligned;
164 enum mlx5_rxq_obj_type {
165 MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */
166 MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */
167 MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN,
168 /* mlx5_rxq_obj with mlx5_devx_rq and hairpin support. */
172 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */
173 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
174 MLX5_RXQ_TYPE_UNDEFINED,
177 /* Verbs/DevX Rx queue elements. */
178 struct mlx5_rxq_obj {
179 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
180 rte_atomic32_t refcnt; /* Reference counter. */
181 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
182 struct ibv_cq *cq; /* Completion Queue. */
183 enum mlx5_rxq_obj_type type;
186 struct ibv_wq *wq; /* Work Queue. */
187 struct mlx5_devx_obj *rq; /* DevX object for Rx Queue. */
189 struct ibv_comp_channel *channel;
192 /* RX queue control descriptor. */
193 struct mlx5_rxq_ctrl {
194 struct mlx5_rxq_data rxq; /* Data path structure. */
195 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
196 rte_atomic32_t refcnt; /* Reference counter. */
197 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
198 struct mlx5_priv *priv; /* Back pointer to private data. */
199 enum mlx5_rxq_type type; /* Rxq type. */
200 unsigned int socket; /* CPU socket ID for allocations. */
201 unsigned int irq:1; /* Whether IRQ is enabled. */
202 unsigned int dbr_umem_id_valid:1; /* dbr_umem_id holds a valid value. */
203 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
204 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
205 uint32_t wqn; /* WQ number. */
206 uint16_t dump_file_n; /* Number of dump files. */
207 uint32_t dbr_umem_id; /* Storing door-bell information, */
208 uint64_t dbr_offset; /* needed when freeing door-bell. */
209 struct mlx5dv_devx_umem *wq_umem; /* WQ buffer registration info. */
210 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
213 enum mlx5_ind_tbl_type {
214 MLX5_IND_TBL_TYPE_IBV,
215 MLX5_IND_TBL_TYPE_DEVX,
218 /* Indirection table. */
219 struct mlx5_ind_table_obj {
220 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
221 rte_atomic32_t refcnt; /* Reference counter. */
222 enum mlx5_ind_tbl_type type;
225 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
226 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
228 uint32_t queues_n; /**< Number of queues in the list. */
229 uint16_t queues[]; /**< Queue list. */
234 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
235 rte_atomic32_t refcnt; /* Reference counter. */
236 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
239 struct ibv_qp *qp; /* Verbs queue pair. */
240 struct mlx5_devx_obj *tir; /* DevX TIR object. */
242 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
243 void *action; /* DV QP action pointer. */
245 uint64_t hash_fields; /* Verbs Hash fields. */
246 uint32_t rss_key_len; /* Hash key length in bytes. */
247 uint8_t rss_key[]; /* Hash key. */
250 /* TX queue send local data. */
252 struct mlx5_txq_local {
253 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
254 struct rte_mbuf *mbuf; /* first mbuf to process. */
255 uint16_t pkts_copy; /* packets copied to elts. */
256 uint16_t pkts_sent; /* packets sent. */
257 uint16_t pkts_loop; /* packets sent on loop entry. */
258 uint16_t elts_free; /* available elts remain. */
259 uint16_t wqe_free; /* available wqe remain. */
260 uint16_t mbuf_off; /* data offset in current mbuf. */
261 uint16_t mbuf_nseg; /* number of remaining mbuf. */
264 /* TX queue descriptor. */
266 struct mlx5_txq_data {
267 uint16_t elts_head; /* Current counter in (*elts)[]. */
268 uint16_t elts_tail; /* Counter of first element awaiting completion. */
269 uint16_t elts_comp; /* elts index since last completion request. */
270 uint16_t elts_s; /* Number of mbuf elements. */
271 uint16_t elts_m; /* Mask for mbuf elements indices. */
272 /* Fields related to elts mbuf storage. */
273 uint16_t wqe_ci; /* Consumer index for work queue. */
274 uint16_t wqe_pi; /* Producer index for work queue. */
275 uint16_t wqe_s; /* Number of WQ elements. */
276 uint16_t wqe_m; /* Mask Number for WQ elements. */
277 uint16_t wqe_comp; /* WQE index since last completion request. */
278 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
279 /* WQ related fields. */
280 uint16_t cq_ci; /* Consumer index for completion queue. */
281 uint16_t cq_pi; /* Production index for completion queue. */
282 uint16_t cqe_s; /* Number of CQ elements. */
283 uint16_t cqe_m; /* Mask for CQ indices. */
284 /* CQ related fields. */
285 uint16_t elts_n:4; /* elts[] length (in log2). */
286 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
287 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
288 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
289 uint16_t tunnel_en:1;
290 /* When set TX offload for tunneled packets are supported. */
291 uint16_t swp_en:1; /* Whether SW parser is enabled. */
292 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
293 uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */
294 uint16_t db_heu:1; /* Doorbell heuristic write barrier. */
295 uint16_t inlen_send; /* Ordinary send data inline size. */
296 uint16_t inlen_empw; /* eMPW max packet size to inline. */
297 uint16_t inlen_mode; /* Minimal data length to inline. */
298 uint32_t qp_num_8s; /* QP number shifted by 8. */
299 uint64_t offloads; /* Offloads for Tx Queue. */
300 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
301 struct mlx5_wqe *wqes; /* Work queue. */
302 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
303 #ifdef RTE_LIBRTE_MLX5_DEBUG
304 uint32_t *fcqs; /* Free completion queue (debug extended). */
306 uint16_t *fcqs; /* Free completion queue. */
308 volatile struct mlx5_cqe *cqes; /* Completion queue. */
309 volatile uint32_t *qp_db; /* Work queue doorbell. */
310 volatile uint32_t *cq_db; /* Completion queue doorbell. */
311 uint16_t port_id; /* Port ID of device. */
312 uint16_t idx; /* Queue index. */
313 struct mlx5_txq_stats stats; /* TX queue counters. */
315 rte_spinlock_t *uar_lock;
316 /* UAR access lock required for 32bit implementations */
318 struct rte_mbuf *elts[0];
319 /* Storage for queued packets, must be the last field. */
320 } __rte_cache_aligned;
322 enum mlx5_txq_obj_type {
323 MLX5_TXQ_OBJ_TYPE_IBV, /* mlx5_txq_obj with ibv_wq. */
324 MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN,
325 /* mlx5_txq_obj with mlx5_devx_tq and hairpin support. */
329 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
330 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
333 /* Verbs/DevX Tx queue elements. */
334 struct mlx5_txq_obj {
335 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
336 rte_atomic32_t refcnt; /* Reference counter. */
337 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
338 enum mlx5_txq_obj_type type; /* The txq object type. */
342 struct ibv_cq *cq; /* Completion Queue. */
343 struct ibv_qp *qp; /* Queue Pair. */
346 struct mlx5_devx_obj *sq;
347 /* DevX object for Sx queue. */
348 struct mlx5_devx_obj *tis; /* The TIS object. */
353 /* TX queue control descriptor. */
354 struct mlx5_txq_ctrl {
355 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
356 rte_atomic32_t refcnt; /* Reference counter. */
357 unsigned int socket; /* CPU socket ID for allocations. */
358 enum mlx5_txq_type type; /* The txq ctrl type. */
359 unsigned int max_inline_data; /* Max inline data. */
360 unsigned int max_tso_header; /* Max TSO header size. */
361 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */
362 struct mlx5_priv *priv; /* Back pointer to private data. */
363 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
364 void *bf_reg; /* BlueFlame register from Verbs. */
365 uint16_t dump_file_n; /* Number of dump files. */
366 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
367 struct mlx5_txq_data txq; /* Data path structure. */
368 /* Must be the last field in the structure, contains elts[]. */
371 #define MLX5_TX_BFREG(txq) \
372 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
376 extern uint8_t rss_hash_default_key[];
378 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
379 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
380 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
381 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
382 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
383 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
384 unsigned int socket, const struct rte_eth_rxconf *conf,
385 struct rte_mempool *mp);
386 int mlx5_rx_hairpin_queue_setup
387 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
388 const struct rte_eth_hairpin_conf *hairpin_conf);
389 void mlx5_rx_queue_release(void *dpdk_rxq);
390 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
391 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
392 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
393 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
394 struct mlx5_rxq_obj *mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
395 enum mlx5_rxq_obj_type type);
396 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
397 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
398 uint16_t desc, unsigned int socket,
399 const struct rte_eth_rxconf *conf,
400 struct rte_mempool *mp);
401 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new
402 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
403 const struct rte_eth_hairpin_conf *hairpin_conf);
404 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
405 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
406 int mlx5_rxq_verify(struct rte_eth_dev *dev);
407 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
408 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
409 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
410 const uint8_t *rss_key, uint32_t rss_key_len,
411 uint64_t hash_fields,
412 const uint16_t *queues, uint32_t queues_n,
413 int tunnel __rte_unused);
414 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
415 const uint8_t *rss_key, uint32_t rss_key_len,
416 uint64_t hash_fields,
417 const uint16_t *queues, uint32_t queues_n);
418 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
419 int mlx5_hrxq_verify(struct rte_eth_dev *dev);
420 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx);
421 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
422 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
423 uint64_t mlx5_get_rx_port_offloads(void);
424 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
428 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
429 unsigned int socket, const struct rte_eth_txconf *conf);
430 int mlx5_tx_hairpin_queue_setup
431 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
432 const struct rte_eth_hairpin_conf *hairpin_conf);
433 void mlx5_tx_queue_release(void *dpdk_txq);
434 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
435 struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
436 enum mlx5_txq_obj_type type);
437 struct mlx5_txq_obj *mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx);
438 int mlx5_txq_obj_release(struct mlx5_txq_obj *txq_ibv);
439 int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
440 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
441 uint16_t desc, unsigned int socket,
442 const struct rte_eth_txconf *conf);
443 struct mlx5_txq_ctrl *mlx5_txq_hairpin_new
444 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
445 const struct rte_eth_hairpin_conf *hairpin_conf);
446 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
447 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
448 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
449 int mlx5_txq_verify(struct rte_eth_dev *dev);
450 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
451 void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);
452 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
456 extern uint32_t mlx5_ptype_table[];
457 extern uint8_t mlx5_cksum_table[];
458 extern uint8_t mlx5_swp_types_table[];
460 void mlx5_set_ptype_table(void);
461 void mlx5_set_cksum_table(void);
462 void mlx5_set_swp_types_table(void);
463 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
464 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
465 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);
466 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
467 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
468 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
470 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
472 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
474 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
475 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
476 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
477 void mlx5_dump_debug_information(const char *path, const char *title,
478 const void *buf, unsigned int len);
479 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
480 const struct mlx5_mp_arg_queue_state_modify *sm);
481 void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
482 struct rte_eth_rxq_info *qinfo);
483 void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
484 struct rte_eth_txq_info *qinfo);
485 int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
486 struct rte_eth_burst_mode *mode);
487 int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
488 struct rte_eth_burst_mode *mode);
490 /* Vectorized version of mlx5_rxtx.c */
491 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
492 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
493 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
498 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
499 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
500 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
501 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
502 struct rte_mempool *mp);
503 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
505 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
509 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
510 * 64bit architectures.
513 * value to write in CPU endian format.
515 * Address to write to.
517 * Address of the lock to use for that UAR access.
519 static __rte_always_inline void
520 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
521 rte_spinlock_t *lock __rte_unused)
524 *(uint64_t *)addr = val;
525 #else /* !RTE_ARCH_64 */
526 rte_spinlock_lock(lock);
527 *(uint32_t *)addr = val;
529 *((uint32_t *)addr + 1) = val >> 32;
530 rte_spinlock_unlock(lock);
535 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
536 * 64bit architectures while guaranteeing the order of execution with the
537 * code being executed.
540 * value to write in CPU endian format.
542 * Address to write to.
544 * Address of the lock to use for that UAR access.
546 static __rte_always_inline void
547 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
550 __mlx5_uar_write64_relaxed(val, addr, lock);
553 /* Assist macros, used instead of directly calling the functions they wrap. */
555 #define mlx5_uar_write64_relaxed(val, dst, lock) \
556 __mlx5_uar_write64_relaxed(val, dst, NULL)
557 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
559 #define mlx5_uar_write64_relaxed(val, dst, lock) \
560 __mlx5_uar_write64_relaxed(val, dst, lock)
561 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
565 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
566 * cloned mbuf is allocated is returned instead.
572 * Memory pool where data is located for given mbuf.
574 static inline struct rte_mempool *
575 mlx5_mb2mp(struct rte_mbuf *buf)
577 if (unlikely(RTE_MBUF_CLONED(buf)))
578 return rte_mbuf_from_indirect(buf)->pool;
583 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
584 * as mempool is pre-configured and static.
587 * Pointer to Rx queue structure.
592 * Searched LKey on success, UINT32_MAX on no match.
594 static __rte_always_inline uint32_t
595 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
597 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
600 /* Linear search on MR cache array. */
601 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
602 MLX5_MR_CACHE_N, addr);
603 if (likely(lkey != UINT32_MAX))
605 /* Take slower bottom-half (Binary Search) on miss. */
606 return mlx5_rx_addr2mr_bh(rxq, addr);
609 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
612 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
615 * Pointer to Tx queue structure.
620 * Searched LKey on success, UINT32_MAX on no match.
622 static __rte_always_inline uint32_t
623 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
625 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
626 uintptr_t addr = (uintptr_t)mb->buf_addr;
629 /* Check generation bit to see if there's any change on existing MRs. */
630 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
631 mlx5_mr_flush_local_cache(mr_ctrl);
632 /* Linear search on MR cache array. */
633 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
634 MLX5_MR_CACHE_N, addr);
635 if (likely(lkey != UINT32_MAX))
637 /* Take slower bottom-half on miss. */
638 return mlx5_tx_mb2mr_bh(txq, mb);
642 * Ring TX queue doorbell and flush the update if requested.
645 * Pointer to TX queue structure.
647 * Pointer to the last WQE posted in the NIC.
649 * Request for write memory barrier after BlueFlame update.
651 static __rte_always_inline void
652 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
655 uint64_t *dst = MLX5_TX_BFREG(txq);
656 volatile uint64_t *src = ((volatile uint64_t *)wqe);
659 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
660 /* Ensure ordering between DB record and BF copy. */
662 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
668 * Ring TX queue doorbell and flush the update by write memory barrier.
671 * Pointer to TX queue structure.
673 * Pointer to the last WQE posted in the NIC.
675 static __rte_always_inline void
676 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
678 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
681 #endif /* RTE_PMD_MLX5_RXTX_H_ */