1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
29 #include <rte_spinlock.h>
32 #include "mlx5_utils.h"
35 #include "mlx5_autoconf.h"
36 #include "mlx5_defs.h"
39 /* Support tunnel matching. */
40 #define MLX5_FLOW_TUNNEL 5
42 struct mlx5_rxq_stats {
43 unsigned int idx; /**< Mapping index. */
44 #ifdef MLX5_PMD_SOFT_COUNTERS
45 uint64_t ipackets; /**< Total of successfully received packets. */
46 uint64_t ibytes; /**< Total of successfully received bytes. */
48 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
49 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
52 struct mlx5_txq_stats {
53 unsigned int idx; /**< Mapping index. */
54 #ifdef MLX5_PMD_SOFT_COUNTERS
55 uint64_t opackets; /**< Total of successfully sent packets. */
56 uint64_t obytes; /**< Total of successfully sent bytes. */
58 uint64_t oerrors; /**< Total number of failed transmitted packets. */
63 /* Compressed CQE context. */
65 uint16_t ai; /* Array index. */
66 uint16_t ca; /* Current array index. */
67 uint16_t na; /* Next array index. */
68 uint16_t cq_ci; /* The next CQE. */
69 uint32_t cqe_cnt; /* Number of CQEs. */
72 /* Multi-Packet RQ buffer header. */
73 struct mlx5_mprq_buf {
74 struct rte_mempool *mp;
75 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
76 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
77 } __rte_cache_aligned;
79 /* Get pointer to the first stride. */
80 #define mlx5_mprq_buf_addr(ptr) ((ptr) + 1)
82 /* RX queue descriptor. */
83 struct mlx5_rxq_data {
84 unsigned int csum:1; /* Enable checksum offloading. */
85 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
86 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
87 unsigned int crc_present:1; /* CRC must be subtracted. */
88 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
89 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
90 unsigned int elts_n:4; /* Log 2 of Mbufs. */
91 unsigned int rss_hash:1; /* RSS hash result is enabled. */
92 unsigned int mark:1; /* Marked flow available on the queue. */
93 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
94 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
95 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
96 unsigned int :6; /* Remaining bits. */
97 volatile uint32_t *rq_db;
98 volatile uint32_t *cq_db;
101 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
104 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
105 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
107 volatile struct mlx5_cqe(*cqes)[];
108 struct rxq_zip zip; /* Compressed context. */
111 struct rte_mbuf *(*elts)[];
112 struct mlx5_mprq_buf *(*mprq_bufs)[];
114 struct rte_mempool *mp;
115 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
116 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
117 struct mlx5_rxq_stats stats;
118 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
119 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
120 void *cq_uar; /* CQ user access region. */
121 uint32_t cqn; /* CQ number. */
122 uint8_t cq_arm_sn; /* CQ arm seq number. */
124 rte_spinlock_t *uar_lock_cq;
125 /* CQ (UAR) access lock required for 32bit implementations */
127 uint32_t tunnel; /* Tunnel information. */
128 } __rte_cache_aligned;
130 /* Verbs Rx queue elements. */
131 struct mlx5_rxq_ibv {
132 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
133 rte_atomic32_t refcnt; /* Reference counter. */
134 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
135 struct ibv_cq *cq; /* Completion Queue. */
136 struct ibv_wq *wq; /* Work Queue. */
137 struct ibv_comp_channel *channel;
140 /* RX queue control descriptor. */
141 struct mlx5_rxq_ctrl {
142 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
143 rte_atomic32_t refcnt; /* Reference counter. */
144 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
145 struct priv *priv; /* Back pointer to private data. */
146 struct mlx5_rxq_data rxq; /* Data path structure. */
147 unsigned int socket; /* CPU socket ID for allocations. */
148 unsigned int irq:1; /* Whether IRQ is enabled. */
149 uint16_t idx; /* Queue index. */
150 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
151 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
154 /* Indirection table. */
155 struct mlx5_ind_table_ibv {
156 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
157 rte_atomic32_t refcnt; /* Reference counter. */
158 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
159 uint32_t queues_n; /**< Number of queues in the list. */
160 uint16_t queues[]; /**< Queue list. */
165 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
166 rte_atomic32_t refcnt; /* Reference counter. */
167 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
168 struct ibv_qp *qp; /* Verbs queue pair. */
169 uint64_t hash_fields; /* Verbs Hash fields. */
170 uint32_t rss_key_len; /* Hash key length in bytes. */
171 uint8_t rss_key[]; /* Hash key. */
174 /* TX queue descriptor. */
176 struct mlx5_txq_data {
177 uint16_t elts_head; /* Current counter in (*elts)[]. */
178 uint16_t elts_tail; /* Counter of first element awaiting completion. */
179 uint16_t elts_comp; /* Counter since last completion request. */
180 uint16_t mpw_comp; /* WQ index since last completion request. */
181 uint16_t cq_ci; /* Consumer index for completion queue. */
183 uint16_t cq_pi; /* Producer index for completion queue. */
185 uint16_t wqe_ci; /* Consumer index for work queue. */
186 uint16_t wqe_pi; /* Producer index for work queue. */
187 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
188 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
189 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
190 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
191 uint16_t tunnel_en:1;
192 /* When set TX offload for tunneled packets are supported. */
193 uint16_t swp_en:1; /* Whether SW parser is enabled. */
194 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
195 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
196 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
197 uint32_t qp_num_8s; /* QP number shifted by 8. */
198 uint64_t offloads; /* Offloads for Tx Queue. */
199 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
200 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
201 volatile void *wqes; /* Work queue (use volatile to write into). */
202 volatile uint32_t *qp_db; /* Work queue doorbell. */
203 volatile uint32_t *cq_db; /* Completion queue doorbell. */
204 volatile void *bf_reg; /* Blueflame register remapped. */
205 struct rte_mbuf *(*elts)[]; /* TX elements. */
206 struct mlx5_txq_stats stats; /* TX queue counters. */
208 rte_spinlock_t *uar_lock;
209 /* UAR access lock required for 32bit implementations */
211 } __rte_cache_aligned;
213 /* Verbs Rx queue elements. */
214 struct mlx5_txq_ibv {
215 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
216 rte_atomic32_t refcnt; /* Reference counter. */
217 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
218 struct ibv_cq *cq; /* Completion Queue. */
219 struct ibv_qp *qp; /* Queue Pair. */
222 /* TX queue control descriptor. */
223 struct mlx5_txq_ctrl {
224 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
225 rte_atomic32_t refcnt; /* Reference counter. */
226 unsigned int socket; /* CPU socket ID for allocations. */
227 unsigned int max_inline_data; /* Max inline data. */
228 unsigned int max_tso_header; /* Max TSO header size. */
229 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
230 struct priv *priv; /* Back pointer to private data. */
231 struct mlx5_txq_data txq; /* Data path structure. */
232 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
233 volatile void *bf_reg_orig; /* Blueflame register from verbs. */
234 uint16_t idx; /* Queue index. */
239 extern uint8_t rss_hash_default_key[];
241 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
242 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
243 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
244 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
245 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
246 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl);
247 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
248 unsigned int socket, const struct rte_eth_rxconf *conf,
249 struct rte_mempool *mp);
250 void mlx5_rx_queue_release(void *dpdk_rxq);
251 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
252 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
253 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
254 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
255 struct mlx5_rxq_ibv *mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
256 struct mlx5_rxq_ibv *mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
257 int mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv);
258 int mlx5_rxq_ibv_releasable(struct mlx5_rxq_ibv *rxq_ibv);
259 struct mlx5_rxq_ibv *mlx5_rxq_ibv_drop_new(struct rte_eth_dev *dev);
260 void mlx5_rxq_ibv_drop_release(struct rte_eth_dev *dev);
261 int mlx5_rxq_ibv_verify(struct rte_eth_dev *dev);
262 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
263 uint16_t desc, unsigned int socket,
264 const struct rte_eth_rxconf *conf,
265 struct rte_mempool *mp);
266 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
267 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
268 int mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx);
269 int mlx5_rxq_verify(struct rte_eth_dev *dev);
270 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
271 int rxq_alloc_mprq_buf(struct mlx5_rxq_ctrl *rxq_ctrl);
272 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_new(struct rte_eth_dev *dev,
273 const uint16_t *queues,
275 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_get(struct rte_eth_dev *dev,
276 const uint16_t *queues,
278 int mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
279 struct mlx5_ind_table_ibv *ind_tbl);
280 int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev);
281 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_drop_new(struct rte_eth_dev *dev);
282 void mlx5_ind_table_ibv_drop_release(struct rte_eth_dev *dev);
283 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
284 const uint8_t *rss_key, uint32_t rss_key_len,
285 uint64_t hash_fields,
286 const uint16_t *queues, uint32_t queues_n);
287 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
288 const uint8_t *rss_key, uint32_t rss_key_len,
289 uint64_t hash_fields,
290 const uint16_t *queues, uint32_t queues_n);
291 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
292 int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev);
293 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
294 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
295 uint64_t mlx5_get_rx_port_offloads(void);
296 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
300 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
301 unsigned int socket, const struct rte_eth_txconf *conf);
302 void mlx5_tx_queue_release(void *dpdk_txq);
303 int mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd);
304 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
305 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
306 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
307 int mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv);
308 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
309 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
310 uint16_t desc, unsigned int socket,
311 const struct rte_eth_txconf *conf);
312 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
313 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
314 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
315 int mlx5_txq_verify(struct rte_eth_dev *dev);
316 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
317 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
321 extern uint32_t mlx5_ptype_table[];
322 extern uint8_t mlx5_cksum_table[];
323 extern uint8_t mlx5_swp_types_table[];
325 void mlx5_set_ptype_table(void);
326 void mlx5_set_cksum_table(void);
327 void mlx5_set_swp_types_table(void);
328 uint16_t mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
330 uint16_t mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts,
332 uint16_t mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
334 uint16_t mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts,
336 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
337 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
338 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
339 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
341 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
343 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
345 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
346 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
348 /* Vectorized version of mlx5_rxtx.c */
349 int mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev);
350 int mlx5_check_vec_tx_support(struct rte_eth_dev *dev);
351 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
352 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
353 uint16_t mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
355 uint16_t mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
357 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
362 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
363 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
364 uint32_t mlx5_tx_addr2mr_bh(struct mlx5_txq_data *txq, uintptr_t addr);
367 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
368 * 64bit architectures.
371 * value to write in CPU endian format.
373 * Address to write to.
375 * Address of the lock to use for that UAR access.
377 static __rte_always_inline void
378 __mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr,
379 rte_spinlock_t *lock __rte_unused)
382 rte_write64_relaxed(val, addr);
383 #else /* !RTE_ARCH_64 */
384 rte_spinlock_lock(lock);
385 rte_write32_relaxed(val, addr);
387 rte_write32_relaxed(val >> 32,
388 (volatile void *)((volatile char *)addr + 4));
389 rte_spinlock_unlock(lock);
394 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
395 * 64bit architectures while guaranteeing the order of execution with the
396 * code being executed.
399 * value to write in CPU endian format.
401 * Address to write to.
403 * Address of the lock to use for that UAR access.
405 static __rte_always_inline void
406 __mlx5_uar_write64(uint64_t val, volatile void *addr, rte_spinlock_t *lock)
409 __mlx5_uar_write64_relaxed(val, addr, lock);
412 /* Assist macros, used instead of directly calling the functions they wrap. */
414 #define mlx5_uar_write64_relaxed(val, dst, lock) \
415 __mlx5_uar_write64_relaxed(val, dst, NULL)
416 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
418 #define mlx5_uar_write64_relaxed(val, dst, lock) \
419 __mlx5_uar_write64_relaxed(val, dst, lock)
420 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
425 * Verify or set magic value in CQE.
434 check_cqe_seen(volatile struct mlx5_cqe *cqe)
436 static const uint8_t magic[] = "seen";
437 volatile uint8_t (*buf)[sizeof(cqe->rsvd1)] = &cqe->rsvd1;
441 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
442 if (!ret || (*buf)[i] != magic[i]) {
444 (*buf)[i] = magic[i];
451 * Check whether CQE is valid.
456 * Size of completion queue.
461 * 0 on success, 1 on failure.
463 static __rte_always_inline int
464 check_cqe(volatile struct mlx5_cqe *cqe,
465 unsigned int cqes_n, const uint16_t ci)
467 uint16_t idx = ci & cqes_n;
468 uint8_t op_own = cqe->op_own;
469 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
470 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
472 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
473 return 1; /* No CQE. */
475 if ((op_code == MLX5_CQE_RESP_ERR) ||
476 (op_code == MLX5_CQE_REQ_ERR)) {
477 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
478 uint8_t syndrome = err_cqe->syndrome;
480 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
481 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
483 if (!check_cqe_seen(cqe)) {
485 "unexpected CQE error %u (0x%02x) syndrome"
487 op_code, op_code, syndrome);
488 rte_hexdump(stderr, "MLX5 Error CQE:",
489 (const void *)((uintptr_t)err_cqe),
493 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
494 (op_code != MLX5_CQE_REQ)) {
495 if (!check_cqe_seen(cqe)) {
496 DRV_LOG(ERR, "unexpected CQE opcode %u (0x%02x)",
498 rte_hexdump(stderr, "MLX5 CQE:",
499 (const void *)((uintptr_t)cqe),
509 * Return the address of the WQE.
512 * Pointer to TX queue structure.
514 * WQE consumer index.
519 static inline uintptr_t *
520 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
522 ci &= ((1 << txq->wqe_n) - 1);
523 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
527 * Manage TX completions.
529 * When sending a burst, mlx5_tx_burst() posts several WRs.
532 * Pointer to TX queue structure.
534 static __rte_always_inline void
535 mlx5_tx_complete(struct mlx5_txq_data *txq)
537 const uint16_t elts_n = 1 << txq->elts_n;
538 const uint16_t elts_m = elts_n - 1;
539 const unsigned int cqe_n = 1 << txq->cqe_n;
540 const unsigned int cqe_cnt = cqe_n - 1;
541 uint16_t elts_free = txq->elts_tail;
543 uint16_t cq_ci = txq->cq_ci;
544 volatile struct mlx5_cqe *cqe = NULL;
545 volatile struct mlx5_wqe_ctrl *ctrl;
546 struct rte_mbuf *m, *free[elts_n];
547 struct rte_mempool *pool = NULL;
548 unsigned int blk_n = 0;
550 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
551 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
554 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
555 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
556 if (!check_cqe_seen(cqe)) {
557 DRV_LOG(ERR, "unexpected error CQE, Tx stopped");
558 rte_hexdump(stderr, "MLX5 TXQ:",
559 (const void *)((uintptr_t)txq->wqes),
567 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
568 ctrl = (volatile struct mlx5_wqe_ctrl *)
569 tx_mlx5_wqe(txq, txq->wqe_pi);
570 elts_tail = ctrl->ctrl3;
571 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
573 while (elts_free != elts_tail) {
574 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
575 if (likely(m != NULL)) {
576 if (likely(m->pool == pool)) {
579 if (likely(pool != NULL))
580 rte_mempool_put_bulk(pool,
590 rte_mempool_put_bulk(pool, (void *)free, blk_n);
592 elts_free = txq->elts_tail;
594 while (elts_free != elts_tail) {
595 memset(&(*txq->elts)[elts_free & elts_m],
597 sizeof((*txq->elts)[elts_free & elts_m]));
602 txq->elts_tail = elts_tail;
603 /* Update the consumer index. */
604 rte_compiler_barrier();
605 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
609 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
610 * as mempool is pre-configured and static.
613 * Pointer to Rx queue structure.
618 * Searched LKey on success, UINT32_MAX on no match.
620 static __rte_always_inline uint32_t
621 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
623 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
626 /* Linear search on MR cache array. */
627 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
628 MLX5_MR_CACHE_N, addr);
629 if (likely(lkey != UINT32_MAX))
631 /* Take slower bottom-half (Binary Search) on miss. */
632 return mlx5_rx_addr2mr_bh(rxq, addr);
635 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
638 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
641 * Pointer to Tx queue structure.
646 * Searched LKey on success, UINT32_MAX on no match.
648 static __rte_always_inline uint32_t
649 mlx5_tx_addr2mr(struct mlx5_txq_data *txq, uintptr_t addr)
651 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
654 /* Check generation bit to see if there's any change on existing MRs. */
655 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
656 mlx5_mr_flush_local_cache(mr_ctrl);
657 /* Linear search on MR cache array. */
658 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
659 MLX5_MR_CACHE_N, addr);
660 if (likely(lkey != UINT32_MAX))
662 /* Take slower bottom-half (binary search) on miss. */
663 return mlx5_tx_addr2mr_bh(txq, addr);
666 #define mlx5_tx_mb2mr(rxq, mb) mlx5_tx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
669 * Ring TX queue doorbell and flush the update if requested.
672 * Pointer to TX queue structure.
674 * Pointer to the last WQE posted in the NIC.
676 * Request for write memory barrier after BlueFlame update.
678 static __rte_always_inline void
679 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
682 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
683 volatile uint64_t *src = ((volatile uint64_t *)wqe);
686 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
687 /* Ensure ordering between DB record and BF copy. */
689 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
695 * Ring TX queue doorbell and flush the update by write memory barrier.
698 * Pointer to TX queue structure.
700 * Pointer to the last WQE posted in the NIC.
702 static __rte_always_inline void
703 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
705 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
709 * Convert mbuf to Verb SWP.
712 * Pointer to the Tx queue.
714 * Pointer to the mbuf.
716 * TSO offloads enabled.
718 * VLAN offloads enabled
720 * Pointer to the SWP header offsets.
722 * Pointer to the SWP header types.
724 static __rte_always_inline void
725 txq_mbuf_to_swp(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
726 uint8_t *offsets, uint8_t *swp_types)
728 const uint64_t vlan = buf->ol_flags & PKT_TX_VLAN_PKT;
729 const uint64_t tunnel = buf->ol_flags & PKT_TX_TUNNEL_MASK;
730 const uint64_t tso = buf->ol_flags & PKT_TX_TCP_SEG;
731 const uint64_t csum_flags = buf->ol_flags & PKT_TX_L4_MASK;
732 const uint64_t inner_ip =
733 buf->ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6);
734 const uint64_t ol_flags_mask = PKT_TX_L4_MASK | PKT_TX_IPV6 |
739 if (likely(!txq->swp_en || (tunnel != PKT_TX_TUNNEL_UDP &&
740 tunnel != PKT_TX_TUNNEL_IP)))
743 * The index should have:
744 * bit[0:1] = PKT_TX_L4_MASK
745 * bit[4] = PKT_TX_IPV6
746 * bit[8] = PKT_TX_OUTER_IPV6
747 * bit[9] = PKT_TX_OUTER_UDP
749 idx = (buf->ol_flags & ol_flags_mask) >> 52;
750 if (tunnel == PKT_TX_TUNNEL_UDP)
752 *swp_types = mlx5_swp_types_table[idx];
754 * Set offsets for SW parser. Since ConnectX-5, SW parser just
755 * complements HW parser. SW parser starts to engage only if HW parser
756 * can't reach a header. For the older devices, HW parser will not kick
757 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
758 * should be set regardless of HW offload.
760 off = buf->outer_l2_len + (vlan ? sizeof(struct vlan_hdr) : 0);
761 offsets[1] = off >> 1; /* Outer L3 offset. */
762 off += buf->outer_l3_len;
763 if (tunnel == PKT_TX_TUNNEL_UDP)
764 offsets[0] = off >> 1; /* Outer L4 offset. */
767 offsets[3] = off >> 1; /* Inner L3 offset. */
768 if (csum_flags == PKT_TX_TCP_CKSUM || tso ||
769 csum_flags == PKT_TX_UDP_CKSUM) {
771 offsets[2] = off >> 1; /* Inner L4 offset. */
777 * Convert the Checksum offloads to Verbs.
780 * Pointer to the mbuf.
783 * Converted checksum flags.
785 static __rte_always_inline uint8_t
786 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
789 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
790 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
791 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
794 * The index should have:
795 * bit[0] = PKT_TX_TCP_SEG
796 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
797 * bit[4] = PKT_TX_IP_CKSUM
798 * bit[8] = PKT_TX_OUTER_IP_CKSUM
801 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
802 return mlx5_cksum_table[idx];
806 * Count the number of contiguous single segment packets.
809 * Pointer to array of packets.
814 * Number of contiguous single segment packets.
816 static __rte_always_inline unsigned int
817 txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
823 /* Count the number of contiguous single segment packets. */
824 for (pos = 0; pos < pkts_n; ++pos)
825 if (NB_SEGS(pkts[pos]) > 1)
831 * Count the number of contiguous multi-segment packets.
834 * Pointer to array of packets.
839 * Number of contiguous multi-segment packets.
841 static __rte_always_inline unsigned int
842 txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
848 /* Count the number of contiguous multi-segment packets. */
849 for (pos = 0; pos < pkts_n; ++pos)
850 if (NB_SEGS(pkts[pos]) == 1)
855 #endif /* RTE_PMD_MLX5_RXTX_H_ */