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34 #ifndef RTE_PMD_MLX5_RXTX_H_
35 #define RTE_PMD_MLX5_RXTX_H_
39 #include <sys/queue.h>
42 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
44 #pragma GCC diagnostic ignored "-Wpedantic"
46 #include <infiniband/verbs.h>
47 #include <infiniband/mlx5dv.h>
49 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_mempool.h>
54 #include <rte_common.h>
55 #include <rte_hexdump.h>
56 #include <rte_atomic.h>
58 #include "mlx5_utils.h"
60 #include "mlx5_autoconf.h"
61 #include "mlx5_defs.h"
64 struct mlx5_rxq_stats {
65 unsigned int idx; /**< Mapping index. */
66 #ifdef MLX5_PMD_SOFT_COUNTERS
67 uint64_t ipackets; /**< Total of successfully received packets. */
68 uint64_t ibytes; /**< Total of successfully received bytes. */
70 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
71 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
74 struct mlx5_txq_stats {
75 unsigned int idx; /**< Mapping index. */
76 #ifdef MLX5_PMD_SOFT_COUNTERS
77 uint64_t opackets; /**< Total of successfully sent packets. */
78 uint64_t obytes; /**< Total of successfully sent bytes. */
80 uint64_t oerrors; /**< Total number of failed transmitted packets. */
85 /* Memory region queue object. */
87 LIST_ENTRY(mlx5_mr) next; /**< Pointer to the next element. */
88 rte_atomic32_t refcnt; /*<< Reference counter. */
89 uint32_t lkey; /*<< rte_cpu_to_be_32(mr->lkey) */
90 uintptr_t start; /* Start address of MR */
91 uintptr_t end; /* End address of MR */
92 struct ibv_mr *mr; /*<< Memory Region. */
93 struct rte_mempool *mp; /*<< Memory Pool. */
96 /* Compressed CQE context. */
98 uint16_t ai; /* Array index. */
99 uint16_t ca; /* Current array index. */
100 uint16_t na; /* Next array index. */
101 uint16_t cq_ci; /* The next CQE. */
102 uint32_t cqe_cnt; /* Number of CQEs. */
105 /* RX queue descriptor. */
106 struct mlx5_rxq_data {
107 unsigned int csum:1; /* Enable checksum offloading. */
108 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
109 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
110 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
111 unsigned int crc_present:1; /* CRC must be subtracted. */
112 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
113 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
114 unsigned int elts_n:4; /* Log 2 of Mbufs. */
115 unsigned int rss_hash:1; /* RSS hash result is enabled. */
116 unsigned int mark:1; /* Marked flow available on the queue. */
117 unsigned int pending_err:1; /* CQE error needs to be handled. */
118 unsigned int :14; /* Remaining bits. */
119 volatile uint32_t *rq_db;
120 volatile uint32_t *cq_db;
125 volatile struct mlx5_wqe_data_seg(*wqes)[];
126 volatile struct mlx5_cqe(*cqes)[];
127 struct rxq_zip zip; /* Compressed context. */
128 struct rte_mbuf *(*elts)[];
129 struct rte_mempool *mp;
130 struct mlx5_rxq_stats stats;
131 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
132 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
133 void *cq_uar; /* CQ user access region. */
134 uint32_t cqn; /* CQ number. */
135 uint8_t cq_arm_sn; /* CQ arm seq number. */
136 } __rte_cache_aligned;
138 /* Verbs Rx queue elements. */
139 struct mlx5_rxq_ibv {
140 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
141 rte_atomic32_t refcnt; /* Reference counter. */
142 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
143 struct ibv_cq *cq; /* Completion Queue. */
144 struct ibv_wq *wq; /* Work Queue. */
145 struct ibv_comp_channel *channel;
146 struct mlx5_mr *mr; /* Memory Region (for mp). */
149 /* RX queue control descriptor. */
150 struct mlx5_rxq_ctrl {
151 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
152 rte_atomic32_t refcnt; /* Reference counter. */
153 struct priv *priv; /* Back pointer to private data. */
154 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
155 struct mlx5_rxq_data rxq; /* Data path structure. */
156 unsigned int socket; /* CPU socket ID for allocations. */
157 unsigned int irq:1; /* Whether IRQ is enabled. */
160 /* Indirection table. */
161 struct mlx5_ind_table_ibv {
162 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
163 rte_atomic32_t refcnt; /* Reference counter. */
164 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
165 uint16_t queues_n; /**< Number of queues in the list. */
166 uint16_t queues[]; /**< Queue list. */
171 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
172 rte_atomic32_t refcnt; /* Reference counter. */
173 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
174 struct ibv_qp *qp; /* Verbs queue pair. */
175 uint64_t hash_fields; /* Verbs Hash fields. */
176 uint8_t rss_key_len; /* Hash key length in bytes. */
177 uint8_t rss_key[]; /* Hash key. */
180 /* TX queue descriptor. */
182 struct mlx5_txq_data {
183 uint16_t elts_head; /* Current counter in (*elts)[]. */
184 uint16_t elts_tail; /* Counter of first element awaiting completion. */
185 uint16_t elts_comp; /* Counter since last completion request. */
186 uint16_t mpw_comp; /* WQ index since last completion request. */
187 uint16_t cq_ci; /* Consumer index for completion queue. */
188 uint16_t cq_pi; /* Producer index for completion queue. */
189 uint16_t wqe_ci; /* Consumer index for work queue. */
190 uint16_t wqe_pi; /* Producer index for work queue. */
191 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
192 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
193 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
194 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
195 uint16_t tunnel_en:1;
196 /* When set TX offload for tunneled packets are supported. */
197 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
198 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
199 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
200 uint16_t mr_cache_idx; /* Index of last hit entry. */
201 uint32_t qp_num_8s; /* QP number shifted by 8. */
202 uint32_t flags; /* Flags for Tx Queue. */
203 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
204 volatile void *wqes; /* Work queue (use volatile to write into). */
205 volatile uint32_t *qp_db; /* Work queue doorbell. */
206 volatile uint32_t *cq_db; /* Completion queue doorbell. */
207 volatile void *bf_reg; /* Blueflame register. */
208 struct mlx5_mr *mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MR translation table. */
209 struct rte_mbuf *(*elts)[]; /* TX elements. */
210 struct mlx5_txq_stats stats; /* TX queue counters. */
211 } __rte_cache_aligned;
213 /* Verbs Rx queue elements. */
214 struct mlx5_txq_ibv {
215 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
216 rte_atomic32_t refcnt; /* Reference counter. */
217 struct ibv_cq *cq; /* Completion Queue. */
218 struct ibv_qp *qp; /* Queue Pair. */
221 /* TX queue control descriptor. */
222 struct mlx5_txq_ctrl {
223 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
224 rte_atomic32_t refcnt; /* Reference counter. */
225 struct priv *priv; /* Back pointer to private data. */
226 unsigned int socket; /* CPU socket ID for allocations. */
227 unsigned int max_inline_data; /* Max inline data. */
228 unsigned int max_tso_header; /* Max TSO header size. */
229 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
230 struct mlx5_txq_data txq; /* Data path structure. */
231 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
236 extern uint8_t rss_hash_default_key[];
237 extern const size_t rss_hash_default_key_len;
239 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *);
240 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
241 const struct rte_eth_rxconf *, struct rte_mempool *);
242 void mlx5_rx_queue_release(void *);
243 int priv_rx_intr_vec_enable(struct priv *priv);
244 void priv_rx_intr_vec_disable(struct priv *priv);
245 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
246 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
247 struct mlx5_rxq_ibv *mlx5_priv_rxq_ibv_new(struct priv *, uint16_t);
248 struct mlx5_rxq_ibv *mlx5_priv_rxq_ibv_get(struct priv *, uint16_t);
249 int mlx5_priv_rxq_ibv_release(struct priv *, struct mlx5_rxq_ibv *);
250 int mlx5_priv_rxq_ibv_releasable(struct priv *, struct mlx5_rxq_ibv *);
251 int mlx5_priv_rxq_ibv_verify(struct priv *);
252 struct mlx5_rxq_ctrl *mlx5_priv_rxq_new(struct priv *, uint16_t,
253 uint16_t, unsigned int,
254 struct rte_mempool *);
255 struct mlx5_rxq_ctrl *mlx5_priv_rxq_get(struct priv *, uint16_t);
256 int mlx5_priv_rxq_release(struct priv *, uint16_t);
257 int mlx5_priv_rxq_releasable(struct priv *, uint16_t);
258 int mlx5_priv_rxq_verify(struct priv *);
259 int rxq_alloc_elts(struct mlx5_rxq_ctrl *);
260 struct mlx5_ind_table_ibv *mlx5_priv_ind_table_ibv_new(struct priv *,
263 struct mlx5_ind_table_ibv *mlx5_priv_ind_table_ibv_get(struct priv *,
266 int mlx5_priv_ind_table_ibv_release(struct priv *, struct mlx5_ind_table_ibv *);
267 int mlx5_priv_ind_table_ibv_verify(struct priv *);
268 struct mlx5_hrxq *mlx5_priv_hrxq_new(struct priv *, uint8_t *, uint8_t,
269 uint64_t, uint16_t [], uint16_t);
270 struct mlx5_hrxq *mlx5_priv_hrxq_get(struct priv *, uint8_t *, uint8_t,
271 uint64_t, uint16_t [], uint16_t);
272 int mlx5_priv_hrxq_release(struct priv *, struct mlx5_hrxq *);
273 int mlx5_priv_hrxq_ibv_verify(struct priv *);
277 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
278 const struct rte_eth_txconf *);
279 void mlx5_tx_queue_release(void *);
280 int priv_tx_uar_remap(struct priv *priv, int fd);
281 struct mlx5_txq_ibv *mlx5_priv_txq_ibv_new(struct priv *, uint16_t);
282 struct mlx5_txq_ibv *mlx5_priv_txq_ibv_get(struct priv *, uint16_t);
283 int mlx5_priv_txq_ibv_release(struct priv *, struct mlx5_txq_ibv *);
284 int mlx5_priv_txq_ibv_releasable(struct priv *, struct mlx5_txq_ibv *);
285 int mlx5_priv_txq_ibv_verify(struct priv *);
286 struct mlx5_txq_ctrl *mlx5_priv_txq_new(struct priv *, uint16_t,
287 uint16_t, unsigned int,
288 const struct rte_eth_txconf *);
289 struct mlx5_txq_ctrl *mlx5_priv_txq_get(struct priv *, uint16_t);
290 int mlx5_priv_txq_release(struct priv *, uint16_t);
291 int mlx5_priv_txq_releasable(struct priv *, uint16_t);
292 int mlx5_priv_txq_verify(struct priv *);
293 void txq_alloc_elts(struct mlx5_txq_ctrl *);
297 extern uint32_t mlx5_ptype_table[];
299 void mlx5_set_ptype_table(void);
300 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
301 uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
302 uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
303 uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t);
304 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
305 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
306 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
307 int mlx5_rx_descriptor_status(void *, uint16_t);
308 int mlx5_tx_descriptor_status(void *, uint16_t);
310 /* Vectorized version of mlx5_rxtx.c */
311 int priv_check_raw_vec_tx_support(struct priv *);
312 int priv_check_vec_tx_support(struct priv *);
313 int rxq_check_vec_support(struct mlx5_rxq_data *);
314 int priv_check_vec_rx_support(struct priv *);
315 uint16_t mlx5_tx_burst_raw_vec(void *, struct rte_mbuf **, uint16_t);
316 uint16_t mlx5_tx_burst_vec(void *, struct rte_mbuf **, uint16_t);
317 uint16_t mlx5_rx_burst_vec(void *, struct rte_mbuf **, uint16_t);
321 void mlx5_mp2mr_iter(struct rte_mempool *, void *);
322 struct mlx5_mr *priv_txq_mp2mr_reg(struct priv *priv, struct mlx5_txq_data *,
323 struct rte_mempool *, unsigned int);
324 struct mlx5_mr *mlx5_txq_mp2mr_reg(struct mlx5_txq_data *, struct rte_mempool *,
329 * Verify or set magic value in CQE.
338 check_cqe_seen(volatile struct mlx5_cqe *cqe)
340 static const uint8_t magic[] = "seen";
341 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
345 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
346 if (!ret || (*buf)[i] != magic[i]) {
348 (*buf)[i] = magic[i];
355 * Check whether CQE is valid.
360 * Size of completion queue.
365 * 0 on success, 1 on failure.
367 static __rte_always_inline int
368 check_cqe(volatile struct mlx5_cqe *cqe,
369 unsigned int cqes_n, const uint16_t ci)
371 uint16_t idx = ci & cqes_n;
372 uint8_t op_own = cqe->op_own;
373 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
374 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
376 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
377 return 1; /* No CQE. */
379 if ((op_code == MLX5_CQE_RESP_ERR) ||
380 (op_code == MLX5_CQE_REQ_ERR)) {
381 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
382 uint8_t syndrome = err_cqe->syndrome;
384 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
385 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
387 if (!check_cqe_seen(cqe)) {
388 ERROR("unexpected CQE error %u (0x%02x)"
390 op_code, op_code, syndrome);
391 rte_hexdump(stderr, "MLX5 Error CQE:",
392 (const void *)((uintptr_t)err_cqe),
396 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
397 (op_code != MLX5_CQE_REQ)) {
398 if (!check_cqe_seen(cqe)) {
399 ERROR("unexpected CQE opcode %u (0x%02x)",
401 rte_hexdump(stderr, "MLX5 CQE:",
402 (const void *)((uintptr_t)cqe),
412 * Return the address of the WQE.
415 * Pointer to TX queue structure.
417 * WQE consumer index.
422 static inline uintptr_t *
423 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
425 ci &= ((1 << txq->wqe_n) - 1);
426 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
430 * Manage TX completions.
432 * When sending a burst, mlx5_tx_burst() posts several WRs.
435 * Pointer to TX queue structure.
437 static __rte_always_inline void
438 mlx5_tx_complete(struct mlx5_txq_data *txq)
440 const uint16_t elts_n = 1 << txq->elts_n;
441 const uint16_t elts_m = elts_n - 1;
442 const unsigned int cqe_n = 1 << txq->cqe_n;
443 const unsigned int cqe_cnt = cqe_n - 1;
444 uint16_t elts_free = txq->elts_tail;
446 uint16_t cq_ci = txq->cq_ci;
447 volatile struct mlx5_cqe *cqe = NULL;
448 volatile struct mlx5_wqe_ctrl *ctrl;
449 struct rte_mbuf *m, *free[elts_n];
450 struct rte_mempool *pool = NULL;
451 unsigned int blk_n = 0;
453 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
454 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
457 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
458 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
459 if (!check_cqe_seen(cqe)) {
460 ERROR("unexpected error CQE, TX stopped");
461 rte_hexdump(stderr, "MLX5 TXQ:",
462 (const void *)((uintptr_t)txq->wqes),
470 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
471 ctrl = (volatile struct mlx5_wqe_ctrl *)
472 tx_mlx5_wqe(txq, txq->wqe_pi);
473 elts_tail = ctrl->ctrl3;
474 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
476 while (elts_free != elts_tail) {
477 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
478 if (likely(m != NULL)) {
479 if (likely(m->pool == pool)) {
482 if (likely(pool != NULL))
483 rte_mempool_put_bulk(pool,
493 rte_mempool_put_bulk(pool, (void *)free, blk_n);
495 elts_free = txq->elts_tail;
497 while (elts_free != elts_tail) {
498 memset(&(*txq->elts)[elts_free & elts_m],
500 sizeof((*txq->elts)[elts_free & elts_m]));
505 txq->elts_tail = elts_tail;
506 /* Update the consumer index. */
507 rte_compiler_barrier();
508 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
512 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
513 * the cloned mbuf is allocated is returned instead.
519 * Memory pool where data is located for given mbuf.
521 static struct rte_mempool *
522 mlx5_tx_mb2mp(struct rte_mbuf *buf)
524 if (unlikely(RTE_MBUF_INDIRECT(buf)))
525 return rte_mbuf_from_indirect(buf)->pool;
530 * Get Memory Region (MR) <-> rte_mbuf association from txq->mp2mr[].
531 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
532 * remove an entry first.
535 * Pointer to TX queue structure.
537 * Memory Pool for which a Memory Region lkey must be returned.
540 * mr->lkey on success, (uint32_t)-1 on failure.
542 static __rte_always_inline uint32_t
543 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
545 uint16_t i = txq->mr_cache_idx;
546 uintptr_t addr = rte_pktmbuf_mtod_offset(mb, uintptr_t, DATA_LEN(mb));
549 assert(i < RTE_DIM(txq->mp2mr));
550 if (likely(txq->mp2mr[i]->start <= addr && txq->mp2mr[i]->end >= addr))
551 return txq->mp2mr[i]->lkey;
552 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
553 if (unlikely(txq->mp2mr[i]->mr == NULL)) {
554 /* Unknown MP, add a new MR for it. */
557 if (txq->mp2mr[i]->start <= addr &&
558 txq->mp2mr[i]->end >= addr) {
559 assert(txq->mp2mr[i]->lkey != (uint32_t)-1);
560 assert(rte_cpu_to_be_32(txq->mp2mr[i]->mr->lkey) ==
561 txq->mp2mr[i]->lkey);
562 txq->mr_cache_idx = i;
563 return txq->mp2mr[i]->lkey;
566 txq->mr_cache_idx = 0;
567 mr = mlx5_txq_mp2mr_reg(txq, mlx5_tx_mb2mp(mb), i);
569 * Request the reference to use in this queue, the original one is
570 * kept by the control plane.
573 rte_atomic32_inc(&mr->refcnt);
580 * Ring TX queue doorbell and flush the update if requested.
583 * Pointer to TX queue structure.
585 * Pointer to the last WQE posted in the NIC.
587 * Request for write memory barrier after BlueFlame update.
589 static __rte_always_inline void
590 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
593 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
594 volatile uint64_t *src = ((volatile uint64_t *)wqe);
597 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
598 /* Ensure ordering between DB record and BF copy. */
606 * Ring TX queue doorbell and flush the update by write memory barrier.
609 * Pointer to TX queue structure.
611 * Pointer to the last WQE posted in the NIC.
613 static __rte_always_inline void
614 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
616 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
620 * Convert the Checksum offloads to Verbs.
623 * Pointer to the Tx queue.
625 * Pointer to the mbuf.
628 * the converted cs_flags.
630 static __rte_always_inline uint8_t
631 txq_ol_cksum_to_cs(struct mlx5_txq_data *txq_data, struct rte_mbuf *buf)
633 uint8_t cs_flags = 0;
635 /* Should we enable HW CKSUM offload */
637 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
638 if (txq_data->tunnel_en &&
640 (PKT_TX_TUNNEL_GRE | PKT_TX_TUNNEL_VXLAN))) {
641 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
642 MLX5_ETH_WQE_L4_INNER_CSUM;
643 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
644 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
646 cs_flags = MLX5_ETH_WQE_L3_CSUM |
647 MLX5_ETH_WQE_L4_CSUM;
653 #endif /* RTE_PMD_MLX5_RXTX_H_ */