1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
30 #include "mlx5_utils.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_defs.h"
37 /* Support tunnel matching. */
38 #define MLX5_FLOW_TUNNEL 2
40 struct mlx5_rxq_stats {
41 unsigned int idx; /**< Mapping index. */
42 #ifdef MLX5_PMD_SOFT_COUNTERS
43 uint64_t ipackets; /**< Total of successfully received packets. */
44 uint64_t ibytes; /**< Total of successfully received bytes. */
46 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
47 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
50 struct mlx5_txq_stats {
51 unsigned int idx; /**< Mapping index. */
52 #ifdef MLX5_PMD_SOFT_COUNTERS
53 uint64_t opackets; /**< Total of successfully sent packets. */
54 uint64_t obytes; /**< Total of successfully sent bytes. */
56 uint64_t oerrors; /**< Total number of failed transmitted packets. */
61 /* Compressed CQE context. */
63 uint16_t ai; /* Array index. */
64 uint16_t ca; /* Current array index. */
65 uint16_t na; /* Next array index. */
66 uint16_t cq_ci; /* The next CQE. */
67 uint32_t cqe_cnt; /* Number of CQEs. */
70 /* Multi-Packet RQ buffer header. */
71 struct mlx5_mprq_buf {
72 struct rte_mempool *mp;
73 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
74 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
75 } __rte_cache_aligned;
77 /* Get pointer to the first stride. */
78 #define mlx5_mprq_buf_addr(ptr) ((ptr) + 1)
80 /* RX queue descriptor. */
81 struct mlx5_rxq_data {
82 unsigned int csum:1; /* Enable checksum offloading. */
83 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
84 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
85 unsigned int crc_present:1; /* CRC must be subtracted. */
86 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
87 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
88 unsigned int elts_n:4; /* Log 2 of Mbufs. */
89 unsigned int rss_hash:1; /* RSS hash result is enabled. */
90 unsigned int mark:1; /* Marked flow available on the queue. */
91 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
92 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
93 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
94 unsigned int :6; /* Remaining bits. */
95 volatile uint32_t *rq_db;
96 volatile uint32_t *cq_db;
99 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
102 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
103 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
105 volatile struct mlx5_cqe(*cqes)[];
106 struct rxq_zip zip; /* Compressed context. */
109 struct rte_mbuf *(*elts)[];
110 struct mlx5_mprq_buf *(*mprq_bufs)[];
112 struct rte_mempool *mp;
113 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
114 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
115 struct mlx5_rxq_stats stats;
116 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
117 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
118 void *cq_uar; /* CQ user access region. */
119 uint32_t cqn; /* CQ number. */
120 uint8_t cq_arm_sn; /* CQ arm seq number. */
121 uint32_t tunnel; /* Tunnel information. */
122 } __rte_cache_aligned;
124 /* Verbs Rx queue elements. */
125 struct mlx5_rxq_ibv {
126 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
127 rte_atomic32_t refcnt; /* Reference counter. */
128 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
129 struct ibv_cq *cq; /* Completion Queue. */
130 struct ibv_wq *wq; /* Work Queue. */
131 struct ibv_comp_channel *channel;
134 /* RX queue control descriptor. */
135 struct mlx5_rxq_ctrl {
136 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
137 rte_atomic32_t refcnt; /* Reference counter. */
138 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
139 struct priv *priv; /* Back pointer to private data. */
140 struct mlx5_rxq_data rxq; /* Data path structure. */
141 unsigned int socket; /* CPU socket ID for allocations. */
142 unsigned int irq:1; /* Whether IRQ is enabled. */
143 uint16_t idx; /* Queue index. */
144 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
145 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
148 /* Indirection table. */
149 struct mlx5_ind_table_ibv {
150 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
151 rte_atomic32_t refcnt; /* Reference counter. */
152 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
153 uint32_t queues_n; /**< Number of queues in the list. */
154 uint16_t queues[]; /**< Queue list. */
159 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
160 rte_atomic32_t refcnt; /* Reference counter. */
161 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
162 struct ibv_qp *qp; /* Verbs queue pair. */
163 uint64_t hash_fields; /* Verbs Hash fields. */
164 uint32_t rss_key_len; /* Hash key length in bytes. */
165 uint8_t rss_key[]; /* Hash key. */
168 /* TX queue descriptor. */
170 struct mlx5_txq_data {
171 uint16_t elts_head; /* Current counter in (*elts)[]. */
172 uint16_t elts_tail; /* Counter of first element awaiting completion. */
173 uint16_t elts_comp; /* Counter since last completion request. */
174 uint16_t mpw_comp; /* WQ index since last completion request. */
175 uint16_t cq_ci; /* Consumer index for completion queue. */
177 uint16_t cq_pi; /* Producer index for completion queue. */
179 uint16_t wqe_ci; /* Consumer index for work queue. */
180 uint16_t wqe_pi; /* Producer index for work queue. */
181 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
182 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
183 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
184 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
185 uint16_t tunnel_en:1;
186 /* When set TX offload for tunneled packets are supported. */
187 uint16_t swp_en:1; /* Whether SW parser is enabled. */
188 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
189 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
190 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
191 uint32_t qp_num_8s; /* QP number shifted by 8. */
192 uint64_t offloads; /* Offloads for Tx Queue. */
193 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
194 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
195 volatile void *wqes; /* Work queue (use volatile to write into). */
196 volatile uint32_t *qp_db; /* Work queue doorbell. */
197 volatile uint32_t *cq_db; /* Completion queue doorbell. */
198 volatile void *bf_reg; /* Blueflame register remapped. */
199 struct rte_mbuf *(*elts)[]; /* TX elements. */
200 struct mlx5_txq_stats stats; /* TX queue counters. */
201 } __rte_cache_aligned;
203 /* Verbs Rx queue elements. */
204 struct mlx5_txq_ibv {
205 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
206 rte_atomic32_t refcnt; /* Reference counter. */
207 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
208 struct ibv_cq *cq; /* Completion Queue. */
209 struct ibv_qp *qp; /* Queue Pair. */
212 /* TX queue control descriptor. */
213 struct mlx5_txq_ctrl {
214 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
215 rte_atomic32_t refcnt; /* Reference counter. */
216 unsigned int socket; /* CPU socket ID for allocations. */
217 unsigned int max_inline_data; /* Max inline data. */
218 unsigned int max_tso_header; /* Max TSO header size. */
219 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
220 struct priv *priv; /* Back pointer to private data. */
221 struct mlx5_txq_data txq; /* Data path structure. */
222 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
223 volatile void *bf_reg_orig; /* Blueflame register from verbs. */
224 uint16_t idx; /* Queue index. */
229 extern uint8_t rss_hash_default_key[];
231 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
232 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
233 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
234 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
235 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
236 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl);
237 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
238 unsigned int socket, const struct rte_eth_rxconf *conf,
239 struct rte_mempool *mp);
240 void mlx5_rx_queue_release(void *dpdk_rxq);
241 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
242 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
243 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
244 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
245 struct mlx5_rxq_ibv *mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
246 struct mlx5_rxq_ibv *mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
247 int mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv);
248 int mlx5_rxq_ibv_releasable(struct mlx5_rxq_ibv *rxq_ibv);
249 struct mlx5_rxq_ibv *mlx5_rxq_ibv_drop_new(struct rte_eth_dev *dev);
250 void mlx5_rxq_ibv_drop_release(struct rte_eth_dev *dev);
251 int mlx5_rxq_ibv_verify(struct rte_eth_dev *dev);
252 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
253 uint16_t desc, unsigned int socket,
254 const struct rte_eth_rxconf *conf,
255 struct rte_mempool *mp);
256 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
257 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
258 int mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx);
259 int mlx5_rxq_verify(struct rte_eth_dev *dev);
260 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
261 int rxq_alloc_mprq_buf(struct mlx5_rxq_ctrl *rxq_ctrl);
262 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_new(struct rte_eth_dev *dev,
263 const uint16_t *queues,
265 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_get(struct rte_eth_dev *dev,
266 const uint16_t *queues,
268 int mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
269 struct mlx5_ind_table_ibv *ind_tbl);
270 int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev);
271 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_drop_new(struct rte_eth_dev *dev);
272 void mlx5_ind_table_ibv_drop_release(struct rte_eth_dev *dev);
273 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
274 const uint8_t *rss_key, uint32_t rss_key_len,
275 uint64_t hash_fields,
276 const uint16_t *queues, uint32_t queues_n);
277 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
278 const uint8_t *rss_key, uint32_t rss_key_len,
279 uint64_t hash_fields,
280 const uint16_t *queues, uint32_t queues_n);
281 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
282 int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev);
283 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
284 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
285 uint64_t mlx5_get_rx_port_offloads(void);
286 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
290 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
291 unsigned int socket, const struct rte_eth_txconf *conf);
292 void mlx5_tx_queue_release(void *dpdk_txq);
293 int mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd);
294 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
295 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
296 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
297 int mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv);
298 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
299 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
300 uint16_t desc, unsigned int socket,
301 const struct rte_eth_txconf *conf);
302 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
303 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
304 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
305 int mlx5_txq_verify(struct rte_eth_dev *dev);
306 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
307 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
311 extern uint32_t mlx5_ptype_table[];
312 extern uint8_t mlx5_cksum_table[];
313 extern uint8_t mlx5_swp_types_table[];
315 void mlx5_set_ptype_table(void);
316 void mlx5_set_cksum_table(void);
317 void mlx5_set_swp_types_table(void);
318 uint16_t mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
320 uint16_t mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts,
322 uint16_t mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
324 uint16_t mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts,
326 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
327 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
328 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
329 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
331 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
333 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
335 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
336 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
338 /* Vectorized version of mlx5_rxtx.c */
339 int mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev);
340 int mlx5_check_vec_tx_support(struct rte_eth_dev *dev);
341 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
342 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
343 uint16_t mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
345 uint16_t mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
347 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
352 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
353 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
354 uint32_t mlx5_tx_addr2mr_bh(struct mlx5_txq_data *txq, uintptr_t addr);
358 * Verify or set magic value in CQE.
367 check_cqe_seen(volatile struct mlx5_cqe *cqe)
369 static const uint8_t magic[] = "seen";
370 volatile uint8_t (*buf)[sizeof(cqe->rsvd1)] = &cqe->rsvd1;
374 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
375 if (!ret || (*buf)[i] != magic[i]) {
377 (*buf)[i] = magic[i];
384 * Check whether CQE is valid.
389 * Size of completion queue.
394 * 0 on success, 1 on failure.
396 static __rte_always_inline int
397 check_cqe(volatile struct mlx5_cqe *cqe,
398 unsigned int cqes_n, const uint16_t ci)
400 uint16_t idx = ci & cqes_n;
401 uint8_t op_own = cqe->op_own;
402 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
403 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
405 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
406 return 1; /* No CQE. */
408 if ((op_code == MLX5_CQE_RESP_ERR) ||
409 (op_code == MLX5_CQE_REQ_ERR)) {
410 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
411 uint8_t syndrome = err_cqe->syndrome;
413 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
414 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
416 if (!check_cqe_seen(cqe)) {
418 "unexpected CQE error %u (0x%02x) syndrome"
420 op_code, op_code, syndrome);
421 rte_hexdump(stderr, "MLX5 Error CQE:",
422 (const void *)((uintptr_t)err_cqe),
426 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
427 (op_code != MLX5_CQE_REQ)) {
428 if (!check_cqe_seen(cqe)) {
429 DRV_LOG(ERR, "unexpected CQE opcode %u (0x%02x)",
431 rte_hexdump(stderr, "MLX5 CQE:",
432 (const void *)((uintptr_t)cqe),
442 * Return the address of the WQE.
445 * Pointer to TX queue structure.
447 * WQE consumer index.
452 static inline uintptr_t *
453 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
455 ci &= ((1 << txq->wqe_n) - 1);
456 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
460 * Manage TX completions.
462 * When sending a burst, mlx5_tx_burst() posts several WRs.
465 * Pointer to TX queue structure.
467 static __rte_always_inline void
468 mlx5_tx_complete(struct mlx5_txq_data *txq)
470 const uint16_t elts_n = 1 << txq->elts_n;
471 const uint16_t elts_m = elts_n - 1;
472 const unsigned int cqe_n = 1 << txq->cqe_n;
473 const unsigned int cqe_cnt = cqe_n - 1;
474 uint16_t elts_free = txq->elts_tail;
476 uint16_t cq_ci = txq->cq_ci;
477 volatile struct mlx5_cqe *cqe = NULL;
478 volatile struct mlx5_wqe_ctrl *ctrl;
479 struct rte_mbuf *m, *free[elts_n];
480 struct rte_mempool *pool = NULL;
481 unsigned int blk_n = 0;
483 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
484 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
487 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
488 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
489 if (!check_cqe_seen(cqe)) {
490 DRV_LOG(ERR, "unexpected error CQE, Tx stopped");
491 rte_hexdump(stderr, "MLX5 TXQ:",
492 (const void *)((uintptr_t)txq->wqes),
500 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
501 ctrl = (volatile struct mlx5_wqe_ctrl *)
502 tx_mlx5_wqe(txq, txq->wqe_pi);
503 elts_tail = ctrl->ctrl3;
504 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
506 while (elts_free != elts_tail) {
507 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
508 if (likely(m != NULL)) {
509 if (likely(m->pool == pool)) {
512 if (likely(pool != NULL))
513 rte_mempool_put_bulk(pool,
523 rte_mempool_put_bulk(pool, (void *)free, blk_n);
525 elts_free = txq->elts_tail;
527 while (elts_free != elts_tail) {
528 memset(&(*txq->elts)[elts_free & elts_m],
530 sizeof((*txq->elts)[elts_free & elts_m]));
535 txq->elts_tail = elts_tail;
536 /* Update the consumer index. */
537 rte_compiler_barrier();
538 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
542 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
543 * as mempool is pre-configured and static.
546 * Pointer to Rx queue structure.
551 * Searched LKey on success, UINT32_MAX on no match.
553 static __rte_always_inline uint32_t
554 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
556 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
559 /* Linear search on MR cache array. */
560 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
561 MLX5_MR_CACHE_N, addr);
562 if (likely(lkey != UINT32_MAX))
564 /* Take slower bottom-half (Binary Search) on miss. */
565 return mlx5_rx_addr2mr_bh(rxq, addr);
568 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
571 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
574 * Pointer to Tx queue structure.
579 * Searched LKey on success, UINT32_MAX on no match.
581 static __rte_always_inline uint32_t
582 mlx5_tx_addr2mr(struct mlx5_txq_data *txq, uintptr_t addr)
584 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
587 /* Check generation bit to see if there's any change on existing MRs. */
588 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
589 mlx5_mr_flush_local_cache(mr_ctrl);
590 /* Linear search on MR cache array. */
591 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
592 MLX5_MR_CACHE_N, addr);
593 if (likely(lkey != UINT32_MAX))
595 /* Take slower bottom-half (binary search) on miss. */
596 return mlx5_tx_addr2mr_bh(txq, addr);
599 #define mlx5_tx_mb2mr(rxq, mb) mlx5_tx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
602 * Ring TX queue doorbell and flush the update if requested.
605 * Pointer to TX queue structure.
607 * Pointer to the last WQE posted in the NIC.
609 * Request for write memory barrier after BlueFlame update.
611 static __rte_always_inline void
612 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
615 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
616 volatile uint64_t *src = ((volatile uint64_t *)wqe);
619 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
620 /* Ensure ordering between DB record and BF copy. */
628 * Ring TX queue doorbell and flush the update by write memory barrier.
631 * Pointer to TX queue structure.
633 * Pointer to the last WQE posted in the NIC.
635 static __rte_always_inline void
636 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
638 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
642 * Convert mbuf to Verb SWP.
645 * Pointer to the Tx queue.
647 * Pointer to the mbuf.
649 * TSO offloads enabled.
651 * VLAN offloads enabled
653 * Pointer to the SWP header offsets.
655 * Pointer to the SWP header types.
657 static __rte_always_inline void
658 txq_mbuf_to_swp(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
659 uint8_t *offsets, uint8_t *swp_types)
661 const uint64_t vlan = buf->ol_flags & PKT_TX_VLAN_PKT;
662 const uint64_t tunnel = buf->ol_flags & PKT_TX_TUNNEL_MASK;
663 const uint64_t tso = buf->ol_flags & PKT_TX_TCP_SEG;
664 const uint64_t csum_flags = buf->ol_flags & PKT_TX_L4_MASK;
665 const uint64_t inner_ip =
666 buf->ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6);
667 const uint64_t ol_flags_mask = PKT_TX_L4_MASK | PKT_TX_IPV6 |
672 if (likely(!txq->swp_en || (tunnel != PKT_TX_TUNNEL_UDP &&
673 tunnel != PKT_TX_TUNNEL_IP)))
676 * The index should have:
677 * bit[0:1] = PKT_TX_L4_MASK
678 * bit[4] = PKT_TX_IPV6
679 * bit[8] = PKT_TX_OUTER_IPV6
680 * bit[9] = PKT_TX_OUTER_UDP
682 idx = (buf->ol_flags & ol_flags_mask) >> 52;
683 if (tunnel == PKT_TX_TUNNEL_UDP)
685 *swp_types = mlx5_swp_types_table[idx];
687 * Set offsets for SW parser. Since ConnectX-5, SW parser just
688 * complements HW parser. SW parser starts to engage only if HW parser
689 * can't reach a header. For the older devices, HW parser will not kick
690 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
691 * should be set regardless of HW offload.
693 off = buf->outer_l2_len + (vlan ? sizeof(struct vlan_hdr) : 0);
694 offsets[1] = off >> 1; /* Outer L3 offset. */
695 off += buf->outer_l3_len;
696 if (tunnel == PKT_TX_TUNNEL_UDP)
697 offsets[0] = off >> 1; /* Outer L4 offset. */
700 offsets[3] = off >> 1; /* Inner L3 offset. */
701 if (csum_flags == PKT_TX_TCP_CKSUM || tso ||
702 csum_flags == PKT_TX_UDP_CKSUM) {
704 offsets[2] = off >> 1; /* Inner L4 offset. */
710 * Convert the Checksum offloads to Verbs.
713 * Pointer to the mbuf.
716 * Converted checksum flags.
718 static __rte_always_inline uint8_t
719 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
722 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
723 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
724 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
727 * The index should have:
728 * bit[0] = PKT_TX_TCP_SEG
729 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
730 * bit[4] = PKT_TX_IP_CKSUM
731 * bit[8] = PKT_TX_OUTER_IP_CKSUM
734 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
735 return mlx5_cksum_table[idx];
739 * Count the number of contiguous single segment packets.
742 * Pointer to array of packets.
747 * Number of contiguous single segment packets.
749 static __rte_always_inline unsigned int
750 txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
756 /* Count the number of contiguous single segment packets. */
757 for (pos = 0; pos < pkts_n; ++pos)
758 if (NB_SEGS(pkts[pos]) > 1)
764 * Count the number of contiguous multi-segment packets.
767 * Pointer to array of packets.
772 * Number of contiguous multi-segment packets.
774 static __rte_always_inline unsigned int
775 txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
781 /* Count the number of contiguous multi-segment packets. */
782 for (pos = 0; pos < pkts_n; ++pos)
783 if (NB_SEGS(pkts[pos]) == 1)
788 #endif /* RTE_PMD_MLX5_RXTX_H_ */