1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
29 #include <rte_spinlock.h>
31 #include <rte_bus_pci.h>
32 #include <rte_malloc.h>
34 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
40 #include "mlx5_glue.h"
42 /* Support tunnel matching. */
43 #define MLX5_FLOW_TUNNEL 5
45 struct mlx5_rxq_stats {
46 #ifdef MLX5_PMD_SOFT_COUNTERS
47 uint64_t ipackets; /**< Total of successfully received packets. */
48 uint64_t ibytes; /**< Total of successfully received bytes. */
50 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
51 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
54 struct mlx5_txq_stats {
55 #ifdef MLX5_PMD_SOFT_COUNTERS
56 uint64_t opackets; /**< Total of successfully sent packets. */
57 uint64_t obytes; /**< Total of successfully sent bytes. */
59 uint64_t oerrors; /**< Total number of failed transmitted packets. */
64 /* Compressed CQE context. */
66 uint16_t ai; /* Array index. */
67 uint16_t ca; /* Current array index. */
68 uint16_t na; /* Next array index. */
69 uint16_t cq_ci; /* The next CQE. */
70 uint32_t cqe_cnt; /* Number of CQEs. */
73 /* Multi-Packet RQ buffer header. */
74 struct mlx5_mprq_buf {
75 struct rte_mempool *mp;
76 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
77 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
78 } __rte_cache_aligned;
80 /* Get pointer to the first stride. */
81 #define mlx5_mprq_buf_addr(ptr) ((ptr) + 1)
83 enum mlx5_rxq_err_state {
84 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
85 MLX5_RXQ_ERR_STATE_NEED_RESET,
86 MLX5_RXQ_ERR_STATE_NEED_READY,
89 /* RX queue descriptor. */
90 struct mlx5_rxq_data {
91 unsigned int csum:1; /* Enable checksum offloading. */
92 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
93 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
94 unsigned int crc_present:1; /* CRC must be subtracted. */
95 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
96 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
97 unsigned int elts_n:4; /* Log 2 of Mbufs. */
98 unsigned int rss_hash:1; /* RSS hash result is enabled. */
99 unsigned int mark:1; /* Marked flow available on the queue. */
100 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
101 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
102 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
103 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
104 unsigned int :4; /* Remaining bits. */
105 volatile uint32_t *rq_db;
106 volatile uint32_t *cq_db;
109 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
112 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
114 struct rxq_zip zip; /* Compressed context. */
115 uint16_t decompressed;
116 /* Number of ready mbufs decompressed from the CQ. */
118 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
119 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
121 volatile struct mlx5_cqe(*cqes)[];
124 struct rte_mbuf *(*elts)[];
125 struct mlx5_mprq_buf *(*mprq_bufs)[];
127 struct rte_mempool *mp;
128 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
129 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
130 uint16_t idx; /* Queue index. */
131 struct mlx5_rxq_stats stats;
132 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
133 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
134 void *cq_uar; /* CQ user access region. */
135 uint32_t cqn; /* CQ number. */
136 uint8_t cq_arm_sn; /* CQ arm seq number. */
138 rte_spinlock_t *uar_lock_cq;
139 /* CQ (UAR) access lock required for 32bit implementations */
141 uint32_t tunnel; /* Tunnel information. */
142 } __rte_cache_aligned;
144 enum mlx5_rxq_obj_type {
145 MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */
146 MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */
149 /* Verbs/DevX Rx queue elements. */
150 struct mlx5_rxq_obj {
151 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
152 rte_atomic32_t refcnt; /* Reference counter. */
153 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
154 struct ibv_cq *cq; /* Completion Queue. */
155 enum mlx5_rxq_obj_type type;
158 struct ibv_wq *wq; /* Work Queue. */
159 struct mlx5_devx_obj *rq; /* DevX object for Rx Queue. */
161 struct ibv_comp_channel *channel;
164 /* RX queue control descriptor. */
165 struct mlx5_rxq_ctrl {
166 struct mlx5_rxq_data rxq; /* Data path structure. */
167 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
168 rte_atomic32_t refcnt; /* Reference counter. */
169 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
170 struct mlx5_priv *priv; /* Back pointer to private data. */
171 unsigned int socket; /* CPU socket ID for allocations. */
172 unsigned int irq:1; /* Whether IRQ is enabled. */
173 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
174 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
175 uint32_t wqn; /* WQ number. */
176 uint16_t dump_file_n; /* Number of dump files. */
179 /* Indirection table. */
180 struct mlx5_ind_table_ibv {
181 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
182 rte_atomic32_t refcnt; /* Reference counter. */
183 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
184 uint32_t queues_n; /**< Number of queues in the list. */
185 uint16_t queues[]; /**< Queue list. */
190 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
191 rte_atomic32_t refcnt; /* Reference counter. */
192 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
193 struct ibv_qp *qp; /* Verbs queue pair. */
194 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
195 void *action; /* DV QP action pointer. */
197 uint64_t hash_fields; /* Verbs Hash fields. */
198 uint32_t rss_key_len; /* Hash key length in bytes. */
199 uint8_t rss_key[]; /* Hash key. */
202 /* TX queue send local data. */
204 struct mlx5_txq_local {
205 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
206 struct rte_mbuf *mbuf; /* first mbuf to process. */
207 uint16_t pkts_copy; /* packets copied to elts. */
208 uint16_t pkts_sent; /* packets sent. */
209 uint16_t elts_free; /* available elts remain. */
210 uint16_t wqe_free; /* available wqe remain. */
211 uint16_t mbuf_off; /* data offset in current mbuf. */
212 uint16_t mbuf_nseg; /* number of remaining mbuf. */
215 /* TX queue descriptor. */
217 struct mlx5_txq_data {
218 uint16_t elts_head; /* Current counter in (*elts)[]. */
219 uint16_t elts_tail; /* Counter of first element awaiting completion. */
220 uint16_t elts_comp; /* elts index since last completion request. */
221 uint16_t elts_s; /* Number of mbuf elements. */
222 uint16_t elts_m; /* Mask for mbuf elements indices. */
223 /* Fields related to elts mbuf storage. */
224 uint16_t wqe_ci; /* Consumer index for work queue. */
225 uint16_t wqe_pi; /* Producer index for work queue. */
226 uint16_t wqe_s; /* Number of WQ elements. */
227 uint16_t wqe_m; /* Mask Number for WQ elements. */
228 uint16_t wqe_comp; /* WQE index since last completion request. */
229 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
230 /* WQ related fields. */
231 uint16_t cq_ci; /* Consumer index for completion queue. */
233 uint16_t cq_pi; /* Counter of issued CQE "always" requests. */
235 uint16_t cqe_s; /* Number of CQ elements. */
236 uint16_t cqe_m; /* Mask for CQ indices. */
237 /* CQ related fields. */
238 uint16_t elts_n:4; /* elts[] length (in log2). */
239 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
240 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
241 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
242 uint16_t tunnel_en:1;
243 /* When set TX offload for tunneled packets are supported. */
244 uint16_t swp_en:1; /* Whether SW parser is enabled. */
245 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
246 uint16_t inlen_send; /* Ordinary send data inline size. */
247 uint16_t inlen_empw; /* eMPW max packet size to inline. */
248 uint16_t inlen_mode; /* Minimal data length to inline. */
249 uint32_t qp_num_8s; /* QP number shifted by 8. */
250 uint64_t offloads; /* Offloads for Tx Queue. */
251 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
252 struct mlx5_wqe *wqes; /* Work queue. */
253 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
254 volatile struct mlx5_cqe *cqes; /* Completion queue. */
255 volatile uint32_t *qp_db; /* Work queue doorbell. */
256 volatile uint32_t *cq_db; /* Completion queue doorbell. */
257 uint16_t port_id; /* Port ID of device. */
258 uint16_t idx; /* Queue index. */
259 struct mlx5_txq_stats stats; /* TX queue counters. */
261 rte_spinlock_t *uar_lock;
262 /* UAR access lock required for 32bit implementations */
264 struct rte_mbuf *elts[0];
265 /* Storage for queued packets, must be the last field. */
266 } __rte_cache_aligned;
268 /* Verbs Rx queue elements. */
269 struct mlx5_txq_ibv {
270 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
271 rte_atomic32_t refcnt; /* Reference counter. */
272 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
273 struct ibv_cq *cq; /* Completion Queue. */
274 struct ibv_qp *qp; /* Queue Pair. */
277 /* TX queue control descriptor. */
278 struct mlx5_txq_ctrl {
279 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
280 rte_atomic32_t refcnt; /* Reference counter. */
281 unsigned int socket; /* CPU socket ID for allocations. */
282 unsigned int max_inline_data; /* Max inline data. */
283 unsigned int max_tso_header; /* Max TSO header size. */
284 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
285 struct mlx5_priv *priv; /* Back pointer to private data. */
286 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
287 void *bf_reg; /* BlueFlame register from Verbs. */
288 uint16_t dump_file_n; /* Number of dump files. */
289 struct mlx5_txq_data txq; /* Data path structure. */
290 /* Must be the last field in the structure, contains elts[]. */
293 #define MLX5_TX_BFREG(txq) \
294 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
298 extern uint8_t rss_hash_default_key[];
300 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
301 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
302 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
303 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
304 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
305 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
306 unsigned int socket, const struct rte_eth_rxconf *conf,
307 struct rte_mempool *mp);
308 void mlx5_rx_queue_release(void *dpdk_rxq);
309 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
310 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
311 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
312 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
313 struct mlx5_rxq_obj *mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx);
314 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
315 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
316 uint16_t desc, unsigned int socket,
317 const struct rte_eth_rxconf *conf,
318 struct rte_mempool *mp);
319 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
320 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
321 int mlx5_rxq_verify(struct rte_eth_dev *dev);
322 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
323 int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev);
324 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
325 const uint8_t *rss_key, uint32_t rss_key_len,
326 uint64_t hash_fields,
327 const uint16_t *queues, uint32_t queues_n,
328 int tunnel __rte_unused);
329 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
330 const uint8_t *rss_key, uint32_t rss_key_len,
331 uint64_t hash_fields,
332 const uint16_t *queues, uint32_t queues_n);
333 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
334 int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev);
335 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
336 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
337 uint64_t mlx5_get_rx_port_offloads(struct rte_eth_dev *dev);
338 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
339 int mlx5_lro_on(struct rte_eth_dev *dev);
343 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
344 unsigned int socket, const struct rte_eth_txconf *conf);
345 void mlx5_tx_queue_release(void *dpdk_txq);
346 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
347 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
348 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
349 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
350 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
351 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
352 uint16_t desc, unsigned int socket,
353 const struct rte_eth_txconf *conf);
354 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
355 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
356 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
357 int mlx5_txq_verify(struct rte_eth_dev *dev);
358 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
359 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
363 extern uint32_t mlx5_ptype_table[];
364 extern uint8_t mlx5_cksum_table[];
365 extern uint8_t mlx5_swp_types_table[];
367 void mlx5_set_ptype_table(void);
368 void mlx5_set_cksum_table(void);
369 void mlx5_set_swp_types_table(void);
370 __rte_noinline uint16_t mlx5_tx_error_cqe_handle
371 (struct mlx5_txq_data *restrict txq,
372 volatile struct mlx5_err_cqe *err_cqe);
373 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
374 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
375 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq,
376 uint8_t mbuf_prepare);
377 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
378 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
379 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
381 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
383 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
385 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
386 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
387 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
388 void mlx5_dump_debug_information(const char *path, const char *title,
389 const void *buf, unsigned int len);
390 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
391 const struct mlx5_mp_arg_queue_state_modify *sm);
393 /* Vectorized version of mlx5_rxtx.c */
394 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
395 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
396 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
401 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
402 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
403 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
404 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
405 struct rte_mempool *mp);
406 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
408 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
412 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
413 * 64bit architectures.
416 * value to write in CPU endian format.
418 * Address to write to.
420 * Address of the lock to use for that UAR access.
422 static __rte_always_inline void
423 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
424 rte_spinlock_t *lock __rte_unused)
427 *(uint64_t *)addr = val;
428 #else /* !RTE_ARCH_64 */
429 rte_spinlock_lock(lock);
430 *(uint32_t *)addr = val;
432 *((uint32_t *)addr + 1) = val >> 32;
433 rte_spinlock_unlock(lock);
438 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
439 * 64bit architectures while guaranteeing the order of execution with the
440 * code being executed.
443 * value to write in CPU endian format.
445 * Address to write to.
447 * Address of the lock to use for that UAR access.
449 static __rte_always_inline void
450 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
453 __mlx5_uar_write64_relaxed(val, addr, lock);
456 /* Assist macros, used instead of directly calling the functions they wrap. */
458 #define mlx5_uar_write64_relaxed(val, dst, lock) \
459 __mlx5_uar_write64_relaxed(val, dst, NULL)
460 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
462 #define mlx5_uar_write64_relaxed(val, dst, lock) \
463 __mlx5_uar_write64_relaxed(val, dst, lock)
464 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
468 enum mlx5_cqe_status {
469 MLX5_CQE_STATUS_SW_OWN,
470 MLX5_CQE_STATUS_HW_OWN,
475 * Check whether CQE is valid.
480 * Size of completion queue.
487 static __rte_always_inline enum mlx5_cqe_status
488 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
491 const uint16_t idx = ci & cqes_n;
492 const uint8_t op_own = cqe->op_own;
493 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
494 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
496 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
497 return MLX5_CQE_STATUS_HW_OWN;
499 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
500 op_code == MLX5_CQE_REQ_ERR))
501 return MLX5_CQE_STATUS_ERR;
502 return MLX5_CQE_STATUS_SW_OWN;
506 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
507 * cloned mbuf is allocated is returned instead.
513 * Memory pool where data is located for given mbuf.
515 static inline struct rte_mempool *
516 mlx5_mb2mp(struct rte_mbuf *buf)
518 if (unlikely(RTE_MBUF_CLONED(buf)))
519 return rte_mbuf_from_indirect(buf)->pool;
524 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
525 * as mempool is pre-configured and static.
528 * Pointer to Rx queue structure.
533 * Searched LKey on success, UINT32_MAX on no match.
535 static __rte_always_inline uint32_t
536 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
538 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
541 /* Linear search on MR cache array. */
542 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
543 MLX5_MR_CACHE_N, addr);
544 if (likely(lkey != UINT32_MAX))
546 /* Take slower bottom-half (Binary Search) on miss. */
547 return mlx5_rx_addr2mr_bh(rxq, addr);
550 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
553 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
556 * Pointer to Tx queue structure.
561 * Searched LKey on success, UINT32_MAX on no match.
563 static __rte_always_inline uint32_t
564 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
566 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
567 uintptr_t addr = (uintptr_t)mb->buf_addr;
570 /* Check generation bit to see if there's any change on existing MRs. */
571 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
572 mlx5_mr_flush_local_cache(mr_ctrl);
573 /* Linear search on MR cache array. */
574 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
575 MLX5_MR_CACHE_N, addr);
576 if (likely(lkey != UINT32_MAX))
578 /* Take slower bottom-half on miss. */
579 return mlx5_tx_mb2mr_bh(txq, mb);
583 * Ring TX queue doorbell and flush the update if requested.
586 * Pointer to TX queue structure.
588 * Pointer to the last WQE posted in the NIC.
590 * Request for write memory barrier after BlueFlame update.
592 static __rte_always_inline void
593 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
596 uint64_t *dst = MLX5_TX_BFREG(txq);
597 volatile uint64_t *src = ((volatile uint64_t *)wqe);
600 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
601 /* Ensure ordering between DB record and BF copy. */
603 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
609 * Ring TX queue doorbell and flush the update by write memory barrier.
612 * Pointer to TX queue structure.
614 * Pointer to the last WQE posted in the NIC.
616 static __rte_always_inline void
617 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
619 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
622 #endif /* RTE_PMD_MLX5_RXTX_H_ */