1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 #include <rte_mempool.h>
15 #include <rte_common.h>
16 #include <rte_hexdump.h>
17 #include <rte_spinlock.h>
19 #include <rte_bus_pci.h>
20 #include <rte_malloc.h>
21 #include <rte_cycles.h>
23 #include <mlx5_glue.h>
25 #include <mlx5_common.h>
26 #include <mlx5_common_mr.h>
28 #include "mlx5_defs.h"
29 #include "mlx5_utils.h"
31 #include "mlx5_autoconf.h"
35 /* Mbuf dynamic flag offset for inline. */
36 extern uint64_t rte_net_mlx5_dynf_inline_mask;
38 struct mlx5_txq_stats {
39 #ifdef MLX5_PMD_SOFT_COUNTERS
40 uint64_t opackets; /**< Total of successfully sent packets. */
41 uint64_t obytes; /**< Total of successfully sent bytes. */
43 uint64_t oerrors; /**< Total number of failed transmitted packets. */
48 /* TX queue send local data. */
50 struct mlx5_txq_local {
51 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
52 struct rte_mbuf *mbuf; /* first mbuf to process. */
53 uint16_t pkts_copy; /* packets copied to elts. */
54 uint16_t pkts_sent; /* packets sent. */
55 uint16_t pkts_loop; /* packets sent on loop entry. */
56 uint16_t elts_free; /* available elts remain. */
57 uint16_t wqe_free; /* available wqe remain. */
58 uint16_t mbuf_off; /* data offset in current mbuf. */
59 uint16_t mbuf_nseg; /* number of remaining mbuf. */
60 uint16_t mbuf_free; /* number of inline mbufs to free. */
63 /* TX queue descriptor. */
65 struct mlx5_txq_data {
66 uint16_t elts_head; /* Current counter in (*elts)[]. */
67 uint16_t elts_tail; /* Counter of first element awaiting completion. */
68 uint16_t elts_comp; /* elts index since last completion request. */
69 uint16_t elts_s; /* Number of mbuf elements. */
70 uint16_t elts_m; /* Mask for mbuf elements indices. */
71 /* Fields related to elts mbuf storage. */
72 uint16_t wqe_ci; /* Consumer index for work queue. */
73 uint16_t wqe_pi; /* Producer index for work queue. */
74 uint16_t wqe_s; /* Number of WQ elements. */
75 uint16_t wqe_m; /* Mask Number for WQ elements. */
76 uint16_t wqe_comp; /* WQE index since last completion request. */
77 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
78 /* WQ related fields. */
79 uint16_t cq_ci; /* Consumer index for completion queue. */
80 uint16_t cq_pi; /* Production index for completion queue. */
81 uint16_t cqe_s; /* Number of CQ elements. */
82 uint16_t cqe_m; /* Mask for CQ indices. */
83 /* CQ related fields. */
84 uint16_t elts_n:4; /* elts[] length (in log2). */
85 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
86 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
87 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
89 /* When set TX offload for tunneled packets are supported. */
90 uint16_t swp_en:1; /* Whether SW parser is enabled. */
91 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
92 uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */
93 uint16_t db_heu:1; /* Doorbell heuristic write barrier. */
94 uint16_t fast_free:1; /* mbuf fast free on Tx is enabled. */
95 uint16_t inlen_send; /* Ordinary send data inline size. */
96 uint16_t inlen_empw; /* eMPW max packet size to inline. */
97 uint16_t inlen_mode; /* Minimal data length to inline. */
98 uint32_t qp_num_8s; /* QP number shifted by 8. */
99 uint64_t offloads; /* Offloads for Tx Queue. */
100 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
101 struct mlx5_wqe *wqes; /* Work queue. */
102 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
103 #ifdef RTE_LIBRTE_MLX5_DEBUG
104 uint32_t *fcqs; /* Free completion queue (debug extended). */
106 uint16_t *fcqs; /* Free completion queue. */
108 volatile struct mlx5_cqe *cqes; /* Completion queue. */
109 volatile uint32_t *qp_db; /* Work queue doorbell. */
110 volatile uint32_t *cq_db; /* Completion queue doorbell. */
111 uint16_t port_id; /* Port ID of device. */
112 uint16_t idx; /* Queue index. */
113 uint64_t ts_mask; /* Timestamp flag dynamic mask. */
114 int32_t ts_offset; /* Timestamp field dynamic offset. */
115 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
116 struct mlx5_txq_stats stats; /* TX queue counters. */
118 rte_spinlock_t *uar_lock;
119 /* UAR access lock required for 32bit implementations */
121 struct rte_mbuf *elts[0];
122 /* Storage for queued packets, must be the last field. */
123 } __rte_cache_aligned;
126 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
127 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
130 /* TX queue control descriptor. */
131 struct mlx5_txq_ctrl {
132 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
133 uint32_t refcnt; /* Reference counter. */
134 unsigned int socket; /* CPU socket ID for allocations. */
135 enum mlx5_txq_type type; /* The txq ctrl type. */
136 unsigned int max_inline_data; /* Max inline data. */
137 unsigned int max_tso_header; /* Max TSO header size. */
138 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */
139 struct mlx5_priv *priv; /* Back pointer to private data. */
140 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
141 void *bf_reg; /* BlueFlame register from Verbs. */
142 uint16_t dump_file_n; /* Number of dump files. */
143 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
144 uint32_t hairpin_status; /* Hairpin binding status. */
145 struct mlx5_txq_data txq; /* Data path structure. */
146 /* Must be the last field in the structure, contains elts[]. */
149 #define MLX5_TX_BFREG(txq) \
150 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
154 int mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id);
155 int mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id);
156 int mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id);
157 int mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id);
158 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
159 unsigned int socket, const struct rte_eth_txconf *conf);
160 int mlx5_tx_hairpin_queue_setup
161 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
162 const struct rte_eth_hairpin_conf *hairpin_conf);
163 void mlx5_tx_queue_release(void *dpdk_txq);
164 void txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl);
165 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
166 void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev);
167 int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
168 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
169 uint16_t desc, unsigned int socket,
170 const struct rte_eth_txconf *conf);
171 struct mlx5_txq_ctrl *mlx5_txq_hairpin_new
172 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
173 const struct rte_eth_hairpin_conf *hairpin_conf);
174 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
175 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
176 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
177 int mlx5_txq_verify(struct rte_eth_dev *dev);
178 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
179 void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);
180 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
181 void mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev);
185 extern uint32_t mlx5_ptype_table[];
186 extern uint8_t mlx5_cksum_table[];
187 extern uint8_t mlx5_swp_types_table[];
189 void mlx5_set_ptype_table(void);
190 void mlx5_set_cksum_table(void);
191 void mlx5_set_swp_types_table(void);
192 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
194 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
195 void mlx5_dump_debug_information(const char *path, const char *title,
196 const void *buf, unsigned int len);
197 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
198 const struct mlx5_mp_arg_queue_state_modify *sm);
199 int mlx5_queue_state_modify(struct rte_eth_dev *dev,
200 struct mlx5_mp_arg_queue_state_modify *sm);
201 void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
202 struct rte_eth_txq_info *qinfo);
203 int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
204 struct rte_eth_burst_mode *mode);
208 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
209 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
210 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
211 struct rte_mempool *mp);
212 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
214 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
218 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
219 * 64bit architectures.
222 * value to write in CPU endian format.
224 * Address to write to.
226 * Address of the lock to use for that UAR access.
228 static __rte_always_inline void
229 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
230 rte_spinlock_t *lock __rte_unused)
233 *(uint64_t *)addr = val;
234 #else /* !RTE_ARCH_64 */
235 rte_spinlock_lock(lock);
236 *(uint32_t *)addr = val;
238 *((uint32_t *)addr + 1) = val >> 32;
239 rte_spinlock_unlock(lock);
244 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
245 * 64bit architectures while guaranteeing the order of execution with the
246 * code being executed.
249 * value to write in CPU endian format.
251 * Address to write to.
253 * Address of the lock to use for that UAR access.
255 static __rte_always_inline void
256 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
259 __mlx5_uar_write64_relaxed(val, addr, lock);
262 /* Assist macros, used instead of directly calling the functions they wrap. */
264 #define mlx5_uar_write64_relaxed(val, dst, lock) \
265 __mlx5_uar_write64_relaxed(val, dst, NULL)
266 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
268 #define mlx5_uar_write64_relaxed(val, dst, lock) \
269 __mlx5_uar_write64_relaxed(val, dst, lock)
270 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
274 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
275 * cloned mbuf is allocated is returned instead.
281 * Memory pool where data is located for given mbuf.
283 static inline struct rte_mempool *
284 mlx5_mb2mp(struct rte_mbuf *buf)
286 if (unlikely(RTE_MBUF_CLONED(buf)))
287 return rte_mbuf_from_indirect(buf)->pool;
292 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
295 * Pointer to Tx queue structure.
300 * Searched LKey on success, UINT32_MAX on no match.
302 static __rte_always_inline uint32_t
303 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
305 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
306 uintptr_t addr = (uintptr_t)mb->buf_addr;
309 /* Check generation bit to see if there's any change on existing MRs. */
310 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
311 mlx5_mr_flush_local_cache(mr_ctrl);
312 /* Linear search on MR cache array. */
313 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
314 MLX5_MR_CACHE_N, addr);
315 if (likely(lkey != UINT32_MAX))
317 /* Take slower bottom-half on miss. */
318 return mlx5_tx_mb2mr_bh(txq, mb);
322 * Ring TX queue doorbell and flush the update if requested.
325 * Pointer to TX queue structure.
327 * Pointer to the last WQE posted in the NIC.
329 * Request for write memory barrier after BlueFlame update.
331 static __rte_always_inline void
332 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
335 uint64_t *dst = MLX5_TX_BFREG(txq);
336 volatile uint64_t *src = ((volatile uint64_t *)wqe);
339 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
340 /* Ensure ordering between DB record and BF copy. */
342 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
348 * Ring TX queue doorbell and flush the update by write memory barrier.
351 * Pointer to TX queue structure.
353 * Pointer to the last WQE posted in the NIC.
355 static __rte_always_inline void
356 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
358 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
362 * Convert timestamp from mbuf format to linear counter
363 * of Clock Queue completions (24 bits)
366 * Pointer to the device shared context to fetch Tx
367 * packet pacing timestamp and parameters.
369 * Timestamp from mbuf to convert.
371 * positive or zero value - completion ID to wait
372 * negative value - conversion error
374 static __rte_always_inline int32_t
375 mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts)
382 * Read atomically two uint64_t fields and compare lsb bits.
383 * It there is no match - the timestamp was updated in
384 * the service thread, data should be re-read.
386 rte_compiler_barrier();
387 ci = __atomic_load_n(&sh->txpp.ts.ci_ts, __ATOMIC_RELAXED);
388 ts = __atomic_load_n(&sh->txpp.ts.ts, __ATOMIC_RELAXED);
389 rte_compiler_barrier();
390 if (!((ts ^ ci) << (64 - MLX5_CQ_INDEX_WIDTH)))
393 /* Perform the skew correction, positive value to send earlier. */
394 mts -= sh->txpp.skew;
396 if (unlikely(mts >= UINT64_MAX / 2)) {
397 /* We have negative integer, mts is in the past. */
398 __atomic_fetch_add(&sh->txpp.err_ts_past,
399 1, __ATOMIC_RELAXED);
402 tick = sh->txpp.tick;
404 /* Convert delta to completions, round up. */
405 mts = (mts + tick - 1) / tick;
406 if (unlikely(mts >= (1 << MLX5_CQ_INDEX_WIDTH) / 2 - 1)) {
407 /* We have mts is too distant future. */
408 __atomic_fetch_add(&sh->txpp.err_ts_future,
409 1, __ATOMIC_RELAXED);
412 mts <<= 64 - MLX5_CQ_INDEX_WIDTH;
414 ci >>= 64 - MLX5_CQ_INDEX_WIDTH;
418 #endif /* RTE_PMD_MLX5_RXTX_H_ */