4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef RTE_PMD_MLX5_RXTX_H_
35 #define RTE_PMD_MLX5_RXTX_H_
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-pedantic"
44 #include <infiniband/verbs.h>
46 #pragma GCC diagnostic error "-pedantic"
49 /* DPDK headers don't like -pedantic. */
51 #pragma GCC diagnostic ignored "-pedantic"
54 #include <rte_mempool.h>
56 #pragma GCC diagnostic error "-pedantic"
59 #include "mlx5_utils.h"
61 #include "mlx5_defs.h"
63 struct mlx5_rxq_stats {
64 unsigned int idx; /**< Mapping index. */
65 #ifdef MLX5_PMD_SOFT_COUNTERS
66 uint64_t ipackets; /**< Total of successfully received packets. */
67 uint64_t ibytes; /**< Total of successfully received bytes. */
69 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
70 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
73 struct mlx5_txq_stats {
74 unsigned int idx; /**< Mapping index. */
75 #ifdef MLX5_PMD_SOFT_COUNTERS
76 uint64_t opackets; /**< Total of successfully sent packets. */
77 uint64_t obytes; /**< Total of successfully sent bytes. */
79 uint64_t odropped; /**< Total of packets not sent when TX ring full. */
82 /* RX element (scattered packets). */
84 struct ibv_sge sges[MLX5_PMD_SGE_WR_N]; /* Scatter/Gather Elements. */
85 struct rte_mbuf *bufs[MLX5_PMD_SGE_WR_N]; /* SGEs buffers. */
90 struct ibv_sge sge; /* Scatter/Gather Element. */
91 struct rte_mbuf *buf; /* SGE buffer. */
96 /* RX queue descriptor. */
98 struct priv *priv; /* Back pointer to private data. */
99 struct rte_mempool *mp; /* Memory Pool for allocations. */
100 struct ibv_mr *mr; /* Memory Region (for mp). */
101 struct ibv_cq *cq; /* Completion Queue. */
102 struct ibv_exp_wq *wq; /* Work Queue. */
103 struct ibv_exp_wq_family *if_wq; /* WQ burst interface. */
104 struct ibv_exp_cq_family *if_cq; /* CQ interface. */
105 unsigned int port_id; /* Port ID for incoming packets. */
106 unsigned int elts_n; /* (*elts)[] length. */
107 unsigned int elts_head; /* Current index in (*elts)[]. */
109 struct rxq_elt_sp (*sp)[]; /* Scattered RX elements. */
110 struct rxq_elt (*no_sp)[]; /* RX elements. */
112 unsigned int sp:1; /* Use scattered RX elements. */
113 unsigned int csum:1; /* Enable checksum offloading. */
114 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
115 uint32_t mb_len; /* Length of a mp-issued mbuf. */
116 struct mlx5_rxq_stats stats; /* RX queue counters. */
117 unsigned int socket; /* CPU socket ID for allocations. */
118 struct ibv_exp_res_domain *rd; /* Resource Domain. */
121 /* Hash RX queue types. */
129 /* Initialization data for hash RX queue. */
130 struct hash_rxq_init {
131 uint64_t hash_fields; /* Fields that participate in the hash. */
134 /* Initialization data for indirection table. */
135 struct ind_table_init {
136 unsigned int max_size; /* Maximum number of WQs. */
137 /* Hash RX queues using this table. */
138 unsigned int hash_types;
139 unsigned int hash_types_n;
143 struct priv *priv; /* Back pointer to private data. */
144 struct ibv_qp *qp; /* Hash RX QP. */
145 enum hash_rxq_type type; /* Hash RX queue type. */
146 /* MAC flow steering rules, one per VLAN ID. */
147 struct ibv_flow *mac_flow[MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS];
148 struct ibv_flow *promisc_flow; /* Promiscuous flow. */
149 struct ibv_flow *allmulti_flow; /* Multicast flow. */
154 struct rte_mbuf *buf;
157 /* Linear buffer type. It is used when transmitting buffers with too many
158 * segments that do not fit the hardware queue (see max_send_sge).
159 * Extra segments are copied (linearized) in such buffers, replacing the
160 * last SGE during TX.
161 * The size is arbitrary but large enough to hold a jumbo frame with
162 * 8 segments considering mbuf.buf_len is about 2048 bytes. */
163 typedef uint8_t linear_t[16384];
165 /* TX queue descriptor. */
167 struct priv *priv; /* Back pointer to private data. */
169 struct rte_mempool *mp; /* Cached Memory Pool. */
170 struct ibv_mr *mr; /* Memory Region (for mp). */
171 uint32_t lkey; /* mr->lkey */
172 } mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
173 struct ibv_cq *cq; /* Completion Queue. */
174 struct ibv_qp *qp; /* Queue Pair. */
175 struct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */
176 struct ibv_exp_cq_family *if_cq; /* CQ interface. */
177 #if MLX5_PMD_MAX_INLINE > 0
178 uint32_t max_inline; /* Max inline send size <= MLX5_PMD_MAX_INLINE. */
180 unsigned int elts_n; /* (*elts)[] length. */
181 struct txq_elt (*elts)[]; /* TX elements. */
182 unsigned int elts_head; /* Current index in (*elts)[]. */
183 unsigned int elts_tail; /* First element awaiting completion. */
184 unsigned int elts_comp; /* Number of completion requests. */
185 unsigned int elts_comp_cd; /* Countdown for next completion request. */
186 unsigned int elts_comp_cd_init; /* Initial value for countdown. */
187 struct mlx5_txq_stats stats; /* TX queue counters. */
188 linear_t (*elts_linear)[]; /* Linearized buffers. */
189 struct ibv_mr *mr_linear; /* Memory Region for linearized buffers. */
190 unsigned int socket; /* CPU socket ID for allocations. */
191 struct ibv_exp_res_domain *rd; /* Resource Domain. */
196 int priv_create_hash_rxqs(struct priv *);
197 void priv_destroy_hash_rxqs(struct priv *);
198 void rxq_cleanup(struct rxq *);
199 int rxq_rehash(struct rte_eth_dev *, struct rxq *);
200 int rxq_setup(struct rte_eth_dev *, struct rxq *, uint16_t, unsigned int,
201 const struct rte_eth_rxconf *, struct rte_mempool *);
202 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
203 const struct rte_eth_rxconf *, struct rte_mempool *);
204 void mlx5_rx_queue_release(void *);
208 void txq_cleanup(struct txq *);
209 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
210 const struct rte_eth_txconf *);
211 void mlx5_tx_queue_release(void *);
215 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
216 uint16_t mlx5_rx_burst_sp(void *, struct rte_mbuf **, uint16_t);
217 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
218 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
219 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
221 #endif /* RTE_PMD_MLX5_RXTX_H_ */