1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
29 #include <rte_spinlock.h>
31 #include <rte_bus_pci.h>
32 #include <rte_malloc.h>
34 #include <mlx5_glue.h>
37 #include "mlx5_defs.h"
38 #include "mlx5_utils.h"
41 #include "mlx5_autoconf.h"
43 /* Support tunnel matching. */
44 #define MLX5_FLOW_TUNNEL 10
46 struct mlx5_rxq_stats {
47 #ifdef MLX5_PMD_SOFT_COUNTERS
48 uint64_t ipackets; /**< Total of successfully received packets. */
49 uint64_t ibytes; /**< Total of successfully received bytes. */
51 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
52 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
55 struct mlx5_txq_stats {
56 #ifdef MLX5_PMD_SOFT_COUNTERS
57 uint64_t opackets; /**< Total of successfully sent packets. */
58 uint64_t obytes; /**< Total of successfully sent bytes. */
60 uint64_t oerrors; /**< Total number of failed transmitted packets. */
65 /* Compressed CQE context. */
67 uint16_t ai; /* Array index. */
68 uint16_t ca; /* Current array index. */
69 uint16_t na; /* Next array index. */
70 uint16_t cq_ci; /* The next CQE. */
71 uint32_t cqe_cnt; /* Number of CQEs. */
74 /* Multi-Packet RQ buffer header. */
75 struct mlx5_mprq_buf {
76 struct rte_mempool *mp;
77 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
78 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
79 struct rte_mbuf_ext_shared_info shinfos[];
81 * Shared information per stride.
82 * More memory will be allocated for the first stride head-room and for
85 } __rte_cache_aligned;
87 /* Get pointer to the first stride. */
88 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
89 sizeof(struct mlx5_mprq_buf) + \
91 sizeof(struct rte_mbuf_ext_shared_info) + \
92 RTE_PKTMBUF_HEADROOM))
94 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
95 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
97 enum mlx5_rxq_err_state {
98 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
99 MLX5_RXQ_ERR_STATE_NEED_RESET,
100 MLX5_RXQ_ERR_STATE_NEED_READY,
103 /* RX queue descriptor. */
104 struct mlx5_rxq_data {
105 unsigned int csum:1; /* Enable checksum offloading. */
106 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
107 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
108 unsigned int crc_present:1; /* CRC must be subtracted. */
109 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */
110 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
111 unsigned int elts_n:4; /* Log 2 of Mbufs. */
112 unsigned int rss_hash:1; /* RSS hash result is enabled. */
113 unsigned int mark:1; /* Marked flow available on the queue. */
114 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
115 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
116 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
117 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
118 unsigned int strd_headroom_en:1; /* Enable mbuf headroom in MPRQ. */
119 unsigned int lro:1; /* Enable LRO. */
120 unsigned int :1; /* Remaining bits. */
121 volatile uint32_t *rq_db;
122 volatile uint32_t *cq_db;
125 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
128 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
130 struct rxq_zip zip; /* Compressed context. */
131 uint16_t decompressed;
132 /* Number of ready mbufs decompressed from the CQ. */
134 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
135 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
137 volatile struct mlx5_cqe(*cqes)[];
140 struct rte_mbuf *(*elts)[];
141 struct mlx5_mprq_buf *(*mprq_bufs)[];
143 struct rte_mempool *mp;
144 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
145 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
146 uint16_t idx; /* Queue index. */
147 struct mlx5_rxq_stats stats;
148 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */
149 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
150 void *cq_uar; /* CQ user access region. */
151 uint32_t cqn; /* CQ number. */
152 uint8_t cq_arm_sn; /* CQ arm seq number. */
154 rte_spinlock_t *uar_lock_cq;
155 /* CQ (UAR) access lock required for 32bit implementations */
157 uint32_t tunnel; /* Tunnel information. */
158 } __rte_cache_aligned;
160 enum mlx5_rxq_obj_type {
161 MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */
162 MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */
163 MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN,
164 /* mlx5_rxq_obj with mlx5_devx_rq and hairpin support. */
168 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */
169 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
170 MLX5_RXQ_TYPE_UNDEFINED,
173 /* Verbs/DevX Rx queue elements. */
174 struct mlx5_rxq_obj {
175 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
176 rte_atomic32_t refcnt; /* Reference counter. */
177 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
178 struct ibv_cq *cq; /* Completion Queue. */
179 enum mlx5_rxq_obj_type type;
182 struct ibv_wq *wq; /* Work Queue. */
183 struct mlx5_devx_obj *rq; /* DevX object for Rx Queue. */
185 struct ibv_comp_channel *channel;
188 /* RX queue control descriptor. */
189 struct mlx5_rxq_ctrl {
190 struct mlx5_rxq_data rxq; /* Data path structure. */
191 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
192 rte_atomic32_t refcnt; /* Reference counter. */
193 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
194 struct mlx5_priv *priv; /* Back pointer to private data. */
195 enum mlx5_rxq_type type; /* Rxq type. */
196 unsigned int socket; /* CPU socket ID for allocations. */
197 unsigned int irq:1; /* Whether IRQ is enabled. */
198 unsigned int dbr_umem_id_valid:1; /* dbr_umem_id holds a valid value. */
199 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
200 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
201 uint32_t wqn; /* WQ number. */
202 uint16_t dump_file_n; /* Number of dump files. */
203 uint32_t dbr_umem_id; /* Storing door-bell information, */
204 uint64_t dbr_offset; /* needed when freeing door-bell. */
205 struct mlx5dv_devx_umem *wq_umem; /* WQ buffer registration info. */
206 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
209 enum mlx5_ind_tbl_type {
210 MLX5_IND_TBL_TYPE_IBV,
211 MLX5_IND_TBL_TYPE_DEVX,
214 /* Indirection table. */
215 struct mlx5_ind_table_obj {
216 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
217 rte_atomic32_t refcnt; /* Reference counter. */
218 enum mlx5_ind_tbl_type type;
221 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
222 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
224 uint32_t queues_n; /**< Number of queues in the list. */
225 uint16_t queues[]; /**< Queue list. */
230 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
231 rte_atomic32_t refcnt; /* Reference counter. */
232 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
235 struct ibv_qp *qp; /* Verbs queue pair. */
236 struct mlx5_devx_obj *tir; /* DevX TIR object. */
238 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
239 void *action; /* DV QP action pointer. */
241 uint64_t hash_fields; /* Verbs Hash fields. */
242 uint32_t rss_key_len; /* Hash key length in bytes. */
243 uint8_t rss_key[]; /* Hash key. */
246 /* TX queue send local data. */
248 struct mlx5_txq_local {
249 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
250 struct rte_mbuf *mbuf; /* first mbuf to process. */
251 uint16_t pkts_copy; /* packets copied to elts. */
252 uint16_t pkts_sent; /* packets sent. */
253 uint16_t pkts_loop; /* packets sent on loop entry. */
254 uint16_t elts_free; /* available elts remain. */
255 uint16_t wqe_free; /* available wqe remain. */
256 uint16_t mbuf_off; /* data offset in current mbuf. */
257 uint16_t mbuf_nseg; /* number of remaining mbuf. */
260 /* TX queue descriptor. */
262 struct mlx5_txq_data {
263 uint16_t elts_head; /* Current counter in (*elts)[]. */
264 uint16_t elts_tail; /* Counter of first element awaiting completion. */
265 uint16_t elts_comp; /* elts index since last completion request. */
266 uint16_t elts_s; /* Number of mbuf elements. */
267 uint16_t elts_m; /* Mask for mbuf elements indices. */
268 /* Fields related to elts mbuf storage. */
269 uint16_t wqe_ci; /* Consumer index for work queue. */
270 uint16_t wqe_pi; /* Producer index for work queue. */
271 uint16_t wqe_s; /* Number of WQ elements. */
272 uint16_t wqe_m; /* Mask Number for WQ elements. */
273 uint16_t wqe_comp; /* WQE index since last completion request. */
274 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
275 /* WQ related fields. */
276 uint16_t cq_ci; /* Consumer index for completion queue. */
277 uint16_t cq_pi; /* Production index for completion queue. */
278 uint16_t cqe_s; /* Number of CQ elements. */
279 uint16_t cqe_m; /* Mask for CQ indices. */
280 /* CQ related fields. */
281 uint16_t elts_n:4; /* elts[] length (in log2). */
282 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
283 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
284 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
285 uint16_t tunnel_en:1;
286 /* When set TX offload for tunneled packets are supported. */
287 uint16_t swp_en:1; /* Whether SW parser is enabled. */
288 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
289 uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */
290 uint16_t db_heu:1; /* Doorbell heuristic write barrier. */
291 uint16_t inlen_send; /* Ordinary send data inline size. */
292 uint16_t inlen_empw; /* eMPW max packet size to inline. */
293 uint16_t inlen_mode; /* Minimal data length to inline. */
294 uint32_t qp_num_8s; /* QP number shifted by 8. */
295 uint64_t offloads; /* Offloads for Tx Queue. */
296 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
297 struct mlx5_wqe *wqes; /* Work queue. */
298 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
300 uint16_t *fcqs; /* Free completion queue. */
302 uint32_t *fcqs; /* Free completion queue (debug extended). */
304 volatile struct mlx5_cqe *cqes; /* Completion queue. */
305 volatile uint32_t *qp_db; /* Work queue doorbell. */
306 volatile uint32_t *cq_db; /* Completion queue doorbell. */
307 uint16_t port_id; /* Port ID of device. */
308 uint16_t idx; /* Queue index. */
309 struct mlx5_txq_stats stats; /* TX queue counters. */
311 rte_spinlock_t *uar_lock;
312 /* UAR access lock required for 32bit implementations */
314 struct rte_mbuf *elts[0];
315 /* Storage for queued packets, must be the last field. */
316 } __rte_cache_aligned;
318 enum mlx5_txq_obj_type {
319 MLX5_TXQ_OBJ_TYPE_IBV, /* mlx5_txq_obj with ibv_wq. */
320 MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN,
321 /* mlx5_txq_obj with mlx5_devx_tq and hairpin support. */
325 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
326 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
329 /* Verbs/DevX Tx queue elements. */
330 struct mlx5_txq_obj {
331 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
332 rte_atomic32_t refcnt; /* Reference counter. */
333 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
334 enum mlx5_txq_obj_type type; /* The txq object type. */
338 struct ibv_cq *cq; /* Completion Queue. */
339 struct ibv_qp *qp; /* Queue Pair. */
342 struct mlx5_devx_obj *sq;
343 /* DevX object for Sx queue. */
344 struct mlx5_devx_obj *tis; /* The TIS object. */
349 /* TX queue control descriptor. */
350 struct mlx5_txq_ctrl {
351 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
352 rte_atomic32_t refcnt; /* Reference counter. */
353 unsigned int socket; /* CPU socket ID for allocations. */
354 enum mlx5_txq_type type; /* The txq ctrl type. */
355 unsigned int max_inline_data; /* Max inline data. */
356 unsigned int max_tso_header; /* Max TSO header size. */
357 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */
358 struct mlx5_priv *priv; /* Back pointer to private data. */
359 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
360 void *bf_reg; /* BlueFlame register from Verbs. */
361 uint16_t dump_file_n; /* Number of dump files. */
362 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
363 struct mlx5_txq_data txq; /* Data path structure. */
364 /* Must be the last field in the structure, contains elts[]. */
367 #define MLX5_TX_BFREG(txq) \
368 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
372 extern uint8_t rss_hash_default_key[];
374 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
375 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
376 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
377 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
378 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
379 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
380 unsigned int socket, const struct rte_eth_rxconf *conf,
381 struct rte_mempool *mp);
382 int mlx5_rx_hairpin_queue_setup
383 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
384 const struct rte_eth_hairpin_conf *hairpin_conf);
385 void mlx5_rx_queue_release(void *dpdk_rxq);
386 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
387 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
388 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
389 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
390 struct mlx5_rxq_obj *mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
391 enum mlx5_rxq_obj_type type);
392 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
393 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
394 uint16_t desc, unsigned int socket,
395 const struct rte_eth_rxconf *conf,
396 struct rte_mempool *mp);
397 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new
398 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
399 const struct rte_eth_hairpin_conf *hairpin_conf);
400 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
401 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
402 int mlx5_rxq_verify(struct rte_eth_dev *dev);
403 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
404 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
405 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
406 const uint8_t *rss_key, uint32_t rss_key_len,
407 uint64_t hash_fields,
408 const uint16_t *queues, uint32_t queues_n,
409 int tunnel __rte_unused);
410 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
411 const uint8_t *rss_key, uint32_t rss_key_len,
412 uint64_t hash_fields,
413 const uint16_t *queues, uint32_t queues_n);
414 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
415 int mlx5_hrxq_verify(struct rte_eth_dev *dev);
416 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx);
417 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
418 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
419 uint64_t mlx5_get_rx_port_offloads(void);
420 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
424 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
425 unsigned int socket, const struct rte_eth_txconf *conf);
426 int mlx5_tx_hairpin_queue_setup
427 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
428 const struct rte_eth_hairpin_conf *hairpin_conf);
429 void mlx5_tx_queue_release(void *dpdk_txq);
430 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
431 struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
432 enum mlx5_txq_obj_type type);
433 struct mlx5_txq_obj *mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx);
434 int mlx5_txq_obj_release(struct mlx5_txq_obj *txq_ibv);
435 int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
436 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
437 uint16_t desc, unsigned int socket,
438 const struct rte_eth_txconf *conf);
439 struct mlx5_txq_ctrl *mlx5_txq_hairpin_new
440 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
441 const struct rte_eth_hairpin_conf *hairpin_conf);
442 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
443 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
444 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
445 int mlx5_txq_verify(struct rte_eth_dev *dev);
446 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
447 void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);
448 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
452 extern uint32_t mlx5_ptype_table[];
453 extern uint8_t mlx5_cksum_table[];
454 extern uint8_t mlx5_swp_types_table[];
456 void mlx5_set_ptype_table(void);
457 void mlx5_set_cksum_table(void);
458 void mlx5_set_swp_types_table(void);
459 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
460 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
461 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);
462 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
463 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
464 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
466 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
468 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
470 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
471 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
472 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
473 void mlx5_dump_debug_information(const char *path, const char *title,
474 const void *buf, unsigned int len);
475 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
476 const struct mlx5_mp_arg_queue_state_modify *sm);
478 /* Vectorized version of mlx5_rxtx.c */
479 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
480 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
481 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
486 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
487 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
488 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
489 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
490 struct rte_mempool *mp);
491 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
493 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
497 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
498 * 64bit architectures.
501 * value to write in CPU endian format.
503 * Address to write to.
505 * Address of the lock to use for that UAR access.
507 static __rte_always_inline void
508 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
509 rte_spinlock_t *lock __rte_unused)
512 *(uint64_t *)addr = val;
513 #else /* !RTE_ARCH_64 */
514 rte_spinlock_lock(lock);
515 *(uint32_t *)addr = val;
517 *((uint32_t *)addr + 1) = val >> 32;
518 rte_spinlock_unlock(lock);
523 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
524 * 64bit architectures while guaranteeing the order of execution with the
525 * code being executed.
528 * value to write in CPU endian format.
530 * Address to write to.
532 * Address of the lock to use for that UAR access.
534 static __rte_always_inline void
535 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
538 __mlx5_uar_write64_relaxed(val, addr, lock);
541 /* Assist macros, used instead of directly calling the functions they wrap. */
543 #define mlx5_uar_write64_relaxed(val, dst, lock) \
544 __mlx5_uar_write64_relaxed(val, dst, NULL)
545 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
547 #define mlx5_uar_write64_relaxed(val, dst, lock) \
548 __mlx5_uar_write64_relaxed(val, dst, lock)
549 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
553 enum mlx5_cqe_status {
554 MLX5_CQE_STATUS_SW_OWN = -1,
555 MLX5_CQE_STATUS_HW_OWN = -2,
556 MLX5_CQE_STATUS_ERR = -3,
560 * Check whether CQE is valid.
565 * Size of completion queue.
572 static __rte_always_inline enum mlx5_cqe_status
573 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
576 const uint16_t idx = ci & cqes_n;
577 const uint8_t op_own = cqe->op_own;
578 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
579 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
581 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
582 return MLX5_CQE_STATUS_HW_OWN;
584 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
585 op_code == MLX5_CQE_REQ_ERR))
586 return MLX5_CQE_STATUS_ERR;
587 return MLX5_CQE_STATUS_SW_OWN;
591 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
592 * cloned mbuf is allocated is returned instead.
598 * Memory pool where data is located for given mbuf.
600 static inline struct rte_mempool *
601 mlx5_mb2mp(struct rte_mbuf *buf)
603 if (unlikely(RTE_MBUF_CLONED(buf)))
604 return rte_mbuf_from_indirect(buf)->pool;
609 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
610 * as mempool is pre-configured and static.
613 * Pointer to Rx queue structure.
618 * Searched LKey on success, UINT32_MAX on no match.
620 static __rte_always_inline uint32_t
621 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
623 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
626 /* Linear search on MR cache array. */
627 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
628 MLX5_MR_CACHE_N, addr);
629 if (likely(lkey != UINT32_MAX))
631 /* Take slower bottom-half (Binary Search) on miss. */
632 return mlx5_rx_addr2mr_bh(rxq, addr);
635 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
638 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
641 * Pointer to Tx queue structure.
646 * Searched LKey on success, UINT32_MAX on no match.
648 static __rte_always_inline uint32_t
649 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
651 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
652 uintptr_t addr = (uintptr_t)mb->buf_addr;
655 /* Check generation bit to see if there's any change on existing MRs. */
656 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
657 mlx5_mr_flush_local_cache(mr_ctrl);
658 /* Linear search on MR cache array. */
659 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
660 MLX5_MR_CACHE_N, addr);
661 if (likely(lkey != UINT32_MAX))
663 /* Take slower bottom-half on miss. */
664 return mlx5_tx_mb2mr_bh(txq, mb);
668 * Ring TX queue doorbell and flush the update if requested.
671 * Pointer to TX queue structure.
673 * Pointer to the last WQE posted in the NIC.
675 * Request for write memory barrier after BlueFlame update.
677 static __rte_always_inline void
678 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
681 uint64_t *dst = MLX5_TX_BFREG(txq);
682 volatile uint64_t *src = ((volatile uint64_t *)wqe);
685 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
686 /* Ensure ordering between DB record and BF copy. */
688 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
694 * Ring TX queue doorbell and flush the update by write memory barrier.
697 * Pointer to TX queue structure.
699 * Pointer to the last WQE posted in the NIC.
701 static __rte_always_inline void
702 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
704 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
707 #endif /* RTE_PMD_MLX5_RXTX_H_ */