1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 #include <rte_mempool.h>
15 #include <rte_common.h>
16 #include <rte_hexdump.h>
17 #include <rte_atomic.h>
18 #include <rte_spinlock.h>
20 #include <rte_bus_pci.h>
21 #include <rte_malloc.h>
22 #include <rte_cycles.h>
24 #include <mlx5_glue.h>
26 #include <mlx5_common.h>
27 #include <mlx5_common_mr.h>
29 #include "mlx5_defs.h"
30 #include "mlx5_utils.h"
32 #include "mlx5_autoconf.h"
34 /* Support tunnel matching. */
35 #define MLX5_FLOW_TUNNEL 10
37 /* Mbuf dynamic flag offset for inline. */
38 extern uint64_t rte_net_mlx5_dynf_inline_mask;
40 struct mlx5_rxq_stats {
41 #ifdef MLX5_PMD_SOFT_COUNTERS
42 uint64_t ipackets; /**< Total of successfully received packets. */
43 uint64_t ibytes; /**< Total of successfully received bytes. */
45 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
46 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
49 struct mlx5_txq_stats {
50 #ifdef MLX5_PMD_SOFT_COUNTERS
51 uint64_t opackets; /**< Total of successfully sent packets. */
52 uint64_t obytes; /**< Total of successfully sent bytes. */
54 uint64_t oerrors; /**< Total number of failed transmitted packets. */
59 /* Compressed CQE context. */
61 uint16_t ai; /* Array index. */
62 uint16_t ca; /* Current array index. */
63 uint16_t na; /* Next array index. */
64 uint16_t cq_ci; /* The next CQE. */
65 uint32_t cqe_cnt; /* Number of CQEs. */
68 /* Multi-Packet RQ buffer header. */
69 struct mlx5_mprq_buf {
70 struct rte_mempool *mp;
71 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
72 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
73 struct rte_mbuf_ext_shared_info shinfos[];
75 * Shared information per stride.
76 * More memory will be allocated for the first stride head-room and for
79 } __rte_cache_aligned;
81 /* Get pointer to the first stride. */
82 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
83 sizeof(struct mlx5_mprq_buf) + \
85 sizeof(struct rte_mbuf_ext_shared_info) + \
86 RTE_PKTMBUF_HEADROOM))
88 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
89 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
91 enum mlx5_rxq_err_state {
92 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
93 MLX5_RXQ_ERR_STATE_NEED_RESET,
94 MLX5_RXQ_ERR_STATE_NEED_READY,
97 /* RX queue descriptor. */
98 struct mlx5_rxq_data {
99 unsigned int csum:1; /* Enable checksum offloading. */
100 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
101 unsigned int rt_timestamp:1; /* Realtime timestamp format. */
102 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
103 unsigned int crc_present:1; /* CRC must be subtracted. */
104 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */
105 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
106 unsigned int elts_n:4; /* Log 2 of Mbufs. */
107 unsigned int rss_hash:1; /* RSS hash result is enabled. */
108 unsigned int mark:1; /* Marked flow available on the queue. */
109 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
110 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
111 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
112 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
113 unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */
114 unsigned int lro:1; /* Enable LRO. */
115 unsigned int dynf_meta:1; /* Dynamic metadata is configured. */
116 volatile uint32_t *rq_db;
117 volatile uint32_t *cq_db;
120 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
123 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
125 struct rxq_zip zip; /* Compressed context. */
126 uint16_t decompressed;
127 /* Number of ready mbufs decompressed from the CQ. */
129 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
130 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
132 volatile struct mlx5_cqe(*cqes)[];
135 struct rte_mbuf *(*elts)[];
136 struct mlx5_mprq_buf *(*mprq_bufs)[];
138 struct rte_mempool *mp;
139 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
140 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
141 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
142 uint16_t idx; /* Queue index. */
143 struct mlx5_rxq_stats stats;
144 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */
145 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
146 void *cq_uar; /* Verbs CQ user access region. */
147 uint32_t cqn; /* CQ number. */
148 uint8_t cq_arm_sn; /* CQ arm seq number. */
150 rte_spinlock_t *uar_lock_cq;
151 /* CQ (UAR) access lock required for 32bit implementations */
153 uint32_t tunnel; /* Tunnel information. */
154 uint64_t flow_meta_mask;
155 int32_t flow_meta_offset;
156 } __rte_cache_aligned;
159 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */
160 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
161 MLX5_RXQ_TYPE_UNDEFINED,
164 /* RX queue control descriptor. */
165 struct mlx5_rxq_ctrl {
166 struct mlx5_rxq_data rxq; /* Data path structure. */
167 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
168 rte_atomic32_t refcnt; /* Reference counter. */
169 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
170 struct mlx5_priv *priv; /* Back pointer to private data. */
171 enum mlx5_rxq_type type; /* Rxq type. */
172 unsigned int socket; /* CPU socket ID for allocations. */
173 unsigned int irq:1; /* Whether IRQ is enabled. */
174 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
175 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
176 uint32_t wqn; /* WQ number. */
177 uint16_t dump_file_n; /* Number of dump files. */
178 uint32_t rq_dbr_umem_id;
179 uint64_t rq_dbr_offset;
180 /* Storing RQ door-bell information, needed when freeing door-bell. */
181 uint32_t cq_dbr_umem_id;
182 uint64_t cq_dbr_offset;
183 /* Storing CQ door-bell information, needed when freeing door-bell. */
184 void *wq_umem; /* WQ buffer registration info. */
185 void *cq_umem; /* CQ buffer registration info. */
186 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
189 enum mlx5_ind_tbl_type {
190 MLX5_IND_TBL_TYPE_IBV,
191 MLX5_IND_TBL_TYPE_DEVX,
194 /* Indirection table. */
195 struct mlx5_ind_table_obj {
196 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
197 rte_atomic32_t refcnt; /* Reference counter. */
198 enum mlx5_ind_tbl_type type;
201 void *ind_table; /**< Indirection table. */
202 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
204 uint32_t queues_n; /**< Number of queues in the list. */
205 uint16_t queues[]; /**< Queue list. */
210 ILIST_ENTRY(uint32_t)next; /* Index to the next element. */
211 rte_atomic32_t refcnt; /* Reference counter. */
212 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
215 void *qp; /* Verbs queue pair. */
216 struct mlx5_devx_obj *tir; /* DevX TIR object. */
218 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
219 void *action; /* DV QP action pointer. */
221 uint64_t hash_fields; /* Verbs Hash fields. */
222 uint32_t rss_key_len; /* Hash key length in bytes. */
223 uint8_t rss_key[]; /* Hash key. */
226 /* TX queue send local data. */
228 struct mlx5_txq_local {
229 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
230 struct rte_mbuf *mbuf; /* first mbuf to process. */
231 uint16_t pkts_copy; /* packets copied to elts. */
232 uint16_t pkts_sent; /* packets sent. */
233 uint16_t pkts_loop; /* packets sent on loop entry. */
234 uint16_t elts_free; /* available elts remain. */
235 uint16_t wqe_free; /* available wqe remain. */
236 uint16_t mbuf_off; /* data offset in current mbuf. */
237 uint16_t mbuf_nseg; /* number of remaining mbuf. */
240 /* TX queue descriptor. */
242 struct mlx5_txq_data {
243 uint16_t elts_head; /* Current counter in (*elts)[]. */
244 uint16_t elts_tail; /* Counter of first element awaiting completion. */
245 uint16_t elts_comp; /* elts index since last completion request. */
246 uint16_t elts_s; /* Number of mbuf elements. */
247 uint16_t elts_m; /* Mask for mbuf elements indices. */
248 /* Fields related to elts mbuf storage. */
249 uint16_t wqe_ci; /* Consumer index for work queue. */
250 uint16_t wqe_pi; /* Producer index for work queue. */
251 uint16_t wqe_s; /* Number of WQ elements. */
252 uint16_t wqe_m; /* Mask Number for WQ elements. */
253 uint16_t wqe_comp; /* WQE index since last completion request. */
254 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
255 /* WQ related fields. */
256 uint16_t cq_ci; /* Consumer index for completion queue. */
257 uint16_t cq_pi; /* Production index for completion queue. */
258 uint16_t cqe_s; /* Number of CQ elements. */
259 uint16_t cqe_m; /* Mask for CQ indices. */
260 /* CQ related fields. */
261 uint16_t elts_n:4; /* elts[] length (in log2). */
262 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
263 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
264 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
265 uint16_t tunnel_en:1;
266 /* When set TX offload for tunneled packets are supported. */
267 uint16_t swp_en:1; /* Whether SW parser is enabled. */
268 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
269 uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */
270 uint16_t db_heu:1; /* Doorbell heuristic write barrier. */
271 uint16_t inlen_send; /* Ordinary send data inline size. */
272 uint16_t inlen_empw; /* eMPW max packet size to inline. */
273 uint16_t inlen_mode; /* Minimal data length to inline. */
274 uint32_t qp_num_8s; /* QP number shifted by 8. */
275 uint64_t offloads; /* Offloads for Tx Queue. */
276 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
277 struct mlx5_wqe *wqes; /* Work queue. */
278 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
279 #ifdef RTE_LIBRTE_MLX5_DEBUG
280 uint32_t *fcqs; /* Free completion queue (debug extended). */
282 uint16_t *fcqs; /* Free completion queue. */
284 volatile struct mlx5_cqe *cqes; /* Completion queue. */
285 volatile uint32_t *qp_db; /* Work queue doorbell. */
286 volatile uint32_t *cq_db; /* Completion queue doorbell. */
287 uint16_t port_id; /* Port ID of device. */
288 uint16_t idx; /* Queue index. */
289 uint64_t ts_mask; /* Timestamp flag dynamic mask. */
290 int32_t ts_offset; /* Timestamp field dynamic offset. */
291 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
292 struct mlx5_txq_stats stats; /* TX queue counters. */
294 rte_spinlock_t *uar_lock;
295 /* UAR access lock required for 32bit implementations */
297 struct rte_mbuf *elts[0];
298 /* Storage for queued packets, must be the last field. */
299 } __rte_cache_aligned;
301 enum mlx5_txq_obj_type {
302 MLX5_TXQ_OBJ_TYPE_IBV, /* mlx5_txq_obj with ibv_wq. */
303 MLX5_TXQ_OBJ_TYPE_DEVX_SQ, /* mlx5_txq_obj with mlx5_devx_sq. */
304 MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN,
305 /* mlx5_txq_obj with mlx5_devx_tq and hairpin support. */
309 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
310 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
313 /* Verbs/DevX Tx queue elements. */
314 struct mlx5_txq_obj {
315 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
316 rte_atomic32_t refcnt; /* Reference counter. */
317 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
318 enum mlx5_txq_obj_type type; /* The txq object type. */
322 void *cq; /* Completion Queue. */
323 void *qp; /* Queue Pair. */
326 struct mlx5_devx_obj *sq;
327 /* DevX object for Sx queue. */
328 struct mlx5_devx_obj *tis; /* The TIS object. */
331 struct rte_eth_dev *dev;
332 struct mlx5_devx_obj *cq_devx;
335 int64_t cq_dbrec_offset;
336 struct mlx5_devx_dbr_page *cq_dbrec_page;
337 struct mlx5_devx_obj *sq_devx;
340 int64_t sq_dbrec_offset;
341 struct mlx5_devx_dbr_page *sq_dbrec_page;
346 /* TX queue control descriptor. */
347 struct mlx5_txq_ctrl {
348 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
349 rte_atomic32_t refcnt; /* Reference counter. */
350 unsigned int socket; /* CPU socket ID for allocations. */
351 enum mlx5_txq_type type; /* The txq ctrl type. */
352 unsigned int max_inline_data; /* Max inline data. */
353 unsigned int max_tso_header; /* Max TSO header size. */
354 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */
355 struct mlx5_priv *priv; /* Back pointer to private data. */
356 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
357 void *bf_reg; /* BlueFlame register from Verbs. */
358 uint16_t dump_file_n; /* Number of dump files. */
359 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
360 struct mlx5_txq_data txq; /* Data path structure. */
361 /* Must be the last field in the structure, contains elts[]. */
364 #define MLX5_TX_BFREG(txq) \
365 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
369 extern uint8_t rss_hash_default_key[];
371 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
372 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
373 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
374 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
375 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
376 int mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id);
377 int mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id);
378 int mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id);
379 int mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id);
380 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
381 unsigned int socket, const struct rte_eth_rxconf *conf,
382 struct rte_mempool *mp);
383 int mlx5_rx_hairpin_queue_setup
384 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
385 const struct rte_eth_hairpin_conf *hairpin_conf);
386 void mlx5_rx_queue_release(void *dpdk_rxq);
387 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
388 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
389 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
390 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
391 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
392 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
393 uint16_t desc, unsigned int socket,
394 const struct rte_eth_rxconf *conf,
395 struct rte_mempool *mp);
396 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new
397 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
398 const struct rte_eth_hairpin_conf *hairpin_conf);
399 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
400 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
401 int mlx5_rxq_verify(struct rte_eth_dev *dev);
402 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
403 void rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
404 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
405 uint32_t mlx5_hrxq_new(struct rte_eth_dev *dev,
406 const uint8_t *rss_key, uint32_t rss_key_len,
407 uint64_t hash_fields,
408 const uint16_t *queues, uint32_t queues_n,
409 int tunnel __rte_unused);
410 uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,
411 const uint8_t *rss_key, uint32_t rss_key_len,
412 uint64_t hash_fields,
413 const uint16_t *queues, uint32_t queues_n);
414 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx);
415 int mlx5_hrxq_verify(struct rte_eth_dev *dev);
416 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx);
417 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
418 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
419 uint64_t mlx5_get_rx_port_offloads(void);
420 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
421 void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev);
426 int mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id);
427 int mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id);
428 int mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id);
429 int mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id);
430 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
431 unsigned int socket, const struct rte_eth_txconf *conf);
432 int mlx5_tx_hairpin_queue_setup
433 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
434 const struct rte_eth_hairpin_conf *hairpin_conf);
435 void mlx5_tx_queue_release(void *dpdk_txq);
436 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
437 void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev);
438 struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
439 enum mlx5_txq_obj_type type);
440 struct mlx5_txq_obj *mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx);
441 int mlx5_txq_obj_release(struct mlx5_txq_obj *txq_ibv);
442 int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
443 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
444 uint16_t desc, unsigned int socket,
445 const struct rte_eth_txconf *conf);
446 struct mlx5_txq_ctrl *mlx5_txq_hairpin_new
447 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
448 const struct rte_eth_hairpin_conf *hairpin_conf);
449 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
450 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
451 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
452 int mlx5_txq_verify(struct rte_eth_dev *dev);
453 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
454 void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);
455 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
456 void mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev);
460 extern uint32_t mlx5_ptype_table[];
461 extern uint8_t mlx5_cksum_table[];
462 extern uint8_t mlx5_swp_types_table[];
464 void mlx5_set_ptype_table(void);
465 void mlx5_set_cksum_table(void);
466 void mlx5_set_swp_types_table(void);
467 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
468 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
469 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);
470 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
471 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
472 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
474 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
476 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
478 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
479 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
480 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
481 void mlx5_dump_debug_information(const char *path, const char *title,
482 const void *buf, unsigned int len);
483 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
484 const struct mlx5_mp_arg_queue_state_modify *sm);
485 void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
486 struct rte_eth_rxq_info *qinfo);
487 void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
488 struct rte_eth_txq_info *qinfo);
489 int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
490 struct rte_eth_burst_mode *mode);
491 int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
492 struct rte_eth_burst_mode *mode);
494 /* Vectorized version of mlx5_rxtx.c */
495 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
496 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
497 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
502 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
503 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
504 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
505 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
506 struct rte_mempool *mp);
507 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
509 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
513 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
514 * 64bit architectures.
517 * value to write in CPU endian format.
519 * Address to write to.
521 * Address of the lock to use for that UAR access.
523 static __rte_always_inline void
524 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
525 rte_spinlock_t *lock __rte_unused)
528 *(uint64_t *)addr = val;
529 #else /* !RTE_ARCH_64 */
530 rte_spinlock_lock(lock);
531 *(uint32_t *)addr = val;
533 *((uint32_t *)addr + 1) = val >> 32;
534 rte_spinlock_unlock(lock);
539 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
540 * 64bit architectures while guaranteeing the order of execution with the
541 * code being executed.
544 * value to write in CPU endian format.
546 * Address to write to.
548 * Address of the lock to use for that UAR access.
550 static __rte_always_inline void
551 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
554 __mlx5_uar_write64_relaxed(val, addr, lock);
557 /* Assist macros, used instead of directly calling the functions they wrap. */
559 #define mlx5_uar_write64_relaxed(val, dst, lock) \
560 __mlx5_uar_write64_relaxed(val, dst, NULL)
561 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
563 #define mlx5_uar_write64_relaxed(val, dst, lock) \
564 __mlx5_uar_write64_relaxed(val, dst, lock)
565 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
569 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
570 * cloned mbuf is allocated is returned instead.
576 * Memory pool where data is located for given mbuf.
578 static inline struct rte_mempool *
579 mlx5_mb2mp(struct rte_mbuf *buf)
581 if (unlikely(RTE_MBUF_CLONED(buf)))
582 return rte_mbuf_from_indirect(buf)->pool;
587 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
588 * as mempool is pre-configured and static.
591 * Pointer to Rx queue structure.
596 * Searched LKey on success, UINT32_MAX on no match.
598 static __rte_always_inline uint32_t
599 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
601 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
604 /* Linear search on MR cache array. */
605 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
606 MLX5_MR_CACHE_N, addr);
607 if (likely(lkey != UINT32_MAX))
609 /* Take slower bottom-half (Binary Search) on miss. */
610 return mlx5_rx_addr2mr_bh(rxq, addr);
613 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
616 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
619 * Pointer to Tx queue structure.
624 * Searched LKey on success, UINT32_MAX on no match.
626 static __rte_always_inline uint32_t
627 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
629 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
630 uintptr_t addr = (uintptr_t)mb->buf_addr;
633 /* Check generation bit to see if there's any change on existing MRs. */
634 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
635 mlx5_mr_flush_local_cache(mr_ctrl);
636 /* Linear search on MR cache array. */
637 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
638 MLX5_MR_CACHE_N, addr);
639 if (likely(lkey != UINT32_MAX))
641 /* Take slower bottom-half on miss. */
642 return mlx5_tx_mb2mr_bh(txq, mb);
646 * Ring TX queue doorbell and flush the update if requested.
649 * Pointer to TX queue structure.
651 * Pointer to the last WQE posted in the NIC.
653 * Request for write memory barrier after BlueFlame update.
655 static __rte_always_inline void
656 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
659 uint64_t *dst = MLX5_TX_BFREG(txq);
660 volatile uint64_t *src = ((volatile uint64_t *)wqe);
663 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
664 /* Ensure ordering between DB record and BF copy. */
666 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
672 * Ring TX queue doorbell and flush the update by write memory barrier.
675 * Pointer to TX queue structure.
677 * Pointer to the last WQE posted in the NIC.
679 static __rte_always_inline void
680 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
682 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
686 * Convert timestamp from HW format to linear counter
687 * from Packet Pacing Clock Queue CQE timestamp format.
690 * Pointer to the device shared context. Might be needed
691 * to convert according current device configuration.
693 * Timestamp from CQE to convert.
697 static __rte_always_inline uint64_t
698 mlx5_txpp_convert_rx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t ts)
701 return (ts & UINT32_MAX) + (ts >> 32) * NS_PER_S;
705 * Convert timestamp from mbuf format to linear counter
706 * of Clock Queue completions (24 bits)
709 * Pointer to the device shared context to fetch Tx
710 * packet pacing timestamp and parameters.
712 * Timestamp from mbuf to convert.
714 * positive or zero value - completion ID to wait
715 * negative value - conversion error
717 static __rte_always_inline int32_t
718 mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts)
725 * Read atomically two uint64_t fields and compare lsb bits.
726 * It there is no match - the timestamp was updated in
727 * the service thread, data should be re-read.
729 rte_compiler_barrier();
730 ci = rte_atomic64_read(&sh->txpp.ts.ci_ts);
731 ts = rte_atomic64_read(&sh->txpp.ts.ts);
732 rte_compiler_barrier();
733 if (!((ts ^ ci) << (64 - MLX5_CQ_INDEX_WIDTH)))
736 /* Perform the skew correction, positive value to send earlier. */
737 mts -= sh->txpp.skew;
739 if (unlikely(mts >= UINT64_MAX / 2)) {
740 /* We have negative integer, mts is in the past. */
741 rte_atomic32_inc(&sh->txpp.err_ts_past);
744 tick = sh->txpp.tick;
746 /* Convert delta to completions, round up. */
747 mts = (mts + tick - 1) / tick;
748 if (unlikely(mts >= (1 << MLX5_CQ_INDEX_WIDTH) / 2 - 1)) {
749 /* We have mts is too distant future. */
750 rte_atomic32_inc(&sh->txpp.err_ts_future);
753 mts <<= 64 - MLX5_CQ_INDEX_WIDTH;
755 ci >>= 64 - MLX5_CQ_INDEX_WIDTH;
759 #endif /* RTE_PMD_MLX5_RXTX_H_ */