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34 #ifndef RTE_PMD_MLX5_RXTX_H_
35 #define RTE_PMD_MLX5_RXTX_H_
39 #include <sys/queue.h>
42 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
44 #pragma GCC diagnostic ignored "-Wpedantic"
46 #include <infiniband/verbs.h>
47 #include <infiniband/mlx5dv.h>
49 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_mempool.h>
54 #include <rte_common.h>
55 #include <rte_hexdump.h>
56 #include <rte_atomic.h>
58 #include "mlx5_utils.h"
60 #include "mlx5_autoconf.h"
61 #include "mlx5_defs.h"
64 struct mlx5_rxq_stats {
65 unsigned int idx; /**< Mapping index. */
66 #ifdef MLX5_PMD_SOFT_COUNTERS
67 uint64_t ipackets; /**< Total of successfully received packets. */
68 uint64_t ibytes; /**< Total of successfully received bytes. */
70 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
71 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
74 struct mlx5_txq_stats {
75 unsigned int idx; /**< Mapping index. */
76 #ifdef MLX5_PMD_SOFT_COUNTERS
77 uint64_t opackets; /**< Total of successfully sent packets. */
78 uint64_t obytes; /**< Total of successfully sent bytes. */
80 uint64_t oerrors; /**< Total number of failed transmitted packets. */
85 /* Memory region queue object. */
87 LIST_ENTRY(mlx5_mr) next; /**< Pointer to the next element. */
88 rte_atomic32_t refcnt; /*<< Reference counter. */
89 uint32_t lkey; /*<< rte_cpu_to_be_32(mr->lkey) */
90 uintptr_t start; /* Start address of MR */
91 uintptr_t end; /* End address of MR */
92 struct ibv_mr *mr; /*<< Memory Region. */
93 struct rte_mempool *mp; /*<< Memory Pool. */
96 /* Compressed CQE context. */
98 uint16_t ai; /* Array index. */
99 uint16_t ca; /* Current array index. */
100 uint16_t na; /* Next array index. */
101 uint16_t cq_ci; /* The next CQE. */
102 uint32_t cqe_cnt; /* Number of CQEs. */
105 /* RX queue descriptor. */
106 struct mlx5_rxq_data {
107 unsigned int csum:1; /* Enable checksum offloading. */
108 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
109 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
110 unsigned int crc_present:1; /* CRC must be subtracted. */
111 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
112 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
113 unsigned int elts_n:4; /* Log 2 of Mbufs. */
114 unsigned int rss_hash:1; /* RSS hash result is enabled. */
115 unsigned int mark:1; /* Marked flow available on the queue. */
116 unsigned int pending_err:1; /* CQE error needs to be handled. */
117 unsigned int :15; /* Remaining bits. */
118 volatile uint32_t *rq_db;
119 volatile uint32_t *cq_db;
124 volatile struct mlx5_wqe_data_seg(*wqes)[];
125 volatile struct mlx5_cqe(*cqes)[];
126 struct rxq_zip zip; /* Compressed context. */
127 struct rte_mbuf *(*elts)[];
128 struct rte_mempool *mp;
129 struct mlx5_rxq_stats stats;
130 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
131 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
132 void *cq_uar; /* CQ user access region. */
133 uint32_t cqn; /* CQ number. */
134 uint8_t cq_arm_sn; /* CQ arm seq number. */
135 } __rte_cache_aligned;
137 /* Verbs Rx queue elements. */
138 struct mlx5_rxq_ibv {
139 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
140 rte_atomic32_t refcnt; /* Reference counter. */
141 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
142 struct ibv_cq *cq; /* Completion Queue. */
143 struct ibv_wq *wq; /* Work Queue. */
144 struct ibv_comp_channel *channel;
145 struct mlx5_mr *mr; /* Memory Region (for mp). */
148 /* RX queue control descriptor. */
149 struct mlx5_rxq_ctrl {
150 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
151 rte_atomic32_t refcnt; /* Reference counter. */
152 struct priv *priv; /* Back pointer to private data. */
153 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
154 struct mlx5_rxq_data rxq; /* Data path structure. */
155 unsigned int socket; /* CPU socket ID for allocations. */
156 unsigned int irq:1; /* Whether IRQ is enabled. */
159 /* Indirection table. */
160 struct mlx5_ind_table_ibv {
161 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
162 rte_atomic32_t refcnt; /* Reference counter. */
163 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
164 uint16_t queues_n; /**< Number of queues in the list. */
165 uint16_t queues[]; /**< Queue list. */
170 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
171 rte_atomic32_t refcnt; /* Reference counter. */
172 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
173 struct ibv_qp *qp; /* Verbs queue pair. */
174 uint64_t hash_fields; /* Verbs Hash fields. */
175 uint8_t rss_key_len; /* Hash key length in bytes. */
176 uint8_t rss_key[]; /* Hash key. */
179 /* Hash RX queue types. */
190 /* Flow structure with Ethernet specification. It is packed to prevent padding
191 * between attr and spec as this layout is expected by libibverbs. */
192 struct flow_attr_spec_eth {
193 struct ibv_flow_attr attr;
194 struct ibv_flow_spec_eth spec;
195 } __attribute__((packed));
197 /* Define a struct flow_attr_spec_eth object as an array of at least
198 * "size" bytes. Room after the first index is normally used to store
199 * extra flow specifications. */
200 #define FLOW_ATTR_SPEC_ETH(name, size) \
201 struct flow_attr_spec_eth name \
202 [((size) / sizeof(struct flow_attr_spec_eth)) + \
203 !!((size) % sizeof(struct flow_attr_spec_eth))]
205 /* Initialization data for hash RX queue. */
206 struct hash_rxq_init {
207 uint64_t hash_fields; /* Fields that participate in the hash. */
208 uint64_t dpdk_rss_hf; /* Matching DPDK RSS hash fields. */
209 unsigned int flow_priority; /* Flow priority to use. */
212 enum ibv_flow_spec_type type;
215 struct ibv_flow_spec_tcp_udp tcp_udp;
216 struct ibv_flow_spec_ipv4 ipv4;
217 struct ibv_flow_spec_ipv6 ipv6;
218 struct ibv_flow_spec_eth eth;
219 } flow_spec; /* Flow specification template. */
220 const struct hash_rxq_init *underlayer; /* Pointer to underlayer. */
223 /* Initialization data for indirection table. */
224 struct ind_table_init {
225 unsigned int max_size; /* Maximum number of WQs. */
226 /* Hash RX queues using this table. */
227 unsigned int hash_types;
228 unsigned int hash_types_n;
231 /* Initialization data for special flows. */
232 struct special_flow_init {
233 uint8_t dst_mac_val[6];
234 uint8_t dst_mac_mask[6];
235 unsigned int hash_types;
236 unsigned int per_vlan:1;
239 enum hash_rxq_flow_type {
240 HASH_RXQ_FLOW_TYPE_PROMISC,
241 HASH_RXQ_FLOW_TYPE_ALLMULTI,
242 HASH_RXQ_FLOW_TYPE_BROADCAST,
243 HASH_RXQ_FLOW_TYPE_IPV6MULTI,
244 HASH_RXQ_FLOW_TYPE_MAC,
248 static inline const char *
249 hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type)
252 case HASH_RXQ_FLOW_TYPE_PROMISC:
253 return "promiscuous";
254 case HASH_RXQ_FLOW_TYPE_ALLMULTI:
255 return "allmulticast";
256 case HASH_RXQ_FLOW_TYPE_BROADCAST:
258 case HASH_RXQ_FLOW_TYPE_IPV6MULTI:
259 return "IPv6 multicast";
260 case HASH_RXQ_FLOW_TYPE_MAC:
268 struct priv *priv; /* Back pointer to private data. */
269 struct ibv_qp *qp; /* Hash RX QP. */
270 enum hash_rxq_type type; /* Hash RX queue type. */
271 /* MAC flow steering rules, one per VLAN ID. */
272 struct ibv_flow *mac_flow
273 [MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS];
274 struct ibv_flow *special_flow
275 [MLX5_MAX_SPECIAL_FLOWS][MLX5_MAX_VLAN_IDS];
278 /* TX queue descriptor. */
280 struct mlx5_txq_data {
281 uint16_t elts_head; /* Current counter in (*elts)[]. */
282 uint16_t elts_tail; /* Counter of first element awaiting completion. */
283 uint16_t elts_comp; /* Counter since last completion request. */
284 uint16_t mpw_comp; /* WQ index since last completion request. */
285 uint16_t cq_ci; /* Consumer index for completion queue. */
286 uint16_t cq_pi; /* Producer index for completion queue. */
287 uint16_t wqe_ci; /* Consumer index for work queue. */
288 uint16_t wqe_pi; /* Producer index for work queue. */
289 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
290 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
291 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
292 uint16_t inline_en:1; /* When set inline is enabled. */
293 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
294 uint16_t tunnel_en:1;
295 /* When set TX offload for tunneled packets are supported. */
296 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
297 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
298 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
299 uint16_t mr_cache_idx; /* Index of last hit entry. */
300 uint32_t qp_num_8s; /* QP number shifted by 8. */
301 uint32_t flags; /* Flags for Tx Queue. */
302 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
303 volatile void *wqes; /* Work queue (use volatile to write into). */
304 volatile uint32_t *qp_db; /* Work queue doorbell. */
305 volatile uint32_t *cq_db; /* Completion queue doorbell. */
306 volatile void *bf_reg; /* Blueflame register. */
307 struct mlx5_mr *mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MR translation table. */
308 struct rte_mbuf *(*elts)[]; /* TX elements. */
309 struct mlx5_txq_stats stats; /* TX queue counters. */
310 } __rte_cache_aligned;
312 /* Verbs Rx queue elements. */
313 struct mlx5_txq_ibv {
314 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
315 rte_atomic32_t refcnt; /* Reference counter. */
316 struct ibv_cq *cq; /* Completion Queue. */
317 struct ibv_qp *qp; /* Queue Pair. */
320 /* TX queue control descriptor. */
321 struct mlx5_txq_ctrl {
322 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
323 rte_atomic32_t refcnt; /* Reference counter. */
324 struct priv *priv; /* Back pointer to private data. */
325 unsigned int socket; /* CPU socket ID for allocations. */
326 unsigned int max_inline_data; /* Max inline data. */
327 unsigned int max_tso_header; /* Max TSO header size. */
328 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
329 struct mlx5_txq_data txq; /* Data path structure. */
330 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
335 extern const struct hash_rxq_init hash_rxq_init[];
336 extern const unsigned int hash_rxq_init_n;
338 extern uint8_t rss_hash_default_key[];
339 extern const size_t rss_hash_default_key_len;
341 size_t priv_flow_attr(struct priv *, struct ibv_flow_attr *,
342 size_t, enum hash_rxq_type);
343 int priv_create_hash_rxqs(struct priv *);
344 void priv_destroy_hash_rxqs(struct priv *);
345 int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type);
346 int priv_rehash_flows(struct priv *);
347 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *);
348 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
349 const struct rte_eth_rxconf *, struct rte_mempool *);
350 void mlx5_rx_queue_release(void *);
351 int priv_rx_intr_vec_enable(struct priv *priv);
352 void priv_rx_intr_vec_disable(struct priv *priv);
353 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
354 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
355 struct mlx5_rxq_ibv *mlx5_priv_rxq_ibv_new(struct priv *, uint16_t);
356 struct mlx5_rxq_ibv *mlx5_priv_rxq_ibv_get(struct priv *, uint16_t);
357 int mlx5_priv_rxq_ibv_release(struct priv *, struct mlx5_rxq_ibv *);
358 int mlx5_priv_rxq_ibv_releasable(struct priv *, struct mlx5_rxq_ibv *);
359 int mlx5_priv_rxq_ibv_verify(struct priv *);
360 struct mlx5_rxq_ctrl *mlx5_priv_rxq_new(struct priv *, uint16_t,
361 uint16_t, unsigned int,
362 struct rte_mempool *);
363 struct mlx5_rxq_ctrl *mlx5_priv_rxq_get(struct priv *, uint16_t);
364 int mlx5_priv_rxq_release(struct priv *, uint16_t);
365 int mlx5_priv_rxq_releasable(struct priv *, uint16_t);
366 int mlx5_priv_rxq_verify(struct priv *);
367 int rxq_alloc_elts(struct mlx5_rxq_ctrl *);
368 struct mlx5_ind_table_ibv *mlx5_priv_ind_table_ibv_new(struct priv *,
371 struct mlx5_ind_table_ibv *mlx5_priv_ind_table_ibv_get(struct priv *,
374 int mlx5_priv_ind_table_ibv_release(struct priv *, struct mlx5_ind_table_ibv *);
375 int mlx5_priv_ind_table_ibv_verify(struct priv *);
376 struct mlx5_hrxq *mlx5_priv_hrxq_new(struct priv *, uint8_t *, uint8_t,
377 uint64_t, uint16_t [], uint16_t);
378 struct mlx5_hrxq *mlx5_priv_hrxq_get(struct priv *, uint8_t *, uint8_t,
379 uint64_t, uint16_t [], uint16_t);
380 int mlx5_priv_hrxq_release(struct priv *, struct mlx5_hrxq *);
381 int mlx5_priv_hrxq_ibv_verify(struct priv *);
385 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
386 const struct rte_eth_txconf *);
387 void mlx5_tx_queue_release(void *);
388 int priv_tx_uar_remap(struct priv *priv, int fd);
389 struct mlx5_txq_ibv *mlx5_priv_txq_ibv_new(struct priv *, uint16_t);
390 struct mlx5_txq_ibv *mlx5_priv_txq_ibv_get(struct priv *, uint16_t);
391 int mlx5_priv_txq_ibv_release(struct priv *, struct mlx5_txq_ibv *);
392 int mlx5_priv_txq_ibv_releasable(struct priv *, struct mlx5_txq_ibv *);
393 int mlx5_priv_txq_ibv_verify(struct priv *);
394 struct mlx5_txq_ctrl *mlx5_priv_txq_new(struct priv *, uint16_t,
395 uint16_t, unsigned int,
396 const struct rte_eth_txconf *);
397 struct mlx5_txq_ctrl *mlx5_priv_txq_get(struct priv *, uint16_t);
398 int mlx5_priv_txq_release(struct priv *, uint16_t);
399 int mlx5_priv_txq_releasable(struct priv *, uint16_t);
400 int mlx5_priv_txq_verify(struct priv *);
401 void txq_alloc_elts(struct mlx5_txq_ctrl *);
405 extern uint32_t mlx5_ptype_table[];
407 void mlx5_set_ptype_table(void);
408 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
409 uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
410 uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
411 uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t);
412 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
413 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
414 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
415 int mlx5_rx_descriptor_status(void *, uint16_t);
416 int mlx5_tx_descriptor_status(void *, uint16_t);
418 /* Vectorized version of mlx5_rxtx.c */
419 int priv_check_raw_vec_tx_support(struct priv *);
420 int priv_check_vec_tx_support(struct priv *);
421 int rxq_check_vec_support(struct mlx5_rxq_data *);
422 int priv_check_vec_rx_support(struct priv *);
423 uint16_t mlx5_tx_burst_raw_vec(void *, struct rte_mbuf **, uint16_t);
424 uint16_t mlx5_tx_burst_vec(void *, struct rte_mbuf **, uint16_t);
425 uint16_t mlx5_rx_burst_vec(void *, struct rte_mbuf **, uint16_t);
429 void mlx5_mp2mr_iter(struct rte_mempool *, void *);
430 struct mlx5_mr *priv_txq_mp2mr_reg(struct priv *priv, struct mlx5_txq_data *,
431 struct rte_mempool *, unsigned int);
432 struct mlx5_mr *mlx5_txq_mp2mr_reg(struct mlx5_txq_data *, struct rte_mempool *,
437 * Verify or set magic value in CQE.
446 check_cqe_seen(volatile struct mlx5_cqe *cqe)
448 static const uint8_t magic[] = "seen";
449 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
453 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
454 if (!ret || (*buf)[i] != magic[i]) {
456 (*buf)[i] = magic[i];
463 * Check whether CQE is valid.
468 * Size of completion queue.
473 * 0 on success, 1 on failure.
475 static __rte_always_inline int
476 check_cqe(volatile struct mlx5_cqe *cqe,
477 unsigned int cqes_n, const uint16_t ci)
479 uint16_t idx = ci & cqes_n;
480 uint8_t op_own = cqe->op_own;
481 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
482 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
484 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
485 return 1; /* No CQE. */
487 if ((op_code == MLX5_CQE_RESP_ERR) ||
488 (op_code == MLX5_CQE_REQ_ERR)) {
489 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
490 uint8_t syndrome = err_cqe->syndrome;
492 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
493 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
495 if (!check_cqe_seen(cqe)) {
496 ERROR("unexpected CQE error %u (0x%02x)"
498 op_code, op_code, syndrome);
499 rte_hexdump(stderr, "MLX5 Error CQE:",
500 (const void *)((uintptr_t)err_cqe),
504 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
505 (op_code != MLX5_CQE_REQ)) {
506 if (!check_cqe_seen(cqe)) {
507 ERROR("unexpected CQE opcode %u (0x%02x)",
509 rte_hexdump(stderr, "MLX5 CQE:",
510 (const void *)((uintptr_t)cqe),
520 * Return the address of the WQE.
523 * Pointer to TX queue structure.
525 * WQE consumer index.
530 static inline uintptr_t *
531 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
533 ci &= ((1 << txq->wqe_n) - 1);
534 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
538 * Manage TX completions.
540 * When sending a burst, mlx5_tx_burst() posts several WRs.
543 * Pointer to TX queue structure.
545 static __rte_always_inline void
546 mlx5_tx_complete(struct mlx5_txq_data *txq)
548 const uint16_t elts_n = 1 << txq->elts_n;
549 const uint16_t elts_m = elts_n - 1;
550 const unsigned int cqe_n = 1 << txq->cqe_n;
551 const unsigned int cqe_cnt = cqe_n - 1;
552 uint16_t elts_free = txq->elts_tail;
554 uint16_t cq_ci = txq->cq_ci;
555 volatile struct mlx5_cqe *cqe = NULL;
556 volatile struct mlx5_wqe_ctrl *ctrl;
557 struct rte_mbuf *m, *free[elts_n];
558 struct rte_mempool *pool = NULL;
559 unsigned int blk_n = 0;
561 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
562 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
565 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
566 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
567 if (!check_cqe_seen(cqe)) {
568 ERROR("unexpected error CQE, TX stopped");
569 rte_hexdump(stderr, "MLX5 TXQ:",
570 (const void *)((uintptr_t)txq->wqes),
578 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
579 ctrl = (volatile struct mlx5_wqe_ctrl *)
580 tx_mlx5_wqe(txq, txq->wqe_pi);
581 elts_tail = ctrl->ctrl3;
582 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
584 while (elts_free != elts_tail) {
585 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
586 if (likely(m != NULL)) {
587 if (likely(m->pool == pool)) {
590 if (likely(pool != NULL))
591 rte_mempool_put_bulk(pool,
601 rte_mempool_put_bulk(pool, (void *)free, blk_n);
603 elts_free = txq->elts_tail;
605 while (elts_free != elts_tail) {
606 memset(&(*txq->elts)[elts_free & elts_m],
608 sizeof((*txq->elts)[elts_free & elts_m]));
613 txq->elts_tail = elts_tail;
614 /* Update the consumer index. */
616 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
620 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
621 * the cloned mbuf is allocated is returned instead.
627 * Memory pool where data is located for given mbuf.
629 static struct rte_mempool *
630 mlx5_tx_mb2mp(struct rte_mbuf *buf)
632 if (unlikely(RTE_MBUF_INDIRECT(buf)))
633 return rte_mbuf_from_indirect(buf)->pool;
638 * Get Memory Region (MR) <-> rte_mbuf association from txq->mp2mr[].
639 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
640 * remove an entry first.
643 * Pointer to TX queue structure.
645 * Memory Pool for which a Memory Region lkey must be returned.
648 * mr->lkey on success, (uint32_t)-1 on failure.
650 static __rte_always_inline uint32_t
651 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
653 uint16_t i = txq->mr_cache_idx;
654 uintptr_t addr = rte_pktmbuf_mtod(mb, uintptr_t);
657 assert(i < RTE_DIM(txq->mp2mr));
658 if (likely(txq->mp2mr[i]->start <= addr && txq->mp2mr[i]->end >= addr))
659 return txq->mp2mr[i]->lkey;
660 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
661 if (unlikely(txq->mp2mr[i]->mr == NULL)) {
662 /* Unknown MP, add a new MR for it. */
665 if (txq->mp2mr[i]->start <= addr &&
666 txq->mp2mr[i]->end >= addr) {
667 assert(txq->mp2mr[i]->lkey != (uint32_t)-1);
668 assert(rte_cpu_to_be_32(txq->mp2mr[i]->mr->lkey) ==
669 txq->mp2mr[i]->lkey);
670 txq->mr_cache_idx = i;
671 return txq->mp2mr[i]->lkey;
674 txq->mr_cache_idx = 0;
675 mr = mlx5_txq_mp2mr_reg(txq, mlx5_tx_mb2mp(mb), i);
677 * Request the reference to use in this queue, the original one is
678 * kept by the control plane.
681 rte_atomic32_inc(&mr->refcnt);
688 * Ring TX queue doorbell.
691 * Pointer to TX queue structure.
693 * Pointer to the last WQE posted in the NIC.
695 static __rte_always_inline void
696 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
698 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
699 volatile uint64_t *src = ((volatile uint64_t *)wqe);
702 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
703 /* Ensure ordering between DB record and BF copy. */
708 #endif /* RTE_PMD_MLX5_RXTX_H_ */