1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_
7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_
16 #include <rte_mempool.h>
17 #include <rte_prefetch.h>
21 #include "mlx5_defs.h"
23 #include "mlx5_utils.h"
24 #include "mlx5_rxtx.h"
25 #include "mlx5_rxtx_vec.h"
26 #include "mlx5_autoconf.h"
28 #pragma GCC diagnostic ignored "-Wcast-qual"
31 * Store free buffers to RX SW ring.
34 * Pointer to RX queue structure.
36 * Pointer to array of packets to be stored.
38 * Number of packets to be stored.
41 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
43 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
44 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
48 for (pos = 0; pos < p; pos += 2) {
51 mbp = vld1q_u64((void *)&elts[pos]);
52 vst1q_u64((void *)&pkts[pos], mbp);
55 pkts[pos] = elts[pos];
59 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
60 * extracted from the title completion descriptor.
63 * Pointer to RX queue structure.
65 * Pointer to completion array having a compressed completion at first.
67 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
68 * the title completion descriptor to be copied to the rest of mbufs.
71 * Number of mini-CQEs successfully decompressed.
73 static inline uint16_t
74 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
75 struct rte_mbuf **elts)
77 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info;
78 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
82 /* Mask to shuffle from extracted mini CQE to mbuf. */
83 const uint8x16_t mcqe_shuf_m1 = {
84 -1, -1, -1, -1, /* skip packet_type */
85 7, 6, -1, -1, /* pkt_len, bswap16 */
86 7, 6, /* data_len, bswap16 */
87 -1, -1, /* skip vlan_tci */
88 3, 2, 1, 0 /* hash.rss, bswap32 */
90 const uint8x16_t mcqe_shuf_m2 = {
91 -1, -1, -1, -1, /* skip packet_type */
92 15, 14, -1, -1, /* pkt_len, bswap16 */
93 15, 14, /* data_len, bswap16 */
94 -1, -1, /* skip vlan_tci */
95 11, 10, 9, 8 /* hash.rss, bswap32 */
97 /* Restore the compressed count. Must be 16 bits. */
98 const uint16_t mcqe_n = t_pkt->data_len +
99 (rxq->crc_present * RTE_ETHER_CRC_LEN);
100 const uint64x2_t rearm =
101 vld1q_u64((void *)&t_pkt->rearm_data);
102 const uint32x4_t rxdf_mask = {
103 0xffffffff, /* packet_type */
104 0, /* skip pkt_len */
105 0xffff0000, /* vlan_tci, skip data_len */
106 0, /* skip hash.rss */
108 const uint8x16_t rxdf =
109 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1),
110 vreinterpretq_u8_u32(rxdf_mask));
111 const uint16x8_t crc_adj = {
113 rxq->crc_present * RTE_ETHER_CRC_LEN, 0,
114 rxq->crc_present * RTE_ETHER_CRC_LEN, 0,
117 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
118 #ifdef MLX5_PMD_SOFT_COUNTERS
119 uint32_t rcvd_byte = 0;
121 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
122 const uint8x8_t len_shuf_m = {
124 15, 14, /* 2nd mCQE */
125 23, 22, /* 3rd mCQE */
126 31, 30 /* 4th mCQE */
130 * A. load mCQEs into a 128bit register.
131 * B. store rearm data to mbuf.
132 * C. combine data from mCQEs with rx_descriptor_fields1.
133 * D. store rx_descriptor_fields1.
134 * E. store flow tag (rte_flow mark).
136 for (pos = 0; pos < mcqe_n; ) {
137 uint8_t *p = (void *)&mcq[pos % 8];
138 uint8_t *e0 = (void *)&elts[pos]->rearm_data;
139 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data;
140 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data;
141 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data;
143 #ifdef MLX5_PMD_SOFT_COUNTERS
144 uint16x4_t invalid_mask =
145 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
146 -1UL << ((mcqe_n - pos) *
147 sizeof(uint16_t) * 8) : 0);
150 if (!(pos & 0x7) && pos + 8 < mcqe_n)
151 rte_prefetch0((void *)(cq + pos + 8));
153 /* A.1 load mCQEs into a 128bit register. */
154 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t"
155 /* B.1 store rearm data to mbuf. */
156 "st1 {%[rearm].2d}, [%[e0]] \n\t"
157 "add %[e0], %[e0], #16 \n\t"
158 "st1 {%[rearm].2d}, [%[e1]] \n\t"
159 "add %[e1], %[e1], #16 \n\t"
160 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
161 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t"
162 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t"
163 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
164 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
165 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
166 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
167 /* D.1 store rx_descriptor_fields1. */
168 "st1 {v18.2d}, [%[e0]] \n\t"
169 "st1 {v19.2d}, [%[e1]] \n\t"
170 /* B.1 store rearm data to mbuf. */
171 "st1 {%[rearm].2d}, [%[e2]] \n\t"
172 "add %[e2], %[e2], #16 \n\t"
173 "st1 {%[rearm].2d}, [%[e3]] \n\t"
174 "add %[e3], %[e3], #16 \n\t"
175 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
176 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t"
177 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t"
178 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
179 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
180 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
181 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
182 /* D.1 store rx_descriptor_fields1. */
183 "st1 {v18.2d}, [%[e2]] \n\t"
184 "st1 {v19.2d}, [%[e3]] \n\t"
185 #ifdef MLX5_PMD_SOFT_COUNTERS
186 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t"
188 :[byte_cnt]"=&w"(byte_cnt)
192 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
193 [mcqe_shuf_m1]"w"(mcqe_shuf_m1),
194 [mcqe_shuf_m2]"w"(mcqe_shuf_m2),
195 [crc_adj]"w"(crc_adj),
196 [len_shuf_m]"w"(len_shuf_m)
197 :"memory", "v16", "v17", "v18", "v19");
198 #ifdef MLX5_PMD_SOFT_COUNTERS
199 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
200 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
203 /* E.1 store flow tag (rte_flow mark). */
204 elts[pos]->hash.fdir.hi = flow_tag;
205 elts[pos + 1]->hash.fdir.hi = flow_tag;
206 elts[pos + 2]->hash.fdir.hi = flow_tag;
207 elts[pos + 3]->hash.fdir.hi = flow_tag;
209 pos += MLX5_VPMD_DESCS_PER_LOOP;
210 /* Move to next CQE and invalidate consumed CQEs. */
211 if (!(pos & 0x7) && pos < mcqe_n) {
212 mcq = (void *)&(cq + pos)->pkt_info;
213 for (i = 0; i < 8; ++i)
214 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
217 /* Invalidate the rest of CQEs. */
218 for (; inv < mcqe_n; ++inv)
219 cq[inv].op_own = MLX5_CQE_INVALIDATE;
220 #ifdef MLX5_PMD_SOFT_COUNTERS
221 rxq->stats.ipackets += mcqe_n;
222 rxq->stats.ibytes += rcvd_byte;
224 rxq->cq_ci += mcqe_n;
229 * Calculate packet type and offload flag for mbuf and store it.
232 * Pointer to RX queue structure.
234 * Array of four 4bytes packet type info extracted from the original
235 * completion descriptor.
237 * Array of four 4bytes flow ID extracted from the original completion
240 * Opcode vector having responder error status. Each field is 4B.
242 * Pointer to array of packets to be filled.
245 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
246 uint32x4_t ptype_info, uint32x4_t flow_tag,
247 uint16x4_t op_err, struct rte_mbuf **pkts)
250 uint32x4_t pinfo, cv_flags;
251 uint32x4_t ol_flags =
252 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH |
253 rxq->hw_timestamp * PKT_RX_TIMESTAMP);
254 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
255 const uint8x16_t cv_flag_sel = {
257 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
258 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
260 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
262 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1),
263 0, 0, 0, 0, 0, 0, 0, 0, 0
265 const uint32x4_t cv_mask =
266 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
267 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
268 const uint64x2_t mbuf_init = vld1q_u64
269 ((const uint64_t *)&rxq->mbuf_initializer);
270 uint64x2_t rearm0, rearm1, rearm2, rearm3;
271 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3;
274 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT);
275 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR);
276 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID);
277 uint32x4_t invalid_mask;
279 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
280 invalid_mask = vceqzq_u32(flow_tag);
281 ol_flags = vorrq_u32(ol_flags,
282 vbicq_u32(fdir_flags, invalid_mask));
283 /* Mask out invalid entries. */
284 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask);
285 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
286 ol_flags = vorrq_u32(ol_flags,
287 vbicq_u32(fdir_id_flags,
288 vceqq_u32(flow_tag, ft_def)));
291 * ptype_info has the following:
295 * bit[11:10] = l3_hdr_type
296 * bit[14:12] = l4_hdr_type
299 * bit[17] = outer_l3_type
301 ptype = vshrn_n_u32(ptype_info, 10);
302 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
303 ptype = vorr_u16(ptype, op_err);
304 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6);
305 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4);
306 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2);
307 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0);
308 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] |
309 !!(pt_idx0 & (1 << 6)) * rxq->tunnel;
310 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] |
311 !!(pt_idx1 & (1 << 6)) * rxq->tunnel;
312 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] |
313 !!(pt_idx2 & (1 << 6)) * rxq->tunnel;
314 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] |
315 !!(pt_idx3 & (1 << 6)) * rxq->tunnel;
316 /* Fill flags for checksum and VLAN. */
317 pinfo = vandq_u32(ptype_info, ptype_ol_mask);
318 pinfo = vreinterpretq_u32_u8(
319 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo)));
320 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
321 cv_flags = vshlq_n_u32(pinfo, 9);
322 cv_flags = vorrq_u32(pinfo, cv_flags);
323 /* Move back flags to start from byte[0]. */
324 cv_flags = vshrq_n_u32(cv_flags, 8);
325 /* Mask out garbage bits. */
326 cv_flags = vandq_u32(cv_flags, cv_mask);
327 /* Merge to ol_flags. */
328 ol_flags = vorrq_u32(ol_flags, cv_flags);
329 /* Merge mbuf_init and ol_flags, and store. */
330 rearm0 = vreinterpretq_u64_u32(vsetq_lane_u32
331 (vgetq_lane_u32(ol_flags, 3),
332 vreinterpretq_u32_u64(mbuf_init), 2));
333 rearm1 = vreinterpretq_u64_u32(vsetq_lane_u32
334 (vgetq_lane_u32(ol_flags, 2),
335 vreinterpretq_u32_u64(mbuf_init), 2));
336 rearm2 = vreinterpretq_u64_u32(vsetq_lane_u32
337 (vgetq_lane_u32(ol_flags, 1),
338 vreinterpretq_u32_u64(mbuf_init), 2));
339 rearm3 = vreinterpretq_u64_u32(vsetq_lane_u32
340 (vgetq_lane_u32(ol_flags, 0),
341 vreinterpretq_u32_u64(mbuf_init), 2));
343 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0);
344 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1);
345 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2);
346 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3);
350 * Receive burst of packets. An errored completion also consumes a mbuf, but the
351 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
352 * before returning to application.
355 * Pointer to RX queue structure.
357 * Array to store received packets.
359 * Maximum number of packets in array.
361 * Pointer to a flag. Set non-zero value if pkts array has at least one error
365 * Number of packets received including errors (<= pkts_n).
367 static inline uint16_t
368 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
371 const uint16_t q_n = 1 << rxq->cqe_n;
372 const uint16_t q_mask = q_n - 1;
373 volatile struct mlx5_cqe *cq;
374 struct rte_mbuf **elts;
378 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
379 uint16_t nocmp_n = 0;
380 uint16_t rcvd_pkt = 0;
381 unsigned int cq_idx = rxq->cq_ci & q_mask;
382 unsigned int elts_idx;
383 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1)));
384 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001);
385 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0);
386 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c);
387 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0);
388 #ifdef MLX5_PMD_SOFT_COUNTERS
389 uint32_t rcvd_byte = 0;
391 /* Mask to generate 16B length vector. */
392 const uint8x8_t len_shuf_m = {
393 52, 53, /* 4th CQE */
394 36, 37, /* 3rd CQE */
395 20, 21, /* 2nd CQE */
398 /* Mask to extract 16B data from a 64B CQE. */
399 const uint8x16_t cqe_shuf_m = {
400 28, 29, /* hdr_type_etc */
403 47, 46, /* byte_cnt, bswap16 */
404 31, 30, /* vlan_info, bswap16 */
405 15, 14, 13, 12, /* rx_hash_res, bswap32 */
406 57, 58, 59, /* flow_tag */
409 /* Mask to generate 16B data for mbuf. */
410 const uint8x16_t mb_shuf_m = {
411 4, 5, -1, -1, /* pkt_len */
414 8, 9, 10, 11, /* hash.rss */
415 12, 13, 14, -1 /* hash.fdir.hi */
417 /* Mask to generate 16B owner vector. */
418 const uint8x8_t owner_shuf_m = {
419 63, -1, /* 4th CQE */
420 47, -1, /* 3rd CQE */
421 31, -1, /* 2nd CQE */
424 /* Mask to generate a vector having packet_type/ol_flags. */
425 const uint8x16_t ptype_shuf_m = {
426 48, 49, 50, -1, /* 4th CQE */
427 32, 33, 34, -1, /* 3rd CQE */
428 16, 17, 18, -1, /* 2nd CQE */
429 0, 1, 2, -1 /* 1st CQE */
431 /* Mask to generate a vector having flow tags. */
432 const uint8x16_t ftag_shuf_m = {
433 60, 61, 62, -1, /* 4th CQE */
434 44, 45, 46, -1, /* 3rd CQE */
435 28, 29, 30, -1, /* 2nd CQE */
436 12, 13, 14, -1 /* 1st CQE */
438 const uint16x8_t crc_adj = {
439 0, 0, rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 0, 0, 0, 0
441 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) };
443 assert(rxq->sges_n == 0);
444 assert(rxq->cqe_n == rxq->elts_n);
445 cq = &(*rxq->cqes)[cq_idx];
446 rte_prefetch_non_temporal(cq);
447 rte_prefetch_non_temporal(cq + 1);
448 rte_prefetch_non_temporal(cq + 2);
449 rte_prefetch_non_temporal(cq + 3);
450 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
451 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
452 if (repl_n >= rxq->rq_repl_thresh)
453 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
454 /* See if there're unreturned mbufs from compressed CQE. */
455 rcvd_pkt = rxq->decompressed;
457 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
458 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
459 rxq->rq_pi += rcvd_pkt;
461 rxq->decompressed -= rcvd_pkt;
463 elts_idx = rxq->rq_pi & q_mask;
464 elts = &(*rxq->elts)[elts_idx];
465 /* Not to overflow pkts array. */
466 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
467 /* Not to cross queue end. */
468 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
469 pkts_n = RTE_MIN(pkts_n, q_n - cq_idx);
472 /* At this point, there shouldn't be any remained packets. */
473 assert(rxq->decompressed == 0);
475 * Note that vectors have reverse order - {v3, v2, v1, v0}, because
476 * there's no instruction to count trailing zeros. __builtin_clzl() is
479 * A. copy 4 mbuf pointers from elts ring to returing pkts.
480 * B. load 64B CQE and extract necessary fields
481 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
482 * following structure:
484 * uint16_t hdr_type_etc;
488 * uint16_t vlan_info;
489 * uint32_t rx_has_res;
490 * uint8_t flow_tag[3];
495 * E. find compressed CQE.
499 pos += MLX5_VPMD_DESCS_PER_LOOP) {
501 uint16x4_t opcode, owner_mask, invalid_mask;
502 uint16x4_t comp_mask;
505 uint32x4_t ptype_info, flow_tag;
506 register uint64x2_t c0, c1, c2, c3;
507 uint8_t *p0, *p1, *p2, *p3;
508 uint8_t *e0 = (void *)&elts[pos]->pkt_len;
509 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len;
510 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len;
511 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len;
512 void *elts_p = (void *)&elts[pos];
513 void *pkts_p = (void *)&pkts[pos];
515 /* A.0 do not cross the end of CQ. */
516 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
517 -1UL >> ((pkts_n - pos) *
518 sizeof(uint16_t) * 8) : 0);
519 p0 = (void *)&cq[pos].pkt_info;
520 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe);
521 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe);
522 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe);
523 /* B.0 (CQE 3) load a block having op_own. */
524 c3 = vld1q_u64((uint64_t *)(p3 + 48));
525 /* B.0 (CQE 2) load a block having op_own. */
526 c2 = vld1q_u64((uint64_t *)(p2 + 48));
527 /* B.0 (CQE 1) load a block having op_own. */
528 c1 = vld1q_u64((uint64_t *)(p1 + 48));
529 /* B.0 (CQE 0) load a block having op_own. */
530 c0 = vld1q_u64((uint64_t *)(p0 + 48));
531 /* Synchronize for loading the rest of blocks. */
533 /* Prefetch next 4 CQEs. */
534 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
535 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP;
536 rte_prefetch_non_temporal(&cq[next]);
537 rte_prefetch_non_temporal(&cq[next + 1]);
538 rte_prefetch_non_temporal(&cq[next + 2]);
539 rte_prefetch_non_temporal(&cq[next + 3]);
542 /* B.1 (CQE 3) load the rest of blocks. */
543 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t"
544 /* B.2 (CQE 3) move the block having op_own. */
545 "mov v19.16b, %[c3].16b \n\t"
546 /* B.3 (CQE 3) extract 16B fields. */
547 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
548 /* B.1 (CQE 2) load the rest of blocks. */
549 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t"
550 /* B.4 (CQE 3) adjust CRC length. */
551 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t"
552 /* C.1 (CQE 3) generate final structure for mbuf. */
553 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t"
554 /* B.2 (CQE 2) move the block having op_own. */
555 "mov v19.16b, %[c2].16b \n\t"
556 /* B.3 (CQE 2) extract 16B fields. */
557 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
558 /* B.1 (CQE 1) load the rest of blocks. */
559 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t"
560 /* B.4 (CQE 2) adjust CRC length. */
561 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t"
562 /* C.1 (CQE 2) generate final structure for mbuf. */
563 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t"
564 /* B.2 (CQE 1) move the block having op_own. */
565 "mov v19.16b, %[c1].16b \n\t"
566 /* B.3 (CQE 1) extract 16B fields. */
567 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
568 /* B.1 (CQE 0) load the rest of blocks. */
569 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t"
570 /* B.4 (CQE 1) adjust CRC length. */
571 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t"
572 /* C.1 (CQE 1) generate final structure for mbuf. */
573 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t"
574 /* B.2 (CQE 0) move the block having op_own. */
575 "mov v19.16b, %[c0].16b \n\t"
576 /* A.1 load mbuf pointers. */
577 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t"
578 /* B.3 (CQE 0) extract 16B fields. */
579 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
580 /* B.4 (CQE 0) adjust CRC length. */
581 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t"
582 /* D.1 extract op_own byte. */
583 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t"
584 /* C.2 (CQE 3) adjust flow mark. */
585 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t"
586 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */
587 "st1 {v15.2d}, [%[e3]] \n\t"
588 /* C.2 (CQE 2) adjust flow mark. */
589 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t"
590 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */
591 "st1 {v14.2d}, [%[e2]] \n\t"
592 /* C.1 (CQE 0) generate final structure for mbuf. */
593 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t"
594 /* C.2 (CQE 1) adjust flow mark. */
595 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t"
596 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
597 "st1 {v13.2d}, [%[e1]] \n\t"
598 #ifdef MLX5_PMD_SOFT_COUNTERS
599 /* Extract byte_cnt. */
600 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t"
602 /* Extract ptype_info. */
603 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t"
604 /* Extract flow_tag. */
605 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t"
606 /* A.2 copy mbuf pointers. */
607 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t"
608 /* C.2 (CQE 0) adjust flow mark. */
609 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t"
610 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
611 "st1 {v12.2d}, [%[e0]] \n\t"
612 :[op_own]"=&w"(op_own),
613 [byte_cnt]"=&w"(byte_cnt),
614 [ptype_info]"=&w"(ptype_info),
615 [flow_tag]"=&w"(flow_tag)
616 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0),
617 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
618 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0),
621 [cqe_shuf_m]"w"(cqe_shuf_m),
622 [mb_shuf_m]"w"(mb_shuf_m),
623 [owner_shuf_m]"w"(owner_shuf_m),
624 [len_shuf_m]"w"(len_shuf_m),
625 [ptype_shuf_m]"w"(ptype_shuf_m),
626 [ftag_shuf_m]"w"(ftag_shuf_m),
627 [crc_adj]"w"(crc_adj),
628 [flow_mark_adj]"w"(flow_mark_adj)
630 "v12", "v13", "v14", "v15",
631 "v16", "v17", "v18", "v19",
632 "v20", "v21", "v22", "v23",
634 /* D.2 flip owner bit to mark CQEs from last round. */
635 owner_mask = vand_u16(op_own, owner_check);
636 owner_mask = vceq_u16(owner_mask, ownership);
637 /* D.3 get mask for invalidated CQEs. */
638 opcode = vand_u16(op_own, opcode_check);
639 invalid_mask = vceq_u16(opcode_check, opcode);
640 /* E.1 find compressed CQE format. */
641 comp_mask = vand_u16(op_own, format_check);
642 comp_mask = vceq_u16(comp_mask, format_check);
643 /* D.4 mask out beyond boundary. */
644 invalid_mask = vorr_u16(invalid_mask, mask);
645 /* D.5 merge invalid_mask with invalid owner. */
646 invalid_mask = vorr_u16(invalid_mask, owner_mask);
647 /* E.2 mask out invalid entries. */
648 comp_mask = vbic_u16(comp_mask, invalid_mask);
649 /* E.3 get the first compressed CQE. */
650 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
652 (sizeof(uint16_t) * 8);
653 /* D.6 mask out entries after the compressed CQE. */
654 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ?
655 -1UL >> (comp_idx * sizeof(uint16_t) * 8) :
657 invalid_mask = vorr_u16(invalid_mask, mask);
658 /* D.7 count non-compressed valid CQEs. */
659 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
660 invalid_mask), 0)) / (sizeof(uint16_t) * 8);
662 /* D.2 get the final invalid mask. */
663 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ?
664 -1UL >> (n * sizeof(uint16_t) * 8) : 0);
665 invalid_mask = vorr_u16(invalid_mask, mask);
666 /* D.3 check error in opcode. */
667 opcode = vceq_u16(resp_err_check, opcode);
668 opcode = vbic_u16(opcode, invalid_mask);
669 /* D.4 mark if any error is set */
670 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0);
671 /* C.4 fill in mbuf - rearm_data and packet_type. */
672 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,
674 if (rxq->hw_timestamp) {
675 elts[pos]->timestamp =
677 container_of(p0, struct mlx5_cqe,
678 pkt_info)->timestamp);
679 elts[pos + 1]->timestamp =
681 container_of(p1, struct mlx5_cqe,
682 pkt_info)->timestamp);
683 elts[pos + 2]->timestamp =
685 container_of(p2, struct mlx5_cqe,
686 pkt_info)->timestamp);
687 elts[pos + 3]->timestamp =
689 container_of(p3, struct mlx5_cqe,
690 pkt_info)->timestamp);
692 if (rte_flow_dynf_metadata_avail()) {
693 /* This code is subject for futher optimization. */
694 *RTE_FLOW_DYNF_METADATA(elts[pos]) =
695 container_of(p0, struct mlx5_cqe,
696 pkt_info)->flow_table_metadata;
697 *RTE_FLOW_DYNF_METADATA(elts[pos + 1]) =
698 container_of(p1, struct mlx5_cqe,
699 pkt_info)->flow_table_metadata;
700 *RTE_FLOW_DYNF_METADATA(elts[pos + 2]) =
701 container_of(p2, struct mlx5_cqe,
702 pkt_info)->flow_table_metadata;
703 *RTE_FLOW_DYNF_METADATA(elts[pos + 3]) =
704 container_of(p3, struct mlx5_cqe,
705 pkt_info)->flow_table_metadata;
706 if (*RTE_FLOW_DYNF_METADATA(elts[pos]))
707 elts[pos]->ol_flags |= PKT_RX_DYNF_METADATA;
708 if (*RTE_FLOW_DYNF_METADATA(elts[pos + 1]))
709 elts[pos + 1]->ol_flags |= PKT_RX_DYNF_METADATA;
710 if (*RTE_FLOW_DYNF_METADATA(elts[pos + 2]))
711 elts[pos + 2]->ol_flags |= PKT_RX_DYNF_METADATA;
712 if (*RTE_FLOW_DYNF_METADATA(elts[pos + 3]))
713 elts[pos + 3]->ol_flags |= PKT_RX_DYNF_METADATA;
715 #ifdef MLX5_PMD_SOFT_COUNTERS
716 /* Add up received bytes count. */
717 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
718 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
721 * Break the loop unless more valid CQE is expected, or if
722 * there's a compressed CQE.
724 if (n != MLX5_VPMD_DESCS_PER_LOOP)
727 /* If no new CQE seen, return without updating cq_db. */
728 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
730 /* Update the consumer indexes for non-compressed CQEs. */
731 assert(nocmp_n <= pkts_n);
732 rxq->cq_ci += nocmp_n;
733 rxq->rq_pi += nocmp_n;
735 #ifdef MLX5_PMD_SOFT_COUNTERS
736 rxq->stats.ipackets += nocmp_n;
737 rxq->stats.ibytes += rcvd_byte;
739 /* Decompress the last CQE if compressed. */
740 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
741 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
742 rxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n],
744 /* Return more packets if needed. */
745 if (nocmp_n < pkts_n) {
746 uint16_t n = rxq->decompressed;
748 n = RTE_MIN(n, pkts_n - nocmp_n);
749 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
752 rxq->decompressed -= n;
756 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
760 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */