1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_
7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_
16 #include <rte_mempool.h>
17 #include <rte_prefetch.h>
20 #include "mlx5_utils.h"
21 #include "mlx5_rxtx.h"
22 #include "mlx5_rxtx_vec.h"
23 #include "mlx5_autoconf.h"
24 #include "mlx5_defs.h"
27 #pragma GCC diagnostic ignored "-Wcast-qual"
30 * Fill in buffer descriptors in a multi-packet send descriptor.
33 * Pointer to TX queue structure.
35 * Pointer to buffer descriptor to be written.
37 * Pointer to array of packets to be sent.
39 * Number of packets to be filled.
42 txq_wr_dseg_v(struct mlx5_txq_data *txq, uint8_t *dseg,
43 struct rte_mbuf **pkts, unsigned int n)
47 const uint8x16_t dseg_shuf_m = {
48 3, 2, 1, 0, /* length, bswap32 */
49 4, 5, 6, 7, /* lkey */
50 15, 14, 13, 12, /* addr, bswap64 */
53 #ifdef MLX5_PMD_SOFT_COUNTERS
57 for (pos = 0; pos < n; ++pos, dseg += MLX5_WQE_DWORD_SIZE) {
59 struct rte_mbuf *pkt = pkts[pos];
61 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
62 desc = vreinterpretq_u8_u32((uint32x4_t) {
64 mlx5_tx_mb2mr(txq, pkt),
67 desc = vqtbl1q_u8(desc, dseg_shuf_m);
69 #ifdef MLX5_PMD_SOFT_COUNTERS
70 tx_byte += DATA_LEN(pkt);
73 #ifdef MLX5_PMD_SOFT_COUNTERS
74 txq->stats.obytes += tx_byte;
79 * Send multi-segmented packets until it encounters a single segment packet in
83 * Pointer to TX queue structure.
85 * Pointer to array of packets to be sent.
87 * Number of packets to be sent.
90 * Number of packets successfully transmitted (<= pkts_n).
93 txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
96 uint16_t elts_head = txq->elts_head;
97 const uint16_t elts_n = 1 << txq->elts_n;
98 const uint16_t elts_m = elts_n - 1;
99 const uint16_t wq_n = 1 << txq->wqe_n;
100 const uint16_t wq_mask = wq_n - 1;
101 const unsigned int nb_dword_per_wqebb =
102 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
103 const unsigned int nb_dword_in_hdr =
104 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
106 volatile struct mlx5_wqe *wqe = NULL;
108 txq->offloads & DEV_TX_OFFLOAD_MATCH_METADATA ? true : false;
110 assert(elts_n > pkts_n);
111 mlx5_tx_complete(txq);
112 if (unlikely(!pkts_n))
114 for (n = 0; n < pkts_n; ++n) {
115 struct rte_mbuf *buf = pkts[n];
116 unsigned int segs_n = buf->nb_segs;
117 unsigned int ds = nb_dword_in_hdr;
118 unsigned int len = PKT_LEN(buf);
119 uint16_t wqe_ci = txq->wqe_ci;
120 const uint8x16_t ctrl_shuf_m = {
121 3, 2, 1, 0, /* bswap32 */
122 7, 6, 5, 4, /* bswap32 */
123 11, 10, 9, 8, /* bswap32 */
132 rte_be32_t metadata =
133 metadata_ol && (buf->ol_flags & PKT_TX_METADATA) ?
134 buf->tx_metadata : 0;
137 max_elts = elts_n - (elts_head - txq->elts_tail);
138 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
140 * A MPW session consumes 2 WQEs at most to
141 * include MLX5_MPW_DSEG_MAX pointers.
144 max_elts < segs_n || max_wqe < 2)
146 wqe = &((volatile struct mlx5_wqe64 *)
147 txq->wqes)[wqe_ci & wq_mask].hdr;
148 cs_flags = txq_ol_cksum_to_cs(buf);
149 /* Title WQEBB pointer. */
150 t_wqe = (uint8x16_t *)wqe;
151 dseg = (uint8_t *)(wqe + 1);
153 if (!(ds++ % nb_dword_per_wqebb)) {
155 &((volatile struct mlx5_wqe64 *)
156 txq->wqes)[++wqe_ci & wq_mask];
158 txq_wr_dseg_v(txq, dseg, &buf, 1);
159 dseg += MLX5_WQE_DWORD_SIZE;
160 (*txq->elts)[elts_head++ & elts_m] = buf;
164 /* Fill CTRL in the header. */
165 ctrl = vreinterpretq_u8_u32((uint32x4_t) {
166 MLX5_OPC_MOD_MPW << 24 |
167 txq->wqe_ci << 8 | MLX5_OPCODE_TSO,
168 txq->qp_num_8s | ds, 0, 0});
169 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m);
170 vst1q_u8((void *)t_wqe, ctrl);
171 /* Fill ESEG in the header. */
172 vst1q_u32((void *)(t_wqe + 1),
174 rte_cpu_to_be_16(len) << 16 | cs_flags,
176 txq->wqe_ci = wqe_ci;
180 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
181 txq->elts_head = elts_head;
182 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
183 /* A CQE slot must always be available. */
184 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
185 wqe->ctrl[2] = rte_cpu_to_be_32(8);
186 wqe->ctrl[3] = txq->elts_head;
189 #ifdef MLX5_PMD_SOFT_COUNTERS
190 txq->stats.opackets += n;
192 mlx5_tx_dbrec(txq, wqe);
197 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
198 * it returns to make it processed by txq_scatter_v(). All the packets in
199 * the pkts list should be single segment packets having same offload flags.
200 * This must be checked by txq_count_contig_single_seg() and txq_calc_offload().
203 * Pointer to TX queue structure.
205 * Pointer to array of packets to be sent.
207 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
209 * Checksum offload flags to be written in the descriptor.
211 * Metadata value to be written in the descriptor.
214 * Number of packets successfully transmitted (<= pkts_n).
216 static inline uint16_t
217 txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
218 uint8_t cs_flags, rte_be32_t metadata)
220 struct rte_mbuf **elts;
221 uint16_t elts_head = txq->elts_head;
222 const uint16_t elts_n = 1 << txq->elts_n;
223 const uint16_t elts_m = elts_n - 1;
224 const unsigned int nb_dword_per_wqebb =
225 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
226 const unsigned int nb_dword_in_hdr =
227 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
232 uint32_t comp_req = 0;
233 const uint16_t wq_n = 1 << txq->wqe_n;
234 const uint16_t wq_mask = wq_n - 1;
235 uint16_t wq_idx = txq->wqe_ci & wq_mask;
236 volatile struct mlx5_wqe64 *wq =
237 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
238 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
239 const uint8x16_t ctrl_shuf_m = {
240 3, 2, 1, 0, /* bswap32 */
241 7, 6, 5, 4, /* bswap32 */
242 11, 10, 9, 8, /* bswap32 */
249 /* Make sure all packets can fit into a single WQE. */
250 assert(elts_n > pkts_n);
251 mlx5_tx_complete(txq);
252 max_elts = (elts_n - (elts_head - txq->elts_tail));
253 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
254 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
255 if (unlikely(!pkts_n))
257 elts = &(*txq->elts)[elts_head & elts_m];
258 /* Loop for available tailroom first. */
259 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
260 for (pos = 0; pos < (n & -2); pos += 2)
261 vst1q_u64((void *)&elts[pos], vld1q_u64((void *)&pkts[pos]));
263 elts[pos] = pkts[pos];
264 /* Check if it crosses the end of the queue. */
265 if (unlikely(n < pkts_n)) {
266 elts = &(*txq->elts)[0];
267 for (pos = 0; pos < pkts_n - n; ++pos)
268 elts[pos] = pkts[n + pos];
270 txq->elts_head += pkts_n;
271 /* Save title WQEBB pointer. */
272 t_wqe = (uint8x16_t *)wqe;
273 dseg = (uint8_t *)(wqe + 1);
274 /* Calculate the number of entries to the end. */
276 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
279 txq_wr_dseg_v(txq, dseg, pkts, n);
280 /* Check if it crosses the end of the queue. */
282 dseg = (uint8_t *)txq->wqes;
283 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
285 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
286 txq->elts_comp += pkts_n;
288 /* A CQE slot must always be available. */
289 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
290 /* Request a completion. */
294 /* Fill CTRL in the header. */
295 ctrl = vreinterpretq_u8_u32((uint32x4_t) {
296 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
297 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW,
298 txq->qp_num_8s | (pkts_n + 2),
301 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m);
302 vst1q_u8((void *)t_wqe, ctrl);
303 /* Fill ESEG in the header. */
304 vst1q_u32((void *)(t_wqe + 1),
305 ((uint32x4_t) { 0, cs_flags, metadata, 0 }));
306 #ifdef MLX5_PMD_SOFT_COUNTERS
307 txq->stats.opackets += pkts_n;
309 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
311 /* Ring QP doorbell. */
312 mlx5_tx_dbrec_cond_wmb(txq, wqe, pkts_n < MLX5_VPMD_TX_MAX_BURST);
317 * Store free buffers to RX SW ring.
320 * Pointer to RX queue structure.
322 * Pointer to array of packets to be stored.
324 * Number of packets to be stored.
327 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
329 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
330 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
334 for (pos = 0; pos < p; pos += 2) {
337 mbp = vld1q_u64((void *)&elts[pos]);
338 vst1q_u64((void *)&pkts[pos], mbp);
341 pkts[pos] = elts[pos];
345 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
346 * extracted from the title completion descriptor.
349 * Pointer to RX queue structure.
351 * Pointer to completion array having a compressed completion at first.
353 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
354 * the title completion descriptor to be copied to the rest of mbufs.
357 * Number of mini-CQEs successfully decompressed.
359 static inline uint16_t
360 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
361 struct rte_mbuf **elts)
363 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info;
364 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
367 unsigned int inv = 0;
368 /* Mask to shuffle from extracted mini CQE to mbuf. */
369 const uint8x16_t mcqe_shuf_m1 = {
370 -1, -1, -1, -1, /* skip packet_type */
371 7, 6, -1, -1, /* pkt_len, bswap16 */
372 7, 6, /* data_len, bswap16 */
373 -1, -1, /* skip vlan_tci */
374 3, 2, 1, 0 /* hash.rss, bswap32 */
376 const uint8x16_t mcqe_shuf_m2 = {
377 -1, -1, -1, -1, /* skip packet_type */
378 15, 14, -1, -1, /* pkt_len, bswap16 */
379 15, 14, /* data_len, bswap16 */
380 -1, -1, /* skip vlan_tci */
381 11, 10, 9, 8 /* hash.rss, bswap32 */
383 /* Restore the compressed count. Must be 16 bits. */
384 const uint16_t mcqe_n = t_pkt->data_len +
385 (rxq->crc_present * RTE_ETHER_CRC_LEN);
386 const uint64x2_t rearm =
387 vld1q_u64((void *)&t_pkt->rearm_data);
388 const uint32x4_t rxdf_mask = {
389 0xffffffff, /* packet_type */
390 0, /* skip pkt_len */
391 0xffff0000, /* vlan_tci, skip data_len */
392 0, /* skip hash.rss */
394 const uint8x16_t rxdf =
395 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1),
396 vreinterpretq_u8_u32(rxdf_mask));
397 const uint16x8_t crc_adj = {
399 rxq->crc_present * RTE_ETHER_CRC_LEN, 0,
400 rxq->crc_present * RTE_ETHER_CRC_LEN, 0,
403 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
404 #ifdef MLX5_PMD_SOFT_COUNTERS
405 uint32_t rcvd_byte = 0;
407 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
408 const uint8x8_t len_shuf_m = {
410 15, 14, /* 2nd mCQE */
411 23, 22, /* 3rd mCQE */
412 31, 30 /* 4th mCQE */
416 * A. load mCQEs into a 128bit register.
417 * B. store rearm data to mbuf.
418 * C. combine data from mCQEs with rx_descriptor_fields1.
419 * D. store rx_descriptor_fields1.
420 * E. store flow tag (rte_flow mark).
422 for (pos = 0; pos < mcqe_n; ) {
423 uint8_t *p = (void *)&mcq[pos % 8];
424 uint8_t *e0 = (void *)&elts[pos]->rearm_data;
425 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data;
426 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data;
427 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data;
429 #ifdef MLX5_PMD_SOFT_COUNTERS
430 uint16x4_t invalid_mask =
431 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
432 -1UL << ((mcqe_n - pos) *
433 sizeof(uint16_t) * 8) : 0);
436 if (!(pos & 0x7) && pos + 8 < mcqe_n)
437 rte_prefetch0((void *)(cq + pos + 8));
439 /* A.1 load mCQEs into a 128bit register. */
440 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t"
441 /* B.1 store rearm data to mbuf. */
442 "st1 {%[rearm].2d}, [%[e0]] \n\t"
443 "add %[e0], %[e0], #16 \n\t"
444 "st1 {%[rearm].2d}, [%[e1]] \n\t"
445 "add %[e1], %[e1], #16 \n\t"
446 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
447 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t"
448 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t"
449 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
450 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
451 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
452 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
453 /* D.1 store rx_descriptor_fields1. */
454 "st1 {v18.2d}, [%[e0]] \n\t"
455 "st1 {v19.2d}, [%[e1]] \n\t"
456 /* B.1 store rearm data to mbuf. */
457 "st1 {%[rearm].2d}, [%[e2]] \n\t"
458 "add %[e2], %[e2], #16 \n\t"
459 "st1 {%[rearm].2d}, [%[e3]] \n\t"
460 "add %[e3], %[e3], #16 \n\t"
461 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
462 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t"
463 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t"
464 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
465 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
466 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
467 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
468 /* D.1 store rx_descriptor_fields1. */
469 "st1 {v18.2d}, [%[e2]] \n\t"
470 "st1 {v19.2d}, [%[e3]] \n\t"
471 #ifdef MLX5_PMD_SOFT_COUNTERS
472 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t"
474 :[byte_cnt]"=&w"(byte_cnt)
478 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
479 [mcqe_shuf_m1]"w"(mcqe_shuf_m1),
480 [mcqe_shuf_m2]"w"(mcqe_shuf_m2),
481 [crc_adj]"w"(crc_adj),
482 [len_shuf_m]"w"(len_shuf_m)
483 :"memory", "v16", "v17", "v18", "v19");
484 #ifdef MLX5_PMD_SOFT_COUNTERS
485 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
486 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
489 /* E.1 store flow tag (rte_flow mark). */
490 elts[pos]->hash.fdir.hi = flow_tag;
491 elts[pos + 1]->hash.fdir.hi = flow_tag;
492 elts[pos + 2]->hash.fdir.hi = flow_tag;
493 elts[pos + 3]->hash.fdir.hi = flow_tag;
495 pos += MLX5_VPMD_DESCS_PER_LOOP;
496 /* Move to next CQE and invalidate consumed CQEs. */
497 if (!(pos & 0x7) && pos < mcqe_n) {
498 mcq = (void *)&(cq + pos)->pkt_info;
499 for (i = 0; i < 8; ++i)
500 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
503 /* Invalidate the rest of CQEs. */
504 for (; inv < mcqe_n; ++inv)
505 cq[inv].op_own = MLX5_CQE_INVALIDATE;
506 #ifdef MLX5_PMD_SOFT_COUNTERS
507 rxq->stats.ipackets += mcqe_n;
508 rxq->stats.ibytes += rcvd_byte;
510 rxq->cq_ci += mcqe_n;
515 * Calculate packet type and offload flag for mbuf and store it.
518 * Pointer to RX queue structure.
520 * Array of four 4bytes packet type info extracted from the original
521 * completion descriptor.
523 * Array of four 4bytes flow ID extracted from the original completion
526 * Opcode vector having responder error status. Each field is 4B.
528 * Pointer to array of packets to be filled.
531 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
532 uint32x4_t ptype_info, uint32x4_t flow_tag,
533 uint16x4_t op_err, struct rte_mbuf **pkts)
536 uint32x4_t pinfo, cv_flags;
537 uint32x4_t ol_flags =
538 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH |
539 rxq->hw_timestamp * PKT_RX_TIMESTAMP);
540 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
541 const uint8x16_t cv_flag_sel = {
543 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
544 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
546 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
548 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1),
549 0, 0, 0, 0, 0, 0, 0, 0, 0
551 const uint32x4_t cv_mask =
552 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
553 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
554 const uint64x1_t mbuf_init = vld1_u64(&rxq->mbuf_initializer);
555 const uint64x1_t r32_mask = vcreate_u64(0xffffffff);
556 uint64x2_t rearm0, rearm1, rearm2, rearm3;
557 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3;
560 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT);
561 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR);
562 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID);
563 uint32x4_t invalid_mask;
565 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
566 invalid_mask = vceqzq_u32(flow_tag);
567 ol_flags = vorrq_u32(ol_flags,
568 vbicq_u32(fdir_flags, invalid_mask));
569 /* Mask out invalid entries. */
570 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask);
571 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
572 ol_flags = vorrq_u32(ol_flags,
573 vbicq_u32(fdir_id_flags,
574 vceqq_u32(flow_tag, ft_def)));
577 * ptype_info has the following:
581 * bit[11:10] = l3_hdr_type
582 * bit[14:12] = l4_hdr_type
585 * bit[17] = outer_l3_type
587 ptype = vshrn_n_u32(ptype_info, 10);
588 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
589 ptype = vorr_u16(ptype, op_err);
590 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6);
591 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4);
592 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2);
593 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0);
594 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] |
595 !!(pt_idx0 & (1 << 6)) * rxq->tunnel;
596 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] |
597 !!(pt_idx1 & (1 << 6)) * rxq->tunnel;
598 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] |
599 !!(pt_idx2 & (1 << 6)) * rxq->tunnel;
600 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] |
601 !!(pt_idx3 & (1 << 6)) * rxq->tunnel;
602 /* Fill flags for checksum and VLAN. */
603 pinfo = vandq_u32(ptype_info, ptype_ol_mask);
604 pinfo = vreinterpretq_u32_u8(
605 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo)));
606 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
607 cv_flags = vshlq_n_u32(pinfo, 9);
608 cv_flags = vorrq_u32(pinfo, cv_flags);
609 /* Move back flags to start from byte[0]. */
610 cv_flags = vshrq_n_u32(cv_flags, 8);
611 /* Mask out garbage bits. */
612 cv_flags = vandq_u32(cv_flags, cv_mask);
613 /* Merge to ol_flags. */
614 ol_flags = vorrq_u32(ol_flags, cv_flags);
615 /* Merge mbuf_init and ol_flags, and store. */
616 rearm0 = vcombine_u64(mbuf_init,
617 vshr_n_u64(vget_high_u64(vreinterpretq_u64_u32(
619 rearm1 = vcombine_u64(mbuf_init,
620 vand_u64(vget_high_u64(vreinterpretq_u64_u32(
621 ol_flags)), r32_mask));
622 rearm2 = vcombine_u64(mbuf_init,
623 vshr_n_u64(vget_low_u64(vreinterpretq_u64_u32(
625 rearm3 = vcombine_u64(mbuf_init,
626 vand_u64(vget_low_u64(vreinterpretq_u64_u32(
627 ol_flags)), r32_mask));
628 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0);
629 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1);
630 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2);
631 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3);
635 * Receive burst of packets. An errored completion also consumes a mbuf, but the
636 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
637 * before returning to application.
640 * Pointer to RX queue structure.
642 * Array to store received packets.
644 * Maximum number of packets in array.
646 * Pointer to a flag. Set non-zero value if pkts array has at least one error
650 * Number of packets received including errors (<= pkts_n).
652 static inline uint16_t
653 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
656 const uint16_t q_n = 1 << rxq->cqe_n;
657 const uint16_t q_mask = q_n - 1;
658 volatile struct mlx5_cqe *cq;
659 struct rte_mbuf **elts;
663 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
664 uint16_t nocmp_n = 0;
665 uint16_t rcvd_pkt = 0;
666 unsigned int cq_idx = rxq->cq_ci & q_mask;
667 unsigned int elts_idx;
668 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1)));
669 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001);
670 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0);
671 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c);
672 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0);
673 #ifdef MLX5_PMD_SOFT_COUNTERS
674 uint32_t rcvd_byte = 0;
676 /* Mask to generate 16B length vector. */
677 const uint8x8_t len_shuf_m = {
678 52, 53, /* 4th CQE */
679 36, 37, /* 3rd CQE */
680 20, 21, /* 2nd CQE */
683 /* Mask to extract 16B data from a 64B CQE. */
684 const uint8x16_t cqe_shuf_m = {
685 28, 29, /* hdr_type_etc */
688 47, 46, /* byte_cnt, bswap16 */
689 31, 30, /* vlan_info, bswap16 */
690 15, 14, 13, 12, /* rx_hash_res, bswap32 */
691 57, 58, 59, /* flow_tag */
694 /* Mask to generate 16B data for mbuf. */
695 const uint8x16_t mb_shuf_m = {
696 4, 5, -1, -1, /* pkt_len */
699 8, 9, 10, 11, /* hash.rss */
700 12, 13, 14, -1 /* hash.fdir.hi */
702 /* Mask to generate 16B owner vector. */
703 const uint8x8_t owner_shuf_m = {
704 63, -1, /* 4th CQE */
705 47, -1, /* 3rd CQE */
706 31, -1, /* 2nd CQE */
709 /* Mask to generate a vector having packet_type/ol_flags. */
710 const uint8x16_t ptype_shuf_m = {
711 48, 49, 50, -1, /* 4th CQE */
712 32, 33, 34, -1, /* 3rd CQE */
713 16, 17, 18, -1, /* 2nd CQE */
714 0, 1, 2, -1 /* 1st CQE */
716 /* Mask to generate a vector having flow tags. */
717 const uint8x16_t ftag_shuf_m = {
718 60, 61, 62, -1, /* 4th CQE */
719 44, 45, 46, -1, /* 3rd CQE */
720 28, 29, 30, -1, /* 2nd CQE */
721 12, 13, 14, -1 /* 1st CQE */
723 const uint16x8_t crc_adj = {
724 0, 0, rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 0, 0, 0, 0
726 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) };
728 assert(rxq->sges_n == 0);
729 assert(rxq->cqe_n == rxq->elts_n);
730 cq = &(*rxq->cqes)[cq_idx];
731 rte_prefetch_non_temporal(cq);
732 rte_prefetch_non_temporal(cq + 1);
733 rte_prefetch_non_temporal(cq + 2);
734 rte_prefetch_non_temporal(cq + 3);
735 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
736 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
737 if (repl_n >= rxq->rq_repl_thresh)
738 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
739 /* See if there're unreturned mbufs from compressed CQE. */
740 rcvd_pkt = rxq->decompressed;
742 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
743 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
744 rxq->rq_pi += rcvd_pkt;
746 rxq->decompressed -= rcvd_pkt;
748 elts_idx = rxq->rq_pi & q_mask;
749 elts = &(*rxq->elts)[elts_idx];
750 /* Not to overflow pkts array. */
751 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
752 /* Not to cross queue end. */
753 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
754 pkts_n = RTE_MIN(pkts_n, q_n - cq_idx);
757 /* At this point, there shouldn't be any remained packets. */
758 assert(rxq->decompressed == 0);
760 * Note that vectors have reverse order - {v3, v2, v1, v0}, because
761 * there's no instruction to count trailing zeros. __builtin_clzl() is
764 * A. copy 4 mbuf pointers from elts ring to returing pkts.
765 * B. load 64B CQE and extract necessary fields
766 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
767 * following structure:
769 * uint16_t hdr_type_etc;
773 * uint16_t vlan_info;
774 * uint32_t rx_has_res;
775 * uint8_t flow_tag[3];
780 * E. find compressed CQE.
784 pos += MLX5_VPMD_DESCS_PER_LOOP) {
786 uint16x4_t opcode, owner_mask, invalid_mask;
787 uint16x4_t comp_mask;
790 uint32x4_t ptype_info, flow_tag;
791 register uint64x2_t c0, c1, c2, c3;
792 uint8_t *p0, *p1, *p2, *p3;
793 uint8_t *e0 = (void *)&elts[pos]->pkt_len;
794 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len;
795 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len;
796 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len;
797 void *elts_p = (void *)&elts[pos];
798 void *pkts_p = (void *)&pkts[pos];
800 /* A.0 do not cross the end of CQ. */
801 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
802 -1UL >> ((pkts_n - pos) *
803 sizeof(uint16_t) * 8) : 0);
804 p0 = (void *)&cq[pos].pkt_info;
805 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe);
806 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe);
807 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe);
808 /* B.0 (CQE 3) load a block having op_own. */
809 c3 = vld1q_u64((uint64_t *)(p3 + 48));
810 /* B.0 (CQE 2) load a block having op_own. */
811 c2 = vld1q_u64((uint64_t *)(p2 + 48));
812 /* B.0 (CQE 1) load a block having op_own. */
813 c1 = vld1q_u64((uint64_t *)(p1 + 48));
814 /* B.0 (CQE 0) load a block having op_own. */
815 c0 = vld1q_u64((uint64_t *)(p0 + 48));
816 /* Synchronize for loading the rest of blocks. */
818 /* Prefetch next 4 CQEs. */
819 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
820 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP;
821 rte_prefetch_non_temporal(&cq[next]);
822 rte_prefetch_non_temporal(&cq[next + 1]);
823 rte_prefetch_non_temporal(&cq[next + 2]);
824 rte_prefetch_non_temporal(&cq[next + 3]);
827 /* B.1 (CQE 3) load the rest of blocks. */
828 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t"
829 /* B.2 (CQE 3) move the block having op_own. */
830 "mov v19.16b, %[c3].16b \n\t"
831 /* B.3 (CQE 3) extract 16B fields. */
832 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
833 /* B.1 (CQE 2) load the rest of blocks. */
834 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t"
835 /* B.4 (CQE 3) adjust CRC length. */
836 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t"
837 /* C.1 (CQE 3) generate final structure for mbuf. */
838 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t"
839 /* B.2 (CQE 2) move the block having op_own. */
840 "mov v19.16b, %[c2].16b \n\t"
841 /* B.3 (CQE 2) extract 16B fields. */
842 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
843 /* B.1 (CQE 1) load the rest of blocks. */
844 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t"
845 /* B.4 (CQE 2) adjust CRC length. */
846 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t"
847 /* C.1 (CQE 2) generate final structure for mbuf. */
848 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t"
849 /* B.2 (CQE 1) move the block having op_own. */
850 "mov v19.16b, %[c1].16b \n\t"
851 /* B.3 (CQE 1) extract 16B fields. */
852 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
853 /* B.1 (CQE 0) load the rest of blocks. */
854 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t"
855 /* B.4 (CQE 1) adjust CRC length. */
856 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t"
857 /* C.1 (CQE 1) generate final structure for mbuf. */
858 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t"
859 /* B.2 (CQE 0) move the block having op_own. */
860 "mov v19.16b, %[c0].16b \n\t"
861 /* A.1 load mbuf pointers. */
862 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t"
863 /* B.3 (CQE 0) extract 16B fields. */
864 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
865 /* B.4 (CQE 0) adjust CRC length. */
866 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t"
867 /* D.1 extract op_own byte. */
868 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t"
869 /* C.2 (CQE 3) adjust flow mark. */
870 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t"
871 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */
872 "st1 {v15.2d}, [%[e3]] \n\t"
873 /* C.2 (CQE 2) adjust flow mark. */
874 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t"
875 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */
876 "st1 {v14.2d}, [%[e2]] \n\t"
877 /* C.1 (CQE 0) generate final structure for mbuf. */
878 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t"
879 /* C.2 (CQE 1) adjust flow mark. */
880 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t"
881 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
882 "st1 {v13.2d}, [%[e1]] \n\t"
883 #ifdef MLX5_PMD_SOFT_COUNTERS
884 /* Extract byte_cnt. */
885 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t"
887 /* Extract ptype_info. */
888 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t"
889 /* Extract flow_tag. */
890 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t"
891 /* A.2 copy mbuf pointers. */
892 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t"
893 /* C.2 (CQE 0) adjust flow mark. */
894 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t"
895 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
896 "st1 {v12.2d}, [%[e0]] \n\t"
897 :[op_own]"=&w"(op_own),
898 [byte_cnt]"=&w"(byte_cnt),
899 [ptype_info]"=&w"(ptype_info),
900 [flow_tag]"=&w"(flow_tag)
901 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0),
902 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
903 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0),
906 [cqe_shuf_m]"w"(cqe_shuf_m),
907 [mb_shuf_m]"w"(mb_shuf_m),
908 [owner_shuf_m]"w"(owner_shuf_m),
909 [len_shuf_m]"w"(len_shuf_m),
910 [ptype_shuf_m]"w"(ptype_shuf_m),
911 [ftag_shuf_m]"w"(ftag_shuf_m),
912 [crc_adj]"w"(crc_adj),
913 [flow_mark_adj]"w"(flow_mark_adj)
915 "v12", "v13", "v14", "v15",
916 "v16", "v17", "v18", "v19",
917 "v20", "v21", "v22", "v23",
919 /* D.2 flip owner bit to mark CQEs from last round. */
920 owner_mask = vand_u16(op_own, owner_check);
921 owner_mask = vceq_u16(owner_mask, ownership);
922 /* D.3 get mask for invalidated CQEs. */
923 opcode = vand_u16(op_own, opcode_check);
924 invalid_mask = vceq_u16(opcode_check, opcode);
925 /* E.1 find compressed CQE format. */
926 comp_mask = vand_u16(op_own, format_check);
927 comp_mask = vceq_u16(comp_mask, format_check);
928 /* D.4 mask out beyond boundary. */
929 invalid_mask = vorr_u16(invalid_mask, mask);
930 /* D.5 merge invalid_mask with invalid owner. */
931 invalid_mask = vorr_u16(invalid_mask, owner_mask);
932 /* E.2 mask out invalid entries. */
933 comp_mask = vbic_u16(comp_mask, invalid_mask);
934 /* E.3 get the first compressed CQE. */
935 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
937 (sizeof(uint16_t) * 8);
938 /* D.6 mask out entries after the compressed CQE. */
939 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ?
940 -1UL >> (comp_idx * sizeof(uint16_t) * 8) :
942 invalid_mask = vorr_u16(invalid_mask, mask);
943 /* D.7 count non-compressed valid CQEs. */
944 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
945 invalid_mask), 0)) / (sizeof(uint16_t) * 8);
947 /* D.2 get the final invalid mask. */
948 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ?
949 -1UL >> (n * sizeof(uint16_t) * 8) : 0);
950 invalid_mask = vorr_u16(invalid_mask, mask);
951 /* D.3 check error in opcode. */
952 opcode = vceq_u16(resp_err_check, opcode);
953 opcode = vbic_u16(opcode, invalid_mask);
954 /* D.4 mark if any error is set */
955 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0);
956 /* C.4 fill in mbuf - rearm_data and packet_type. */
957 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,
959 if (rxq->hw_timestamp) {
960 elts[pos]->timestamp =
962 container_of(p0, struct mlx5_cqe,
963 pkt_info)->timestamp);
964 elts[pos + 1]->timestamp =
966 container_of(p1, struct mlx5_cqe,
967 pkt_info)->timestamp);
968 elts[pos + 2]->timestamp =
970 container_of(p2, struct mlx5_cqe,
971 pkt_info)->timestamp);
972 elts[pos + 3]->timestamp =
974 container_of(p3, struct mlx5_cqe,
975 pkt_info)->timestamp);
977 #ifdef MLX5_PMD_SOFT_COUNTERS
978 /* Add up received bytes count. */
979 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
980 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
983 * Break the loop unless more valid CQE is expected, or if
984 * there's a compressed CQE.
986 if (n != MLX5_VPMD_DESCS_PER_LOOP)
989 /* If no new CQE seen, return without updating cq_db. */
990 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
992 /* Update the consumer indexes for non-compressed CQEs. */
993 assert(nocmp_n <= pkts_n);
994 rxq->cq_ci += nocmp_n;
995 rxq->rq_pi += nocmp_n;
997 #ifdef MLX5_PMD_SOFT_COUNTERS
998 rxq->stats.ipackets += nocmp_n;
999 rxq->stats.ibytes += rcvd_byte;
1001 /* Decompress the last CQE if compressed. */
1002 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
1003 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
1004 rxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n],
1006 /* Return more packets if needed. */
1007 if (nocmp_n < pkts_n) {
1008 uint16_t n = rxq->decompressed;
1010 n = RTE_MIN(n, pkts_n - nocmp_n);
1011 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
1014 rxq->decompressed -= n;
1017 rte_compiler_barrier();
1018 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1022 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */