1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox.
6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_
7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_
16 #include <rte_mempool.h>
17 #include <rte_prefetch.h>
20 #include "mlx5_utils.h"
21 #include "mlx5_rxtx.h"
22 #include "mlx5_rxtx_vec.h"
23 #include "mlx5_autoconf.h"
24 #include "mlx5_defs.h"
27 #pragma GCC diagnostic ignored "-Wcast-qual"
30 * Fill in buffer descriptors in a multi-packet send descriptor.
33 * Pointer to TX queue structure.
35 * Pointer to buffer descriptor to be written.
37 * Pointer to array of packets to be sent.
39 * Number of packets to be filled.
42 txq_wr_dseg_v(struct mlx5_txq_data *txq, uint8_t *dseg,
43 struct rte_mbuf **pkts, unsigned int n)
47 const uint8x16_t dseg_shuf_m = {
48 3, 2, 1, 0, /* length, bswap32 */
49 4, 5, 6, 7, /* lkey */
50 15, 14, 13, 12, /* addr, bswap64 */
53 #ifdef MLX5_PMD_SOFT_COUNTERS
57 for (pos = 0; pos < n; ++pos, dseg += MLX5_WQE_DWORD_SIZE) {
59 struct rte_mbuf *pkt = pkts[pos];
61 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
62 desc = vreinterpretq_u8_u32((uint32x4_t) {
64 mlx5_tx_mb2mr(txq, pkt),
67 desc = vqtbl1q_u8(desc, dseg_shuf_m);
69 #ifdef MLX5_PMD_SOFT_COUNTERS
70 tx_byte += DATA_LEN(pkt);
73 #ifdef MLX5_PMD_SOFT_COUNTERS
74 txq->stats.obytes += tx_byte;
79 * Send multi-segmented packets until it encounters a single segment packet in
83 * Pointer to TX queue structure.
85 * Pointer to array of packets to be sent.
87 * Number of packets to be sent.
90 * Number of packets successfully transmitted (<= pkts_n).
93 txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
96 uint16_t elts_head = txq->elts_head;
97 const uint16_t elts_n = 1 << txq->elts_n;
98 const uint16_t elts_m = elts_n - 1;
99 const uint16_t wq_n = 1 << txq->wqe_n;
100 const uint16_t wq_mask = wq_n - 1;
101 const unsigned int nb_dword_per_wqebb =
102 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
103 const unsigned int nb_dword_in_hdr =
104 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
106 volatile struct mlx5_wqe *wqe = NULL;
108 assert(elts_n > pkts_n);
109 mlx5_tx_complete(txq);
110 /* A CQE slot must always be available. */
111 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
112 if (unlikely(!pkts_n))
114 for (n = 0; n < pkts_n; ++n) {
115 struct rte_mbuf *buf = pkts[n];
116 unsigned int segs_n = buf->nb_segs;
117 unsigned int ds = nb_dword_in_hdr;
118 unsigned int len = PKT_LEN(buf);
119 uint16_t wqe_ci = txq->wqe_ci;
120 const uint8x16_t ctrl_shuf_m = {
121 3, 2, 1, 0, /* bswap32 */
122 7, 6, 5, 4, /* bswap32 */
123 11, 10, 9, 8, /* bswap32 */
134 max_elts = elts_n - (elts_head - txq->elts_tail);
135 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
137 * A MPW session consumes 2 WQEs at most to
138 * include MLX5_MPW_DSEG_MAX pointers.
141 max_elts < segs_n || max_wqe < 2)
143 wqe = &((volatile struct mlx5_wqe64 *)
144 txq->wqes)[wqe_ci & wq_mask].hdr;
145 cs_flags = txq_ol_cksum_to_cs(txq, buf);
146 /* Title WQEBB pointer. */
147 t_wqe = (uint8x16_t *)wqe;
148 dseg = (uint8_t *)(wqe + 1);
150 if (!(ds++ % nb_dword_per_wqebb)) {
152 &((volatile struct mlx5_wqe64 *)
153 txq->wqes)[++wqe_ci & wq_mask];
155 txq_wr_dseg_v(txq, dseg, &buf, 1);
156 dseg += MLX5_WQE_DWORD_SIZE;
157 (*txq->elts)[elts_head++ & elts_m] = buf;
161 /* Fill CTRL in the header. */
162 ctrl = vreinterpretq_u8_u32((uint32x4_t) {
163 MLX5_OPC_MOD_MPW << 24 |
164 txq->wqe_ci << 8 | MLX5_OPCODE_TSO,
165 txq->qp_num_8s | ds, 0, 0});
166 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m);
167 vst1q_u8((void *)t_wqe, ctrl);
168 /* Fill ESEG in the header. */
169 vst1q_u16((void *)(t_wqe + 1),
170 (uint16x8_t) { 0, 0, cs_flags, rte_cpu_to_be_16(len),
172 txq->wqe_ci = wqe_ci;
176 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
177 txq->elts_head = elts_head;
178 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
179 wqe->ctrl[2] = rte_cpu_to_be_32(8);
180 wqe->ctrl[3] = txq->elts_head;
186 #ifdef MLX5_PMD_SOFT_COUNTERS
187 txq->stats.opackets += n;
189 mlx5_tx_dbrec(txq, wqe);
194 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
195 * it returns to make it processed by txq_scatter_v(). All the packets in
196 * the pkts list should be single segment packets having same offload flags.
197 * This must be checked by txq_count_contig_single_seg() and txq_calc_offload().
200 * Pointer to TX queue structure.
202 * Pointer to array of packets to be sent.
204 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
206 * Checksum offload flags to be written in the descriptor.
209 * Number of packets successfully transmitted (<= pkts_n).
211 static inline uint16_t
212 txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
215 struct rte_mbuf **elts;
216 uint16_t elts_head = txq->elts_head;
217 const uint16_t elts_n = 1 << txq->elts_n;
218 const uint16_t elts_m = elts_n - 1;
219 const unsigned int nb_dword_per_wqebb =
220 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
221 const unsigned int nb_dword_in_hdr =
222 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
227 uint32_t comp_req = 0;
228 const uint16_t wq_n = 1 << txq->wqe_n;
229 const uint16_t wq_mask = wq_n - 1;
230 uint16_t wq_idx = txq->wqe_ci & wq_mask;
231 volatile struct mlx5_wqe64 *wq =
232 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
233 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
234 const uint8x16_t ctrl_shuf_m = {
235 3, 2, 1, 0, /* bswap32 */
236 7, 6, 5, 4, /* bswap32 */
237 11, 10, 9, 8, /* bswap32 */
244 /* Make sure all packets can fit into a single WQE. */
245 assert(elts_n > pkts_n);
246 mlx5_tx_complete(txq);
247 max_elts = (elts_n - (elts_head - txq->elts_tail));
248 /* A CQE slot must always be available. */
249 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
250 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
251 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
252 if (unlikely(!pkts_n))
254 elts = &(*txq->elts)[elts_head & elts_m];
255 /* Loop for available tailroom first. */
256 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
257 for (pos = 0; pos < (n & -2); pos += 2)
258 vst1q_u64((void *)&elts[pos], vld1q_u64((void *)&pkts[pos]));
260 elts[pos] = pkts[pos];
261 /* Check if it crosses the end of the queue. */
262 if (unlikely(n < pkts_n)) {
263 elts = &(*txq->elts)[0];
264 for (pos = 0; pos < pkts_n - n; ++pos)
265 elts[pos] = pkts[n + pos];
267 txq->elts_head += pkts_n;
268 /* Save title WQEBB pointer. */
269 t_wqe = (uint8x16_t *)wqe;
270 dseg = (uint8_t *)(wqe + 1);
271 /* Calculate the number of entries to the end. */
273 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
276 txq_wr_dseg_v(txq, dseg, pkts, n);
277 /* Check if it crosses the end of the queue. */
279 dseg = (uint8_t *)txq->wqes;
280 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
282 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
283 txq->elts_comp += pkts_n;
285 /* Request a completion. */
292 /* Fill CTRL in the header. */
293 ctrl = vreinterpretq_u8_u32((uint32x4_t) {
294 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
295 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW,
296 txq->qp_num_8s | (pkts_n + 2),
299 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m);
300 vst1q_u8((void *)t_wqe, ctrl);
301 /* Fill ESEG in the header. */
302 vst1q_u8((void *)(t_wqe + 1),
303 (uint8x16_t) { 0, 0, 0, 0,
307 #ifdef MLX5_PMD_SOFT_COUNTERS
308 txq->stats.opackets += pkts_n;
310 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
312 /* Ring QP doorbell. */
313 mlx5_tx_dbrec_cond_wmb(txq, wqe, pkts_n < MLX5_VPMD_TX_MAX_BURST);
318 * Store free buffers to RX SW ring.
321 * Pointer to RX queue structure.
323 * Pointer to array of packets to be stored.
325 * Number of packets to be stored.
328 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
330 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
331 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
335 for (pos = 0; pos < p; pos += 2) {
338 mbp = vld1q_u64((void *)&elts[pos]);
339 vst1q_u64((void *)&pkts[pos], mbp);
342 pkts[pos] = elts[pos];
346 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
347 * extracted from the title completion descriptor.
350 * Pointer to RX queue structure.
352 * Pointer to completion array having a compressed completion at first.
354 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
355 * the title completion descriptor to be copied to the rest of mbufs.
358 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
359 struct rte_mbuf **elts)
361 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info;
362 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
365 unsigned int inv = 0;
366 /* Mask to shuffle from extracted mini CQE to mbuf. */
367 const uint8x16_t mcqe_shuf_m1 = {
368 -1, -1, -1, -1, /* skip packet_type */
369 7, 6, -1, -1, /* pkt_len, bswap16 */
370 7, 6, /* data_len, bswap16 */
371 -1, -1, /* skip vlan_tci */
372 3, 2, 1, 0 /* hash.rss, bswap32 */
374 const uint8x16_t mcqe_shuf_m2 = {
375 -1, -1, -1, -1, /* skip packet_type */
376 15, 14, -1, -1, /* pkt_len, bswap16 */
377 15, 14, /* data_len, bswap16 */
378 -1, -1, /* skip vlan_tci */
379 11, 10, 9, 8 /* hash.rss, bswap32 */
381 /* Restore the compressed count. Must be 16 bits. */
382 const uint16_t mcqe_n = t_pkt->data_len +
383 (rxq->crc_present * ETHER_CRC_LEN);
384 const uint64x2_t rearm =
385 vld1q_u64((void *)&t_pkt->rearm_data);
386 const uint32x4_t rxdf_mask = {
387 0xffffffff, /* packet_type */
388 0, /* skip pkt_len */
389 0xffff0000, /* vlan_tci, skip data_len */
390 0, /* skip hash.rss */
392 const uint8x16_t rxdf =
393 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1),
394 vreinterpretq_u8_u32(rxdf_mask));
395 const uint16x8_t crc_adj = {
397 rxq->crc_present * ETHER_CRC_LEN, 0,
398 rxq->crc_present * ETHER_CRC_LEN, 0,
401 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
402 #ifdef MLX5_PMD_SOFT_COUNTERS
403 uint32_t rcvd_byte = 0;
405 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
406 const uint8x8_t len_shuf_m = {
408 15, 14, /* 2nd mCQE */
409 23, 22, /* 3rd mCQE */
410 31, 30 /* 4th mCQE */
414 * A. load mCQEs into a 128bit register.
415 * B. store rearm data to mbuf.
416 * C. combine data from mCQEs with rx_descriptor_fields1.
417 * D. store rx_descriptor_fields1.
418 * E. store flow tag (rte_flow mark).
420 for (pos = 0; pos < mcqe_n; ) {
421 uint8_t *p = (void *)&mcq[pos % 8];
422 uint8_t *e0 = (void *)&elts[pos]->rearm_data;
423 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data;
424 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data;
425 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data;
427 #ifdef MLX5_PMD_SOFT_COUNTERS
428 uint16x4_t invalid_mask =
429 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
430 -1UL << ((mcqe_n - pos) *
431 sizeof(uint16_t) * 8) : 0);
434 if (!(pos & 0x7) && pos + 8 < mcqe_n)
435 rte_prefetch0((void *)(cq + pos + 8));
437 /* A.1 load mCQEs into a 128bit register. */
438 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t"
439 /* B.1 store rearm data to mbuf. */
440 "st1 {%[rearm].2d}, [%[e0]] \n\t"
441 "add %[e0], %[e0], #16 \n\t"
442 "st1 {%[rearm].2d}, [%[e1]] \n\t"
443 "add %[e1], %[e1], #16 \n\t"
444 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
445 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t"
446 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t"
447 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
448 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
449 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
450 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
451 /* D.1 store rx_descriptor_fields1. */
452 "st1 {v18.2d}, [%[e0]] \n\t"
453 "st1 {v19.2d}, [%[e1]] \n\t"
454 /* B.1 store rearm data to mbuf. */
455 "st1 {%[rearm].2d}, [%[e2]] \n\t"
456 "add %[e2], %[e2], #16 \n\t"
457 "st1 {%[rearm].2d}, [%[e3]] \n\t"
458 "add %[e3], %[e3], #16 \n\t"
459 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
460 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t"
461 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t"
462 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
463 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
464 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
465 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
466 /* D.1 store rx_descriptor_fields1. */
467 "st1 {v18.2d}, [%[e2]] \n\t"
468 "st1 {v19.2d}, [%[e3]] \n\t"
469 #ifdef MLX5_PMD_SOFT_COUNTERS
470 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t"
472 :[byte_cnt]"=&w"(byte_cnt)
476 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
477 [mcqe_shuf_m1]"w"(mcqe_shuf_m1),
478 [mcqe_shuf_m2]"w"(mcqe_shuf_m2),
479 [crc_adj]"w"(crc_adj),
480 [len_shuf_m]"w"(len_shuf_m)
481 :"memory", "v16", "v17", "v18", "v19");
482 #ifdef MLX5_PMD_SOFT_COUNTERS
483 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
484 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
487 /* E.1 store flow tag (rte_flow mark). */
488 elts[pos]->hash.fdir.hi = flow_tag;
489 elts[pos + 1]->hash.fdir.hi = flow_tag;
490 elts[pos + 2]->hash.fdir.hi = flow_tag;
491 elts[pos + 3]->hash.fdir.hi = flow_tag;
493 pos += MLX5_VPMD_DESCS_PER_LOOP;
494 /* Move to next CQE and invalidate consumed CQEs. */
495 if (!(pos & 0x7) && pos < mcqe_n) {
496 mcq = (void *)&(cq + pos)->pkt_info;
497 for (i = 0; i < 8; ++i)
498 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
501 /* Invalidate the rest of CQEs. */
502 for (; inv < mcqe_n; ++inv)
503 cq[inv].op_own = MLX5_CQE_INVALIDATE;
504 #ifdef MLX5_PMD_SOFT_COUNTERS
505 rxq->stats.ipackets += mcqe_n;
506 rxq->stats.ibytes += rcvd_byte;
508 rxq->cq_ci += mcqe_n;
512 * Calculate packet type and offload flag for mbuf and store it.
515 * Pointer to RX queue structure.
517 * Array of four 4bytes packet type info extracted from the original
518 * completion descriptor.
520 * Array of four 4bytes flow ID extracted from the original completion
523 * Opcode vector having responder error status. Each field is 4B.
525 * Pointer to array of packets to be filled.
528 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
529 uint32x4_t ptype_info, uint32x4_t flow_tag,
530 uint16x4_t op_err, struct rte_mbuf **pkts)
533 uint32x4_t pinfo, cv_flags;
534 uint32x4_t ol_flags =
535 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH |
536 rxq->hw_timestamp * PKT_RX_TIMESTAMP);
537 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
538 const uint8x16_t cv_flag_sel = {
540 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
541 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
543 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
545 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1),
546 0, 0, 0, 0, 0, 0, 0, 0, 0
548 const uint32x4_t cv_mask =
549 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
550 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
551 const uint64x1_t mbuf_init = vld1_u64(&rxq->mbuf_initializer);
552 const uint64x1_t r32_mask = vcreate_u64(0xffffffff);
553 uint64x2_t rearm0, rearm1, rearm2, rearm3;
556 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT);
557 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR);
558 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID);
559 uint32x4_t invalid_mask;
561 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
562 invalid_mask = vceqzq_u32(flow_tag);
563 ol_flags = vorrq_u32(ol_flags,
564 vbicq_u32(fdir_flags, invalid_mask));
565 /* Mask out invalid entries. */
566 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask);
567 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
568 ol_flags = vorrq_u32(ol_flags,
569 vbicq_u32(fdir_id_flags,
570 vceqq_u32(flow_tag, ft_def)));
573 * ptype_info has the following:
577 * bit[11:10] = l3_hdr_type
578 * bit[14:12] = l4_hdr_type
581 * bit[17] = outer_l3_type
583 ptype = vshrn_n_u32(ptype_info, 10);
584 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
585 ptype = vorr_u16(ptype, op_err);
586 pkts[0]->packet_type =
587 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 6)];
588 pkts[1]->packet_type =
589 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 4)];
590 pkts[2]->packet_type =
591 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 2)];
592 pkts[3]->packet_type =
593 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 0)];
594 /* Fill flags for checksum and VLAN. */
595 pinfo = vandq_u32(ptype_info, ptype_ol_mask);
596 pinfo = vreinterpretq_u32_u8(
597 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo)));
598 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
599 cv_flags = vshlq_n_u32(pinfo, 9);
600 cv_flags = vorrq_u32(pinfo, cv_flags);
601 /* Move back flags to start from byte[0]. */
602 cv_flags = vshrq_n_u32(cv_flags, 8);
603 /* Mask out garbage bits. */
604 cv_flags = vandq_u32(cv_flags, cv_mask);
605 /* Merge to ol_flags. */
606 ol_flags = vorrq_u32(ol_flags, cv_flags);
607 /* Merge mbuf_init and ol_flags, and store. */
608 rearm0 = vcombine_u64(mbuf_init,
609 vshr_n_u64(vget_high_u64(vreinterpretq_u64_u32(
611 rearm1 = vcombine_u64(mbuf_init,
612 vand_u64(vget_high_u64(vreinterpretq_u64_u32(
613 ol_flags)), r32_mask));
614 rearm2 = vcombine_u64(mbuf_init,
615 vshr_n_u64(vget_low_u64(vreinterpretq_u64_u32(
617 rearm3 = vcombine_u64(mbuf_init,
618 vand_u64(vget_low_u64(vreinterpretq_u64_u32(
619 ol_flags)), r32_mask));
620 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0);
621 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1);
622 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2);
623 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3);
627 * Receive burst of packets. An errored completion also consumes a mbuf, but the
628 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
629 * before returning to application.
632 * Pointer to RX queue structure.
634 * Array to store received packets.
636 * Maximum number of packets in array.
638 * Pointer to a flag. Set non-zero value if pkts array has at least one error
642 * Number of packets received including errors (<= pkts_n).
644 static inline uint16_t
645 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
648 const uint16_t q_n = 1 << rxq->cqe_n;
649 const uint16_t q_mask = q_n - 1;
650 volatile struct mlx5_cqe *cq;
651 struct rte_mbuf **elts;
655 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
656 uint16_t nocmp_n = 0;
657 uint16_t rcvd_pkt = 0;
658 unsigned int cq_idx = rxq->cq_ci & q_mask;
659 unsigned int elts_idx;
660 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1)));
661 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001);
662 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0);
663 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c);
664 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0);
665 #ifdef MLX5_PMD_SOFT_COUNTERS
666 uint32_t rcvd_byte = 0;
668 /* Mask to generate 16B length vector. */
669 const uint8x8_t len_shuf_m = {
670 52, 53, /* 4th CQE */
671 36, 37, /* 3rd CQE */
672 20, 21, /* 2nd CQE */
675 /* Mask to extract 16B data from a 64B CQE. */
676 const uint8x16_t cqe_shuf_m = {
677 28, 29, /* hdr_type_etc */
680 47, 46, /* byte_cnt, bswap16 */
681 31, 30, /* vlan_info, bswap16 */
682 15, 14, 13, 12, /* rx_hash_res, bswap32 */
683 57, 58, 59, /* flow_tag */
686 /* Mask to generate 16B data for mbuf. */
687 const uint8x16_t mb_shuf_m = {
688 4, 5, -1, -1, /* pkt_len */
691 8, 9, 10, 11, /* hash.rss */
692 12, 13, 14, -1 /* hash.fdir.hi */
694 /* Mask to generate 16B owner vector. */
695 const uint8x8_t owner_shuf_m = {
696 63, -1, /* 4th CQE */
697 47, -1, /* 3rd CQE */
698 31, -1, /* 2nd CQE */
701 /* Mask to generate a vector having packet_type/ol_flags. */
702 const uint8x16_t ptype_shuf_m = {
703 48, 49, 50, -1, /* 4th CQE */
704 32, 33, 34, -1, /* 3rd CQE */
705 16, 17, 18, -1, /* 2nd CQE */
706 0, 1, 2, -1 /* 1st CQE */
708 /* Mask to generate a vector having flow tags. */
709 const uint8x16_t ftag_shuf_m = {
710 60, 61, 62, -1, /* 4th CQE */
711 44, 45, 46, -1, /* 3rd CQE */
712 28, 29, 30, -1, /* 2nd CQE */
713 12, 13, 14, -1 /* 1st CQE */
715 const uint16x8_t crc_adj = {
716 0, 0, rxq->crc_present * ETHER_CRC_LEN, 0, 0, 0, 0, 0
718 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) };
720 assert(rxq->sges_n == 0);
721 assert(rxq->cqe_n == rxq->elts_n);
722 cq = &(*rxq->cqes)[cq_idx];
723 rte_prefetch_non_temporal(cq);
724 rte_prefetch_non_temporal(cq + 1);
725 rte_prefetch_non_temporal(cq + 2);
726 rte_prefetch_non_temporal(cq + 3);
727 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
730 * rq_ci >= cq_ci >= rq_pi
731 * Definition of indexes:
732 * rq_ci - cq_ci := # of buffers owned by HW (posted).
733 * cq_ci - rq_pi := # of buffers not returned to app (decompressed).
734 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished).
736 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
737 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH)
738 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
739 /* See if there're unreturned mbufs from compressed CQE. */
740 rcvd_pkt = rxq->cq_ci - rxq->rq_pi;
742 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
743 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
744 rxq->rq_pi += rcvd_pkt;
747 elts_idx = rxq->rq_pi & q_mask;
748 elts = &(*rxq->elts)[elts_idx];
749 /* Not to overflow pkts array. */
750 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
751 /* Not to cross queue end. */
752 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
755 /* At this point, there shouldn't be any remained packets. */
756 assert(rxq->rq_pi == rxq->cq_ci);
758 * Note that vectors have reverse order - {v3, v2, v1, v0}, because
759 * there's no instruction to count trailing zeros. __builtin_clzl() is
762 * A. copy 4 mbuf pointers from elts ring to returing pkts.
763 * B. load 64B CQE and extract necessary fields
764 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
765 * following structure:
767 * uint16_t hdr_type_etc;
771 * uint16_t vlan_info;
772 * uint32_t rx_has_res;
773 * uint8_t flow_tag[3];
778 * E. find compressed CQE.
782 pos += MLX5_VPMD_DESCS_PER_LOOP) {
784 uint16x4_t opcode, owner_mask, invalid_mask;
785 uint16x4_t comp_mask;
788 uint32x4_t ptype_info, flow_tag;
789 register uint64x2_t c0, c1, c2, c3;
790 uint8_t *p0, *p1, *p2, *p3;
791 uint8_t *e0 = (void *)&elts[pos]->pkt_len;
792 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len;
793 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len;
794 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len;
795 void *elts_p = (void *)&elts[pos];
796 void *pkts_p = (void *)&pkts[pos];
798 /* A.0 do not cross the end of CQ. */
799 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
800 -1UL >> ((pkts_n - pos) *
801 sizeof(uint16_t) * 8) : 0);
802 p0 = (void *)&cq[pos].pkt_info;
803 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe);
804 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe);
805 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe);
806 /* B.0 (CQE 3) load a block having op_own. */
807 c3 = vld1q_u64((uint64_t *)(p3 + 48));
808 /* B.0 (CQE 2) load a block having op_own. */
809 c2 = vld1q_u64((uint64_t *)(p2 + 48));
810 /* B.0 (CQE 1) load a block having op_own. */
811 c1 = vld1q_u64((uint64_t *)(p1 + 48));
812 /* B.0 (CQE 0) load a block having op_own. */
813 c0 = vld1q_u64((uint64_t *)(p0 + 48));
814 /* Synchronize for loading the rest of blocks. */
816 /* Prefetch next 4 CQEs. */
817 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
818 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP;
819 rte_prefetch_non_temporal(&cq[next]);
820 rte_prefetch_non_temporal(&cq[next + 1]);
821 rte_prefetch_non_temporal(&cq[next + 2]);
822 rte_prefetch_non_temporal(&cq[next + 3]);
825 /* B.1 (CQE 3) load the rest of blocks. */
826 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t"
827 /* B.2 (CQE 3) move the block having op_own. */
828 "mov v19.16b, %[c3].16b \n\t"
829 /* B.3 (CQE 3) extract 16B fields. */
830 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
831 /* B.1 (CQE 2) load the rest of blocks. */
832 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t"
833 /* B.4 (CQE 3) adjust CRC length. */
834 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t"
835 /* C.1 (CQE 3) generate final structure for mbuf. */
836 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t"
837 /* B.2 (CQE 2) move the block having op_own. */
838 "mov v19.16b, %[c2].16b \n\t"
839 /* B.3 (CQE 2) extract 16B fields. */
840 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
841 /* B.1 (CQE 1) load the rest of blocks. */
842 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t"
843 /* B.4 (CQE 2) adjust CRC length. */
844 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t"
845 /* C.1 (CQE 2) generate final structure for mbuf. */
846 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t"
847 /* B.2 (CQE 1) move the block having op_own. */
848 "mov v19.16b, %[c1].16b \n\t"
849 /* B.3 (CQE 1) extract 16B fields. */
850 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
851 /* B.1 (CQE 0) load the rest of blocks. */
852 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t"
853 /* B.4 (CQE 1) adjust CRC length. */
854 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t"
855 /* C.1 (CQE 1) generate final structure for mbuf. */
856 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t"
857 /* B.2 (CQE 0) move the block having op_own. */
858 "mov v19.16b, %[c0].16b \n\t"
859 /* A.1 load mbuf pointers. */
860 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t"
861 /* B.3 (CQE 0) extract 16B fields. */
862 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
863 /* B.4 (CQE 0) adjust CRC length. */
864 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t"
865 /* D.1 extract op_own byte. */
866 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t"
867 /* C.2 (CQE 3) adjust flow mark. */
868 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t"
869 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */
870 "st1 {v15.2d}, [%[e3]] \n\t"
871 /* C.2 (CQE 2) adjust flow mark. */
872 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t"
873 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */
874 "st1 {v14.2d}, [%[e2]] \n\t"
875 /* C.1 (CQE 0) generate final structure for mbuf. */
876 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t"
877 /* C.2 (CQE 1) adjust flow mark. */
878 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t"
879 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
880 "st1 {v13.2d}, [%[e1]] \n\t"
881 #ifdef MLX5_PMD_SOFT_COUNTERS
882 /* Extract byte_cnt. */
883 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t"
885 /* Extract ptype_info. */
886 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t"
887 /* Extract flow_tag. */
888 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t"
889 /* A.2 copy mbuf pointers. */
890 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t"
891 /* C.2 (CQE 0) adjust flow mark. */
892 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t"
893 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
894 "st1 {v12.2d}, [%[e0]] \n\t"
895 :[op_own]"=&w"(op_own),
896 [byte_cnt]"=&w"(byte_cnt),
897 [ptype_info]"=&w"(ptype_info),
898 [flow_tag]"=&w"(flow_tag)
899 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0),
900 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
901 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0),
904 [cqe_shuf_m]"w"(cqe_shuf_m),
905 [mb_shuf_m]"w"(mb_shuf_m),
906 [owner_shuf_m]"w"(owner_shuf_m),
907 [len_shuf_m]"w"(len_shuf_m),
908 [ptype_shuf_m]"w"(ptype_shuf_m),
909 [ftag_shuf_m]"w"(ftag_shuf_m),
910 [crc_adj]"w"(crc_adj),
911 [flow_mark_adj]"w"(flow_mark_adj)
913 "v12", "v13", "v14", "v15",
914 "v16", "v17", "v18", "v19",
915 "v20", "v21", "v22", "v23",
917 /* D.2 flip owner bit to mark CQEs from last round. */
918 owner_mask = vand_u16(op_own, owner_check);
919 owner_mask = vceq_u16(owner_mask, ownership);
920 /* D.3 get mask for invalidated CQEs. */
921 opcode = vand_u16(op_own, opcode_check);
922 invalid_mask = vceq_u16(opcode_check, opcode);
923 /* E.1 find compressed CQE format. */
924 comp_mask = vand_u16(op_own, format_check);
925 comp_mask = vceq_u16(comp_mask, format_check);
926 /* D.4 mask out beyond boundary. */
927 invalid_mask = vorr_u16(invalid_mask, mask);
928 /* D.5 merge invalid_mask with invalid owner. */
929 invalid_mask = vorr_u16(invalid_mask, owner_mask);
930 /* E.2 mask out invalid entries. */
931 comp_mask = vbic_u16(comp_mask, invalid_mask);
932 /* E.3 get the first compressed CQE. */
933 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
935 (sizeof(uint16_t) * 8);
936 /* D.6 mask out entries after the compressed CQE. */
937 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ?
938 -1UL >> (comp_idx * sizeof(uint16_t) * 8) :
940 invalid_mask = vorr_u16(invalid_mask, mask);
941 /* D.7 count non-compressed valid CQEs. */
942 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
943 invalid_mask), 0)) / (sizeof(uint16_t) * 8);
945 /* D.2 get the final invalid mask. */
946 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ?
947 -1UL >> (n * sizeof(uint16_t) * 8) : 0);
948 invalid_mask = vorr_u16(invalid_mask, mask);
949 /* D.3 check error in opcode. */
950 opcode = vceq_u16(resp_err_check, opcode);
951 opcode = vbic_u16(opcode, invalid_mask);
952 /* D.4 mark if any error is set */
953 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0);
954 /* C.4 fill in mbuf - rearm_data and packet_type. */
955 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,
957 if (rxq->hw_timestamp) {
958 elts[pos]->timestamp =
960 container_of(p0, struct mlx5_cqe,
961 pkt_info)->timestamp);
962 elts[pos + 1]->timestamp =
964 container_of(p1, struct mlx5_cqe,
965 pkt_info)->timestamp);
966 elts[pos + 2]->timestamp =
968 container_of(p2, struct mlx5_cqe,
969 pkt_info)->timestamp);
970 elts[pos + 3]->timestamp =
972 container_of(p3, struct mlx5_cqe,
973 pkt_info)->timestamp);
975 #ifdef MLX5_PMD_SOFT_COUNTERS
976 /* Add up received bytes count. */
977 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
978 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
981 * Break the loop unless more valid CQE is expected, or if
982 * there's a compressed CQE.
984 if (n != MLX5_VPMD_DESCS_PER_LOOP)
987 /* If no new CQE seen, return without updating cq_db. */
988 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
990 /* Update the consumer indexes for non-compressed CQEs. */
991 assert(nocmp_n <= pkts_n);
992 rxq->cq_ci += nocmp_n;
993 rxq->rq_pi += nocmp_n;
995 #ifdef MLX5_PMD_SOFT_COUNTERS
996 rxq->stats.ipackets += nocmp_n;
997 rxq->stats.ibytes += rcvd_byte;
999 /* Decompress the last CQE if compressed. */
1000 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
1001 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
1002 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);
1003 /* Return more packets if needed. */
1004 if (nocmp_n < pkts_n) {
1005 uint16_t n = rxq->cq_ci - rxq->rq_pi;
1007 n = RTE_MIN(n, pkts_n - nocmp_n);
1008 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
1013 rte_compiler_barrier();
1014 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1018 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */