4 * Copyright 2017 6WIND S.A.
5 * Copyright 2017 Mellanox.
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38 #include <smmintrin.h>
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
46 #include <infiniband/mlx5dv.h>
48 #pragma GCC diagnostic error "-Wpedantic"
52 #include <rte_mempool.h>
53 #include <rte_prefetch.h>
56 #include "mlx5_utils.h"
57 #include "mlx5_rxtx.h"
58 #include "mlx5_autoconf.h"
59 #include "mlx5_defs.h"
62 #ifndef __INTEL_COMPILER
63 #pragma GCC diagnostic ignored "-Wcast-qual"
67 * Fill in buffer descriptors in a multi-packet send descriptor.
70 * Pointer to TX queue structure.
72 * Pointer to buffer descriptor to be writen.
74 * Pointer to array of packets to be sent.
76 * Number of packets to be filled.
79 txq_wr_dseg_v(struct txq *txq, __m128i *dseg,
80 struct rte_mbuf **pkts, unsigned int n)
84 const __m128i shuf_mask_dseg =
85 _mm_set_epi8(8, 9, 10, 11, /* addr, bswap64 */
87 7, 6, 5, 4, /* lkey */
88 0, 1, 2, 3 /* length, bswap32 */);
89 #ifdef MLX5_PMD_SOFT_COUNTERS
93 for (pos = 0; pos < n; ++pos, ++dseg) {
95 struct rte_mbuf *pkt = pkts[pos];
97 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
98 desc = _mm_set_epi32(addr >> 32,
100 mlx5_tx_mb2mr(txq, pkt),
102 desc = _mm_shuffle_epi8(desc, shuf_mask_dseg);
103 _mm_store_si128(dseg, desc);
104 #ifdef MLX5_PMD_SOFT_COUNTERS
105 tx_byte += DATA_LEN(pkt);
108 #ifdef MLX5_PMD_SOFT_COUNTERS
109 txq->stats.obytes += tx_byte;
114 * Count the number of continuous single segment packets.
117 * Pointer to array of packets.
122 * Number of continuous single segment packets.
124 static inline unsigned int
125 txq_check_multiseg(struct rte_mbuf **pkts, uint16_t pkts_n)
131 /* Count the number of continuous single segment packets. */
132 for (pos = 0; pos < pkts_n; ++pos)
133 if (NB_SEGS(pkts[pos]) > 1)
139 * Count the number of packets having same ol_flags and calculate cs_flags.
142 * Pointer to TX queue structure.
144 * Pointer to array of packets.
148 * Pointer of flags to be returned.
151 * Number of packets having same ol_flags.
153 static inline unsigned int
154 txq_calc_offload(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
158 const uint64_t ol_mask =
159 PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM |
160 PKT_TX_UDP_CKSUM | PKT_TX_TUNNEL_GRE |
161 PKT_TX_TUNNEL_VXLAN | PKT_TX_OUTER_IP_CKSUM;
165 /* Count the number of packets having same ol_flags. */
166 for (pos = 1; pos < pkts_n; ++pos)
167 if ((pkts[pos]->ol_flags ^ pkts[0]->ol_flags) & ol_mask)
169 /* Should open another MPW session for the rest. */
170 if (pkts[0]->ol_flags &
171 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
172 const uint64_t is_tunneled =
175 PKT_TX_TUNNEL_VXLAN);
177 if (is_tunneled && txq->tunnel_en) {
178 *cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
179 MLX5_ETH_WQE_L4_INNER_CSUM;
180 if (pkts[0]->ol_flags & PKT_TX_OUTER_IP_CKSUM)
181 *cs_flags |= MLX5_ETH_WQE_L3_CSUM;
183 *cs_flags = MLX5_ETH_WQE_L3_CSUM |
184 MLX5_ETH_WQE_L4_CSUM;
191 * Send multi-segmented packets until it encounters a single segment packet in
195 * Pointer to TX queue structure.
197 * Pointer to array of packets to be sent.
199 * Number of packets to be sent.
202 * Number of packets successfully transmitted (<= pkts_n).
205 txq_scatter_v(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n)
207 uint16_t elts_head = txq->elts_head;
208 const uint16_t elts_n = 1 << txq->elts_n;
209 const uint16_t elts_m = elts_n - 1;
210 const uint16_t wq_n = 1 << txq->wqe_n;
211 const uint16_t wq_mask = wq_n - 1;
212 const unsigned int nb_dword_per_wqebb =
213 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
214 const unsigned int nb_dword_in_hdr =
215 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
217 volatile struct mlx5_wqe *wqe = NULL;
219 assert(elts_n > pkts_n);
220 mlx5_tx_complete(txq);
221 if (unlikely(!pkts_n))
223 for (n = 0; n < pkts_n; ++n) {
224 struct rte_mbuf *buf = pkts[n];
225 unsigned int segs_n = buf->nb_segs;
226 unsigned int ds = nb_dword_in_hdr;
227 unsigned int len = PKT_LEN(buf);
228 uint16_t wqe_ci = txq->wqe_ci;
229 const __m128i shuf_mask_ctrl =
230 _mm_set_epi8(15, 14, 13, 12,
231 8, 9, 10, 11, /* bswap32 */
232 4, 5, 6, 7, /* bswap32 */
233 0, 1, 2, 3 /* bswap32 */);
234 uint8_t cs_flags = 0;
237 __m128i *t_wqe, *dseg;
241 max_elts = elts_n - (elts_head - txq->elts_tail);
242 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
244 * A MPW session consumes 2 WQEs at most to
245 * include MLX5_MPW_DSEG_MAX pointers.
248 max_elts < segs_n || max_wqe < 2)
250 if (segs_n > MLX5_MPW_DSEG_MAX) {
251 txq->stats.oerrors++;
254 wqe = &((volatile struct mlx5_wqe64 *)
255 txq->wqes)[wqe_ci & wq_mask].hdr;
257 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
258 const uint64_t is_tunneled = buf->ol_flags &
260 PKT_TX_TUNNEL_VXLAN);
262 if (is_tunneled && txq->tunnel_en) {
263 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
264 MLX5_ETH_WQE_L4_INNER_CSUM;
265 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
266 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
268 cs_flags = MLX5_ETH_WQE_L3_CSUM |
269 MLX5_ETH_WQE_L4_CSUM;
272 /* Title WQEBB pointer. */
273 t_wqe = (__m128i *)wqe;
274 dseg = (__m128i *)(wqe + 1);
276 if (!(ds++ % nb_dword_per_wqebb)) {
278 &((volatile struct mlx5_wqe64 *)
279 txq->wqes)[++wqe_ci & wq_mask];
281 txq_wr_dseg_v(txq, dseg++, &buf, 1);
282 (*txq->elts)[elts_head++ & elts_m] = buf;
286 /* Fill CTRL in the header. */
287 ctrl = _mm_set_epi32(0, 0, txq->qp_num_8s | ds,
288 MLX5_OPC_MOD_MPW << 24 |
289 txq->wqe_ci << 8 | MLX5_OPCODE_TSO);
290 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
291 _mm_store_si128(t_wqe, ctrl);
292 /* Fill ESEG in the header. */
293 _mm_store_si128(t_wqe + 1,
294 _mm_set_epi16(0, 0, 0, 0,
295 rte_cpu_to_be_16(len), cs_flags,
297 txq->wqe_ci = wqe_ci;
301 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
302 txq->elts_head = elts_head;
303 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
304 wqe->ctrl[2] = rte_cpu_to_be_32(8);
305 wqe->ctrl[3] = txq->elts_head;
309 #ifdef MLX5_PMD_SOFT_COUNTERS
310 txq->stats.opackets += n;
312 mlx5_tx_dbrec(txq, wqe);
317 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
318 * it returns to make it processed by txq_scatter_v(). All the packets in
319 * the pkts list should be single segment packets having same offload flags.
320 * This must be checked by txq_check_multiseg() and txq_calc_offload().
323 * Pointer to TX queue structure.
325 * Pointer to array of packets to be sent.
327 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
329 * Checksum offload flags to be written in the descriptor.
332 * Number of packets successfully transmitted (<= pkts_n).
334 static inline uint16_t
335 txq_burst_v(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
338 struct rte_mbuf **elts;
339 uint16_t elts_head = txq->elts_head;
340 const uint16_t elts_n = 1 << txq->elts_n;
341 const uint16_t elts_m = elts_n - 1;
342 const unsigned int nb_dword_per_wqebb =
343 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
344 const unsigned int nb_dword_in_hdr =
345 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
350 uint32_t comp_req = 0;
351 const uint16_t wq_n = 1 << txq->wqe_n;
352 const uint16_t wq_mask = wq_n - 1;
353 uint16_t wq_idx = txq->wqe_ci & wq_mask;
354 volatile struct mlx5_wqe64 *wq =
355 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
356 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
357 const __m128i shuf_mask_ctrl =
358 _mm_set_epi8(15, 14, 13, 12,
359 8, 9, 10, 11, /* bswap32 */
360 4, 5, 6, 7, /* bswap32 */
361 0, 1, 2, 3 /* bswap32 */);
362 __m128i *t_wqe, *dseg;
365 /* Make sure all packets can fit into a single WQE. */
366 assert(elts_n > pkts_n);
367 mlx5_tx_complete(txq);
368 max_elts = (elts_n - (elts_head - txq->elts_tail));
369 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
370 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
371 assert(pkts_n <= MLX5_DSEG_MAX - nb_dword_in_hdr);
372 if (unlikely(!pkts_n))
374 elts = &(*txq->elts)[elts_head & elts_m];
375 /* Loop for available tailroom first. */
376 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
377 for (pos = 0; pos < (n & -2); pos += 2)
378 _mm_storeu_si128((__m128i *)&elts[pos],
379 _mm_loadu_si128((__m128i *)&pkts[pos]));
381 elts[pos] = pkts[pos];
382 /* Check if it crosses the end of the queue. */
383 if (unlikely(n < pkts_n)) {
384 elts = &(*txq->elts)[0];
385 for (pos = 0; pos < pkts_n - n; ++pos)
386 elts[pos] = pkts[n + pos];
388 txq->elts_head += pkts_n;
389 /* Save title WQEBB pointer. */
390 t_wqe = (__m128i *)wqe;
391 dseg = (__m128i *)(wqe + 1);
392 /* Calculate the number of entries to the end. */
394 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
397 txq_wr_dseg_v(txq, dseg, pkts, n);
398 /* Check if it crosses the end of the queue. */
400 dseg = (__m128i *)txq->wqes;
401 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
403 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
404 txq->elts_comp += pkts_n;
406 /* Request a completion. */
411 /* Fill CTRL in the header. */
412 ctrl = _mm_set_epi32(txq->elts_head, comp_req,
413 txq->qp_num_8s | (pkts_n + 2),
414 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
415 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW);
416 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
417 _mm_store_si128(t_wqe, ctrl);
418 /* Fill ESEG in the header. */
419 _mm_store_si128(t_wqe + 1,
420 _mm_set_epi8(0, 0, 0, 0,
424 #ifdef MLX5_PMD_SOFT_COUNTERS
425 txq->stats.opackets += pkts_n;
427 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
429 /* Ring QP doorbell. */
430 mlx5_tx_dbrec(txq, wqe);
435 * DPDK callback for vectorized TX.
438 * Generic pointer to TX queue structure.
440 * Packets to transmit.
442 * Number of packets in array.
445 * Number of packets successfully transmitted (<= pkts_n).
448 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
451 struct txq *txq = (struct txq *)dpdk_txq;
454 while (pkts_n > nb_tx) {
458 n = RTE_MIN((uint16_t)(pkts_n - nb_tx), MLX5_VPMD_TX_MAX_BURST);
459 ret = txq_burst_v(txq, &pkts[nb_tx], n, 0);
468 * DPDK callback for vectorized TX with multi-seg packets and offload.
471 * Generic pointer to TX queue structure.
473 * Packets to transmit.
475 * Number of packets in array.
478 * Number of packets successfully transmitted (<= pkts_n).
481 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
483 struct txq *txq = (struct txq *)dpdk_txq;
486 while (pkts_n > nb_tx) {
487 uint8_t cs_flags = 0;
491 /* Transmit multi-seg packets in the head of pkts list. */
492 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS) &&
493 NB_SEGS(pkts[nb_tx]) > 1)
494 nb_tx += txq_scatter_v(txq,
497 n = RTE_MIN((uint16_t)(pkts_n - nb_tx), MLX5_VPMD_TX_MAX_BURST);
498 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS))
499 n = txq_check_multiseg(&pkts[nb_tx], n);
500 if (!(txq->flags & ETH_TXQ_FLAGS_NOOFFLOADS))
501 n = txq_calc_offload(txq, &pkts[nb_tx], n, &cs_flags);
502 ret = txq_burst_v(txq, &pkts[nb_tx], n, cs_flags);
511 * Store free buffers to RX SW ring.
514 * Pointer to RX queue structure.
516 * Pointer to array of packets to be stored.
518 * Number of packets to be stored.
521 rxq_copy_mbuf_v(struct rxq *rxq, struct rte_mbuf **pkts, uint16_t n)
523 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
524 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
528 for (pos = 0; pos < p; pos += 2) {
531 mbp = _mm_loadu_si128((__m128i *)&elts[pos]);
532 _mm_storeu_si128((__m128i *)&pkts[pos], mbp);
535 pkts[pos] = elts[pos];
539 * Replenish buffers for RX in bulk.
542 * Pointer to RX queue structure.
544 * Number of buffers to be replenished.
547 rxq_replenish_bulk_mbuf(struct rxq *rxq, uint16_t n)
549 const uint16_t q_n = 1 << rxq->elts_n;
550 const uint16_t q_mask = q_n - 1;
551 const uint16_t elts_idx = rxq->rq_ci & q_mask;
552 struct rte_mbuf **elts = &(*rxq->elts)[elts_idx];
553 volatile struct mlx5_wqe_data_seg *wq = &(*rxq->wqes)[elts_idx];
556 assert(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH);
557 assert(n <= (uint16_t)(q_n - (rxq->rq_ci - rxq->rq_pi)));
558 assert(MLX5_VPMD_RXQ_RPLNSH_THRESH > MLX5_VPMD_DESCS_PER_LOOP);
559 /* Not to cross queue end. */
560 n = RTE_MIN(n - MLX5_VPMD_DESCS_PER_LOOP, q_n - elts_idx);
561 if (rte_mempool_get_bulk(rxq->mp, (void *)elts, n) < 0) {
562 rxq->stats.rx_nombuf += n;
565 for (i = 0; i < n; ++i)
566 wq[i].addr = rte_cpu_to_be_64((uintptr_t)elts[i]->buf_addr +
567 RTE_PKTMBUF_HEADROOM);
570 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
574 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
575 * extracted from the title completion descriptor.
578 * Pointer to RX queue structure.
580 * Pointer to completion array having a compressed completion at first.
582 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
583 * the title completion descriptor to be copied to the rest of mbufs.
586 rxq_cq_decompress_v(struct rxq *rxq,
587 volatile struct mlx5_cqe *cq,
588 struct rte_mbuf **elts)
590 volatile struct mlx5_mini_cqe8 *mcq = (void *)(cq + 1);
591 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
594 unsigned int inv = 0;
595 /* Mask to shuffle from extracted mini CQE to mbuf. */
596 const __m128i shuf_mask1 =
597 _mm_set_epi8(0, 1, 2, 3, /* rss, bswap32 */
598 -1, -1, /* skip vlan_tci */
599 6, 7, /* data_len, bswap16 */
600 -1, -1, 6, 7, /* pkt_len, bswap16 */
601 -1, -1, -1, -1 /* skip packet_type */);
602 const __m128i shuf_mask2 =
603 _mm_set_epi8(8, 9, 10, 11, /* rss, bswap32 */
604 -1, -1, /* skip vlan_tci */
605 14, 15, /* data_len, bswap16 */
606 -1, -1, 14, 15, /* pkt_len, bswap16 */
607 -1, -1, -1, -1 /* skip packet_type */);
608 /* Restore the compressed count. Must be 16 bits. */
609 const uint16_t mcqe_n = t_pkt->data_len +
610 (rxq->crc_present * ETHER_CRC_LEN);
611 const __m128i rearm =
612 _mm_loadu_si128((__m128i *)&t_pkt->rearm_data);
614 _mm_loadu_si128((__m128i *)&t_pkt->rx_descriptor_fields1);
615 const __m128i crc_adj =
616 _mm_set_epi16(0, 0, 0,
617 rxq->crc_present * ETHER_CRC_LEN,
619 rxq->crc_present * ETHER_CRC_LEN,
621 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
622 #ifdef MLX5_PMD_SOFT_COUNTERS
623 const __m128i zero = _mm_setzero_si128();
624 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
625 uint32_t rcvd_byte = 0;
626 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
627 const __m128i len_shuf_mask =
628 _mm_set_epi8(-1, -1, -1, -1,
634 /* Compile time sanity check for this function. */
635 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
636 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
637 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
638 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
639 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
640 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
642 * A. load mCQEs into a 128bit register.
643 * B. store rearm data to mbuf.
644 * C. combine data from mCQEs with rx_descriptor_fields1.
645 * D. store rx_descriptor_fields1.
646 * E. store flow tag (rte_flow mark).
648 for (pos = 0; pos < mcqe_n; ) {
649 __m128i mcqe1, mcqe2;
650 __m128i rxdf1, rxdf2;
651 #ifdef MLX5_PMD_SOFT_COUNTERS
652 __m128i byte_cnt, invalid_mask;
655 if (!(pos & 0x7) && pos + 8 < mcqe_n)
656 rte_prefetch0((void *)(cq + pos + 8));
657 /* A.1 load mCQEs into a 128bit register. */
658 mcqe1 = _mm_loadu_si128((__m128i *)&mcq[pos % 8]);
659 mcqe2 = _mm_loadu_si128((__m128i *)&mcq[pos % 8 + 2]);
660 /* B.1 store rearm data to mbuf. */
661 _mm_storeu_si128((__m128i *)&elts[pos]->rearm_data, rearm);
662 _mm_storeu_si128((__m128i *)&elts[pos + 1]->rearm_data, rearm);
663 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
664 rxdf1 = _mm_shuffle_epi8(mcqe1, shuf_mask1);
665 rxdf2 = _mm_shuffle_epi8(mcqe1, shuf_mask2);
666 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
667 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
668 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
669 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
670 /* D.1 store rx_descriptor_fields1. */
671 _mm_storeu_si128((__m128i *)
672 &elts[pos]->rx_descriptor_fields1,
674 _mm_storeu_si128((__m128i *)
675 &elts[pos + 1]->rx_descriptor_fields1,
677 /* B.1 store rearm data to mbuf. */
678 _mm_storeu_si128((__m128i *)&elts[pos + 2]->rearm_data, rearm);
679 _mm_storeu_si128((__m128i *)&elts[pos + 3]->rearm_data, rearm);
680 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
681 rxdf1 = _mm_shuffle_epi8(mcqe2, shuf_mask1);
682 rxdf2 = _mm_shuffle_epi8(mcqe2, shuf_mask2);
683 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
684 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
685 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
686 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
687 /* D.1 store rx_descriptor_fields1. */
688 _mm_storeu_si128((__m128i *)
689 &elts[pos + 2]->rx_descriptor_fields1,
691 _mm_storeu_si128((__m128i *)
692 &elts[pos + 3]->rx_descriptor_fields1,
694 #ifdef MLX5_PMD_SOFT_COUNTERS
695 invalid_mask = _mm_set_epi64x(0,
697 sizeof(uint16_t) * 8);
698 invalid_mask = _mm_sll_epi64(ones, invalid_mask);
699 mcqe1 = _mm_srli_si128(mcqe1, 4);
700 byte_cnt = _mm_blend_epi16(mcqe1, mcqe2, 0xcc);
701 byte_cnt = _mm_shuffle_epi8(byte_cnt, len_shuf_mask);
702 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
703 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
704 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
707 /* E.1 store flow tag (rte_flow mark). */
708 elts[pos]->hash.fdir.hi = flow_tag;
709 elts[pos + 1]->hash.fdir.hi = flow_tag;
710 elts[pos + 2]->hash.fdir.hi = flow_tag;
711 elts[pos + 3]->hash.fdir.hi = flow_tag;
713 pos += MLX5_VPMD_DESCS_PER_LOOP;
714 /* Move to next CQE and invalidate consumed CQEs. */
715 if (!(pos & 0x7) && pos < mcqe_n) {
716 mcq = (void *)(cq + pos);
717 for (i = 0; i < 8; ++i)
718 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
721 /* Invalidate the rest of CQEs. */
722 for (; inv < mcqe_n; ++inv)
723 cq[inv].op_own = MLX5_CQE_INVALIDATE;
724 #ifdef MLX5_PMD_SOFT_COUNTERS
725 rxq->stats.ipackets += mcqe_n;
726 rxq->stats.ibytes += rcvd_byte;
728 rxq->cq_ci += mcqe_n;
732 * Calculate packet type and offload flag for mbuf and store it.
735 * Pointer to RX queue structure.
737 * Array of four 16bytes completions extracted from the original completion
740 * Opcode vector having responder error status. Each field is 4B.
742 * Pointer to array of packets to be filled.
745 rxq_cq_to_ptype_oflags_v(struct rxq *rxq, __m128i cqes[4], __m128i op_err,
746 struct rte_mbuf **pkts)
748 __m128i pinfo0, pinfo1;
749 __m128i pinfo, ptype;
750 __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH);
752 const __m128i zero = _mm_setzero_si128();
753 const __m128i ptype_mask =
754 _mm_set_epi32(0xfd06, 0xfd06, 0xfd06, 0xfd06);
755 const __m128i ptype_ol_mask =
756 _mm_set_epi32(0x106, 0x106, 0x106, 0x106);
757 const __m128i pinfo_mask =
758 _mm_set_epi32(0x3, 0x3, 0x3, 0x3);
759 const __m128i cv_flag_sel =
760 _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
761 (uint8_t)((PKT_RX_IP_CKSUM_GOOD |
762 PKT_RX_L4_CKSUM_GOOD) >> 1),
764 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
766 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
767 (uint8_t)(PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED),
769 const __m128i cv_mask =
770 _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
771 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
772 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
773 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
774 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
775 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
776 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
777 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED);
778 const __m128i mbuf_init =
779 _mm_loadl_epi64((__m128i *)&rxq->mbuf_initializer);
780 __m128i rearm0, rearm1, rearm2, rearm3;
782 /* Extract pkt_info field. */
783 pinfo0 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
784 pinfo1 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
785 pinfo = _mm_unpacklo_epi64(pinfo0, pinfo1);
786 /* Extract hdr_type_etc field. */
787 pinfo0 = _mm_unpackhi_epi32(cqes[0], cqes[1]);
788 pinfo1 = _mm_unpackhi_epi32(cqes[2], cqes[3]);
789 ptype = _mm_unpacklo_epi64(pinfo0, pinfo1);
791 const __m128i pinfo_ft_mask =
792 _mm_set_epi32(0xffffff00, 0xffffff00,
793 0xffffff00, 0xffffff00);
794 const __m128i fdir_flags = _mm_set1_epi32(PKT_RX_FDIR);
795 const __m128i fdir_id_flags = _mm_set1_epi32(PKT_RX_FDIR_ID);
796 __m128i flow_tag, invalid_mask;
798 flow_tag = _mm_and_si128(pinfo, pinfo_ft_mask);
799 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
800 invalid_mask = _mm_cmpeq_epi32(flow_tag, zero);
801 ol_flags = _mm_or_si128(ol_flags,
802 _mm_andnot_si128(invalid_mask,
804 /* Mask out invalid entries. */
805 flow_tag = _mm_andnot_si128(invalid_mask, flow_tag);
806 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
807 ol_flags = _mm_or_si128(ol_flags,
809 _mm_cmpeq_epi32(flow_tag,
814 * Merge the two fields to generate the following:
818 * bit[11:10] = l3_hdr_type
819 * bit[14:12] = l4_hdr_type
822 * bit[17] = outer_l3_type
824 ptype = _mm_and_si128(ptype, ptype_mask);
825 pinfo = _mm_and_si128(pinfo, pinfo_mask);
826 pinfo = _mm_slli_epi32(pinfo, 16);
827 /* Make pinfo has merged fields for ol_flags calculation. */
828 pinfo = _mm_or_si128(ptype, pinfo);
829 ptype = _mm_srli_epi32(pinfo, 10);
830 ptype = _mm_packs_epi32(ptype, zero);
831 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
832 op_err = _mm_srli_epi16(op_err, 8);
833 ptype = _mm_or_si128(ptype, op_err);
834 pkts[0]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 0)];
835 pkts[1]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 2)];
836 pkts[2]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 4)];
837 pkts[3]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 6)];
838 /* Fill flags for checksum and VLAN. */
839 pinfo = _mm_and_si128(pinfo, ptype_ol_mask);
840 pinfo = _mm_shuffle_epi8(cv_flag_sel, pinfo);
841 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
842 cv_flags = _mm_slli_epi32(pinfo, 9);
843 cv_flags = _mm_or_si128(pinfo, cv_flags);
844 /* Move back flags to start from byte[0]. */
845 cv_flags = _mm_srli_epi32(cv_flags, 8);
846 /* Mask out garbage bits. */
847 cv_flags = _mm_and_si128(cv_flags, cv_mask);
848 /* Merge to ol_flags. */
849 ol_flags = _mm_or_si128(ol_flags, cv_flags);
850 /* Merge mbuf_init and ol_flags. */
851 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
852 offsetof(struct rte_mbuf, rearm_data) + 8);
853 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 8), 0x30);
854 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 4), 0x30);
855 rearm2 = _mm_blend_epi16(mbuf_init, ol_flags, 0x30);
856 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(ol_flags, 4), 0x30);
857 /* Write 8B rearm_data and 8B ol_flags. */
858 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
859 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
860 _mm_store_si128((__m128i *)&pkts[0]->rearm_data, rearm0);
861 _mm_store_si128((__m128i *)&pkts[1]->rearm_data, rearm1);
862 _mm_store_si128((__m128i *)&pkts[2]->rearm_data, rearm2);
863 _mm_store_si128((__m128i *)&pkts[3]->rearm_data, rearm3);
867 * Skip error packets.
870 * Pointer to RX queue structure.
872 * Array to store received packets.
874 * Maximum number of packets in array.
877 * Number of packets successfully received (<= pkts_n).
880 rxq_handle_pending_error(struct rxq *rxq, struct rte_mbuf **pkts,
885 #ifdef MLX5_PMD_SOFT_COUNTERS
886 uint32_t err_bytes = 0;
889 for (i = 0; i < pkts_n; ++i) {
890 struct rte_mbuf *pkt = pkts[i];
892 if (pkt->packet_type == RTE_PTYPE_ALL_MASK) {
893 #ifdef MLX5_PMD_SOFT_COUNTERS
894 err_bytes += PKT_LEN(pkt);
896 rte_pktmbuf_free_seg(pkt);
901 rxq->stats.idropped += (pkts_n - n);
902 #ifdef MLX5_PMD_SOFT_COUNTERS
903 /* Correct counters of errored completions. */
904 rxq->stats.ipackets -= (pkts_n - n);
905 rxq->stats.ibytes -= err_bytes;
907 rxq->pending_err = 0;
912 * Receive burst of packets. An errored completion also consumes a mbuf, but the
913 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
914 * before returning to application.
917 * Pointer to RX queue structure.
919 * Array to store received packets.
921 * Maximum number of packets in array.
924 * Number of packets received including errors (<= pkts_n).
926 static inline uint16_t
927 rxq_burst_v(struct rxq *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
929 const uint16_t q_n = 1 << rxq->cqe_n;
930 const uint16_t q_mask = q_n - 1;
931 volatile struct mlx5_cqe *cq;
932 struct rte_mbuf **elts;
936 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
937 uint16_t nocmp_n = 0;
938 uint16_t rcvd_pkt = 0;
939 unsigned int cq_idx = rxq->cq_ci & q_mask;
940 unsigned int elts_idx;
941 unsigned int ownership = !!(rxq->cq_ci & (q_mask + 1));
942 const __m128i owner_check =
943 _mm_set_epi64x(0x0100000001000000LL, 0x0100000001000000LL);
944 const __m128i opcode_check =
945 _mm_set_epi64x(0xf0000000f0000000LL, 0xf0000000f0000000LL);
946 const __m128i format_check =
947 _mm_set_epi64x(0x0c0000000c000000LL, 0x0c0000000c000000LL);
948 const __m128i resp_err_check =
949 _mm_set_epi64x(0xe0000000e0000000LL, 0xe0000000e0000000LL);
950 #ifdef MLX5_PMD_SOFT_COUNTERS
951 uint32_t rcvd_byte = 0;
952 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
953 const __m128i len_shuf_mask =
954 _mm_set_epi8(-1, -1, -1, -1,
959 /* Mask to shuffle from extracted CQE to mbuf. */
960 const __m128i shuf_mask =
961 _mm_set_epi8(-1, 3, 2, 1, /* fdir.hi */
962 12, 13, 14, 15, /* rss, bswap32 */
963 10, 11, /* vlan_tci, bswap16 */
964 4, 5, /* data_len, bswap16 */
965 -1, -1, /* zero out 2nd half of pkt_len */
966 4, 5 /* pkt_len, bswap16 */);
967 /* Mask to blend from the last Qword to the first DQword. */
968 const __m128i blend_mask =
969 _mm_set_epi8(-1, -1, -1, -1,
973 const __m128i zero = _mm_setzero_si128();
974 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
975 const __m128i crc_adj =
976 _mm_set_epi16(0, 0, 0, 0, 0,
977 rxq->crc_present * ETHER_CRC_LEN,
979 rxq->crc_present * ETHER_CRC_LEN);
980 const __m128i flow_mark_adj = _mm_set_epi32(rxq->mark * (-1), 0, 0, 0);
982 /* Compile time sanity check for this function. */
983 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
984 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
985 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
986 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
987 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, pkt_info) != 0);
988 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rx_hash_res) !=
989 offsetof(struct mlx5_cqe, pkt_info) + 12);
990 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rsvd1) +
991 sizeof(((struct mlx5_cqe *)0)->rsvd1) !=
992 offsetof(struct mlx5_cqe, hdr_type_etc));
993 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, vlan_info) !=
994 offsetof(struct mlx5_cqe, hdr_type_etc) + 2);
995 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rsvd2) +
996 sizeof(((struct mlx5_cqe *)0)->rsvd2) !=
997 offsetof(struct mlx5_cqe, byte_cnt));
998 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, sop_drop_qpn) !=
999 RTE_ALIGN(offsetof(struct mlx5_cqe, sop_drop_qpn), 8));
1000 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, op_own) !=
1001 offsetof(struct mlx5_cqe, sop_drop_qpn) + 7);
1002 assert(rxq->sges_n == 0);
1003 assert(rxq->cqe_n == rxq->elts_n);
1004 cq = &(*rxq->cqes)[cq_idx];
1006 rte_prefetch0(cq + 1);
1007 rte_prefetch0(cq + 2);
1008 rte_prefetch0(cq + 3);
1009 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
1012 * rq_ci >= cq_ci >= rq_pi
1013 * Definition of indexes:
1014 * rq_ci - cq_ci := # of buffers owned by HW (posted).
1015 * cq_ci - rq_pi := # of buffers not returned to app (decompressed).
1016 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished).
1018 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
1019 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH)
1020 rxq_replenish_bulk_mbuf(rxq, repl_n);
1021 /* See if there're unreturned mbufs from compressed CQE. */
1022 rcvd_pkt = rxq->cq_ci - rxq->rq_pi;
1024 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
1025 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
1026 rxq->rq_pi += rcvd_pkt;
1029 elts_idx = rxq->rq_pi & q_mask;
1030 elts = &(*rxq->elts)[elts_idx];
1031 /* Not to overflow pkts array. */
1032 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
1033 /* Not to cross queue end. */
1034 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
1037 /* At this point, there shouldn't be any remained packets. */
1038 assert(rxq->rq_pi == rxq->cq_ci);
1040 * A. load first Qword (8bytes) in one loop.
1041 * B. copy 4 mbuf pointers from elts ring to returing pkts.
1042 * C. load remained CQE data and extract necessary fields.
1043 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
1044 * following structure:
1047 * uint8_t flow_tag[3];
1048 * uint16_t byte_cnt;
1051 * uint16_t hdr_type_etc;
1052 * uint16_t vlan_info;
1053 * uint32_t rx_has_res;
1056 * E. get valid CQEs.
1057 * F. find compressed CQE.
1061 pos += MLX5_VPMD_DESCS_PER_LOOP) {
1062 __m128i cqes[MLX5_VPMD_DESCS_PER_LOOP];
1063 __m128i cqe_tmp1, cqe_tmp2;
1064 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
1065 __m128i op_own, op_own_tmp1, op_own_tmp2;
1066 __m128i opcode, owner_mask, invalid_mask;
1069 #ifdef MLX5_PMD_SOFT_COUNTERS
1073 __m128i p = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0);
1074 unsigned int p1, p2, p3;
1076 /* Prefetch next 4 CQEs. */
1077 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
1078 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP]);
1079 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 1]);
1080 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 2]);
1081 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 3]);
1083 /* A.0 do not cross the end of CQ. */
1084 mask = _mm_set_epi64x(0, (pkts_n - pos) * sizeof(uint16_t) * 8);
1085 mask = _mm_sll_epi64(ones, mask);
1086 p = _mm_andnot_si128(mask, p);
1087 /* A.1 load cqes. */
1088 p3 = _mm_extract_epi16(p, 3);
1089 cqes[3] = _mm_loadl_epi64((__m128i *)
1090 &cq[pos + p3].sop_drop_qpn);
1091 rte_compiler_barrier();
1092 p2 = _mm_extract_epi16(p, 2);
1093 cqes[2] = _mm_loadl_epi64((__m128i *)
1094 &cq[pos + p2].sop_drop_qpn);
1095 rte_compiler_barrier();
1096 /* B.1 load mbuf pointers. */
1097 mbp1 = _mm_loadu_si128((__m128i *)&elts[pos]);
1098 mbp2 = _mm_loadu_si128((__m128i *)&elts[pos + 2]);
1099 /* A.1 load a block having op_own. */
1100 p1 = _mm_extract_epi16(p, 1);
1101 cqes[1] = _mm_loadl_epi64((__m128i *)
1102 &cq[pos + p1].sop_drop_qpn);
1103 rte_compiler_barrier();
1104 cqes[0] = _mm_loadl_epi64((__m128i *)
1105 &cq[pos].sop_drop_qpn);
1106 /* B.2 copy mbuf pointers. */
1107 _mm_storeu_si128((__m128i *)&pkts[pos], mbp1);
1108 _mm_storeu_si128((__m128i *)&pkts[pos + 2], mbp2);
1109 rte_compiler_barrier();
1110 /* C.1 load remained CQE data and extract necessary fields. */
1111 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p3]);
1112 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos + p2]);
1113 cqes[3] = _mm_blendv_epi8(cqes[3], cqe_tmp2, blend_mask);
1114 cqes[2] = _mm_blendv_epi8(cqes[2], cqe_tmp1, blend_mask);
1115 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p3].rsvd1[3]);
1116 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos + p2].rsvd1[3]);
1117 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x30);
1118 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x30);
1119 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p3].rsvd2[10]);
1120 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos + p2].rsvd2[10]);
1121 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x04);
1122 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x04);
1123 /* C.2 generate final structure for mbuf with swapping bytes. */
1124 pkt_mb3 = _mm_shuffle_epi8(cqes[3], shuf_mask);
1125 pkt_mb2 = _mm_shuffle_epi8(cqes[2], shuf_mask);
1126 /* C.3 adjust CRC length. */
1127 pkt_mb3 = _mm_sub_epi16(pkt_mb3, crc_adj);
1128 pkt_mb2 = _mm_sub_epi16(pkt_mb2, crc_adj);
1129 /* C.4 adjust flow mark. */
1130 pkt_mb3 = _mm_add_epi32(pkt_mb3, flow_mark_adj);
1131 pkt_mb2 = _mm_add_epi32(pkt_mb2, flow_mark_adj);
1132 /* D.1 fill in mbuf - rx_descriptor_fields1. */
1133 _mm_storeu_si128((void *)&pkts[pos + 3]->pkt_len, pkt_mb3);
1134 _mm_storeu_si128((void *)&pkts[pos + 2]->pkt_len, pkt_mb2);
1135 /* E.1 extract op_own field. */
1136 op_own_tmp2 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
1137 /* C.1 load remained CQE data and extract necessary fields. */
1138 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p1]);
1139 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos]);
1140 cqes[1] = _mm_blendv_epi8(cqes[1], cqe_tmp2, blend_mask);
1141 cqes[0] = _mm_blendv_epi8(cqes[0], cqe_tmp1, blend_mask);
1142 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p1].rsvd1[3]);
1143 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos].rsvd1[3]);
1144 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x30);
1145 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x30);
1146 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p1].rsvd2[10]);
1147 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos].rsvd2[10]);
1148 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x04);
1149 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x04);
1150 /* C.2 generate final structure for mbuf with swapping bytes. */
1151 pkt_mb1 = _mm_shuffle_epi8(cqes[1], shuf_mask);
1152 pkt_mb0 = _mm_shuffle_epi8(cqes[0], shuf_mask);
1153 /* C.3 adjust CRC length. */
1154 pkt_mb1 = _mm_sub_epi16(pkt_mb1, crc_adj);
1155 pkt_mb0 = _mm_sub_epi16(pkt_mb0, crc_adj);
1156 /* C.4 adjust flow mark. */
1157 pkt_mb1 = _mm_add_epi32(pkt_mb1, flow_mark_adj);
1158 pkt_mb0 = _mm_add_epi32(pkt_mb0, flow_mark_adj);
1159 /* E.1 extract op_own byte. */
1160 op_own_tmp1 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
1161 op_own = _mm_unpackhi_epi64(op_own_tmp1, op_own_tmp2);
1162 /* D.1 fill in mbuf - rx_descriptor_fields1. */
1163 _mm_storeu_si128((void *)&pkts[pos + 1]->pkt_len, pkt_mb1);
1164 _mm_storeu_si128((void *)&pkts[pos]->pkt_len, pkt_mb0);
1165 /* E.2 flip owner bit to mark CQEs from last round. */
1166 owner_mask = _mm_and_si128(op_own, owner_check);
1168 owner_mask = _mm_xor_si128(owner_mask, owner_check);
1169 owner_mask = _mm_cmpeq_epi32(owner_mask, owner_check);
1170 owner_mask = _mm_packs_epi32(owner_mask, zero);
1171 /* E.3 get mask for invalidated CQEs. */
1172 opcode = _mm_and_si128(op_own, opcode_check);
1173 invalid_mask = _mm_cmpeq_epi32(opcode_check, opcode);
1174 invalid_mask = _mm_packs_epi32(invalid_mask, zero);
1175 /* E.4 mask out beyond boundary. */
1176 invalid_mask = _mm_or_si128(invalid_mask, mask);
1177 /* E.5 merge invalid_mask with invalid owner. */
1178 invalid_mask = _mm_or_si128(invalid_mask, owner_mask);
1179 /* F.1 find compressed CQE format. */
1180 comp_mask = _mm_and_si128(op_own, format_check);
1181 comp_mask = _mm_cmpeq_epi32(comp_mask, format_check);
1182 comp_mask = _mm_packs_epi32(comp_mask, zero);
1183 /* F.2 mask out invalid entries. */
1184 comp_mask = _mm_andnot_si128(invalid_mask, comp_mask);
1185 comp_idx = _mm_cvtsi128_si64(comp_mask);
1186 /* F.3 get the first compressed CQE. */
1187 comp_idx = comp_idx ?
1188 __builtin_ctzll(comp_idx) /
1189 (sizeof(uint16_t) * 8) :
1190 MLX5_VPMD_DESCS_PER_LOOP;
1191 /* E.6 mask out entries after the compressed CQE. */
1192 mask = _mm_set_epi64x(0, comp_idx * sizeof(uint16_t) * 8);
1193 mask = _mm_sll_epi64(ones, mask);
1194 invalid_mask = _mm_or_si128(invalid_mask, mask);
1195 /* E.7 count non-compressed valid CQEs. */
1196 n = _mm_cvtsi128_si64(invalid_mask);
1197 n = n ? __builtin_ctzll(n) / (sizeof(uint16_t) * 8) :
1198 MLX5_VPMD_DESCS_PER_LOOP;
1200 /* D.2 get the final invalid mask. */
1201 mask = _mm_set_epi64x(0, n * sizeof(uint16_t) * 8);
1202 mask = _mm_sll_epi64(ones, mask);
1203 invalid_mask = _mm_or_si128(invalid_mask, mask);
1204 /* D.3 check error in opcode. */
1205 opcode = _mm_cmpeq_epi32(resp_err_check, opcode);
1206 opcode = _mm_packs_epi32(opcode, zero);
1207 opcode = _mm_andnot_si128(invalid_mask, opcode);
1208 /* D.4 mark if any error is set */
1209 rxq->pending_err |= !!_mm_cvtsi128_si64(opcode);
1210 /* D.5 fill in mbuf - rearm_data and packet_type. */
1211 rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
1212 #ifdef MLX5_PMD_SOFT_COUNTERS
1213 /* Add up received bytes count. */
1214 byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);
1215 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
1216 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
1217 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
1220 * Break the loop unless more valid CQE is expected, or if
1221 * there's a compressed CQE.
1223 if (n != MLX5_VPMD_DESCS_PER_LOOP)
1226 /* If no new CQE seen, return without updating cq_db. */
1227 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
1229 /* Update the consumer indexes for non-compressed CQEs. */
1230 assert(nocmp_n <= pkts_n);
1231 rxq->cq_ci += nocmp_n;
1232 rxq->rq_pi += nocmp_n;
1233 rcvd_pkt += nocmp_n;
1234 #ifdef MLX5_PMD_SOFT_COUNTERS
1235 rxq->stats.ipackets += nocmp_n;
1236 rxq->stats.ibytes += rcvd_byte;
1238 /* Decompress the last CQE if compressed. */
1239 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
1240 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
1241 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);
1242 /* Return more packets if needed. */
1243 if (nocmp_n < pkts_n) {
1244 uint16_t n = rxq->cq_ci - rxq->rq_pi;
1246 n = RTE_MIN(n, pkts_n - nocmp_n);
1247 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
1253 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1258 * DPDK callback for vectorized RX.
1261 * Generic pointer to RX queue structure.
1263 * Array to store received packets.
1265 * Maximum number of packets in array.
1268 * Number of packets successfully received (<= pkts_n).
1271 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1273 struct rxq *rxq = dpdk_rxq;
1276 nb_rx = rxq_burst_v(rxq, pkts, pkts_n);
1277 if (unlikely(rxq->pending_err))
1278 nb_rx = rxq_handle_pending_error(rxq, pkts, nb_rx);
1283 * Check Tx queue flags are set for raw vectorized Tx.
1286 * Pointer to private structure.
1289 * 1 if supported, negative errno value if not.
1291 int __attribute__((cold))
1292 priv_check_raw_vec_tx_support(struct priv *priv)
1296 /* All the configured queues should support. */
1297 for (i = 0; i < priv->txqs_n; ++i) {
1298 struct txq *txq = (*priv->txqs)[i];
1300 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS) ||
1301 !(txq->flags & ETH_TXQ_FLAGS_NOOFFLOADS))
1304 if (i != priv->txqs_n)
1310 * Check a device can support vectorized TX.
1313 * Pointer to private structure.
1316 * 1 if supported, negative errno value if not.
1318 int __attribute__((cold))
1319 priv_check_vec_tx_support(struct priv *priv)
1321 if (!priv->tx_vec_en ||
1322 priv->txqs_n > MLX5_VPMD_MIN_TXQS ||
1323 priv->mps != MLX5_MPW_ENHANCED ||
1330 * Check a RX queue can support vectorized RX.
1333 * Pointer to RX queue.
1336 * 1 if supported, negative errno value if not.
1338 int __attribute__((cold))
1339 rxq_check_vec_support(struct rxq *rxq)
1341 struct rxq_ctrl *ctrl = container_of(rxq, struct rxq_ctrl, rxq);
1343 if (!ctrl->priv->rx_vec_en || rxq->sges_n != 0)
1349 * Check a device can support vectorized RX.
1352 * Pointer to private structure.
1355 * 1 if supported, negative errno value if not.
1357 int __attribute__((cold))
1358 priv_check_vec_rx_support(struct priv *priv)
1362 if (!priv->rx_vec_en)
1364 /* All the configured queues should support. */
1365 for (i = 0; i < priv->rxqs_n; ++i) {
1366 struct rxq *rxq = (*priv->rxqs)[i];
1368 if (rxq_check_vec_support(rxq) < 0)
1371 if (i != priv->rxqs_n)