4 * Copyright 2017 6WIND S.A.
5 * Copyright 2017 Mellanox.
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8 * modification, are permitted provided that the following conditions
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38 #include <smmintrin.h>
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
46 #include <infiniband/mlx5_hw.h>
47 #include <infiniband/arch.h>
49 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_mempool.h>
54 #include <rte_prefetch.h>
57 #include "mlx5_utils.h"
58 #include "mlx5_rxtx.h"
59 #include "mlx5_autoconf.h"
60 #include "mlx5_defs.h"
63 #ifndef __INTEL_COMPILER
64 #pragma GCC diagnostic ignored "-Wcast-qual"
68 * Fill in buffer descriptors in a multi-packet send descriptor.
71 * Pointer to TX queue structure.
73 * Pointer to buffer descriptor to be writen.
75 * Pointer to array of packets to be sent.
77 * Number of packets to be filled.
80 txq_wr_dseg_v(struct txq *txq, __m128i *dseg,
81 struct rte_mbuf **pkts, unsigned int n)
85 const __m128i shuf_mask_dseg =
86 _mm_set_epi8(8, 9, 10, 11, /* addr, bswap64 */
88 7, 6, 5, 4, /* lkey */
89 0, 1, 2, 3 /* length, bswap32 */);
90 #ifdef MLX5_PMD_SOFT_COUNTERS
94 for (pos = 0; pos < n; ++pos, ++dseg) {
96 struct rte_mbuf *pkt = pkts[pos];
98 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
99 desc = _mm_set_epi32(addr >> 32,
101 mlx5_tx_mb2mr(txq, pkt),
103 desc = _mm_shuffle_epi8(desc, shuf_mask_dseg);
104 _mm_store_si128(dseg, desc);
105 #ifdef MLX5_PMD_SOFT_COUNTERS
106 tx_byte += DATA_LEN(pkt);
109 #ifdef MLX5_PMD_SOFT_COUNTERS
110 txq->stats.obytes += tx_byte;
115 * Count the number of continuous single segment packets. The first packet must
116 * be a single segment packet.
119 * Pointer to array of packets.
124 * Number of continuous single segment packets.
126 static inline unsigned int
127 txq_check_multiseg(struct rte_mbuf **pkts, uint16_t pkts_n)
133 assert(NB_SEGS(pkts[0]) == 1);
134 /* Count the number of continuous single segment packets. */
135 for (pos = 1; pos < pkts_n; ++pos)
136 if (NB_SEGS(pkts[pos]) > 1)
142 * Count the number of packets having same ol_flags and calculate cs_flags.
145 * Pointer to TX queue structure.
147 * Pointer to array of packets.
151 * Pointer of flags to be returned.
154 * Number of packets having same ol_flags.
156 static inline unsigned int
157 txq_calc_offload(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
161 const uint64_t ol_mask =
162 PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM |
163 PKT_TX_UDP_CKSUM | PKT_TX_TUNNEL_GRE |
164 PKT_TX_TUNNEL_VXLAN | PKT_TX_OUTER_IP_CKSUM;
168 /* Count the number of packets having same ol_flags. */
169 for (pos = 1; pos < pkts_n; ++pos)
170 if ((pkts[pos]->ol_flags ^ pkts[0]->ol_flags) & ol_mask)
172 /* Should open another MPW session for the rest. */
173 if (pkts[0]->ol_flags &
174 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
175 const uint64_t is_tunneled =
178 PKT_TX_TUNNEL_VXLAN);
180 if (is_tunneled && txq->tunnel_en) {
181 *cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
182 MLX5_ETH_WQE_L4_INNER_CSUM;
183 if (pkts[0]->ol_flags & PKT_TX_OUTER_IP_CKSUM)
184 *cs_flags |= MLX5_ETH_WQE_L3_CSUM;
186 *cs_flags = MLX5_ETH_WQE_L3_CSUM |
187 MLX5_ETH_WQE_L4_CSUM;
194 * Send multi-segmented packets until it encounters a single segment packet in
198 * Pointer to TX queue structure.
200 * Pointer to array of packets to be sent.
202 * Number of packets to be sent.
205 * Number of packets successfully transmitted (<= pkts_n).
208 txq_scatter_v(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n)
210 uint16_t elts_head = txq->elts_head;
211 const uint16_t elts_n = 1 << txq->elts_n;
212 const uint16_t elts_m = elts_n - 1;
213 const uint16_t wq_n = 1 << txq->wqe_n;
214 const uint16_t wq_mask = wq_n - 1;
215 const unsigned int nb_dword_per_wqebb =
216 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
217 const unsigned int nb_dword_in_hdr =
218 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
220 volatile struct mlx5_wqe *wqe = NULL;
222 assert(elts_n > pkts_n);
223 mlx5_tx_complete(txq);
224 if (unlikely(!pkts_n))
226 for (n = 0; n < pkts_n; ++n) {
227 struct rte_mbuf *buf = pkts[n];
228 unsigned int segs_n = buf->nb_segs;
229 unsigned int ds = nb_dword_in_hdr;
230 unsigned int len = PKT_LEN(buf);
231 uint16_t wqe_ci = txq->wqe_ci;
232 const __m128i shuf_mask_ctrl =
233 _mm_set_epi8(15, 14, 13, 12,
234 8, 9, 10, 11, /* bswap32 */
235 4, 5, 6, 7, /* bswap32 */
236 0, 1, 2, 3 /* bswap32 */);
237 uint8_t cs_flags = 0;
240 __m128i *t_wqe, *dseg;
244 max_elts = elts_n - (elts_head - txq->elts_tail);
245 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
247 * A MPW session consumes 2 WQEs at most to
248 * include MLX5_MPW_DSEG_MAX pointers.
251 max_elts < segs_n || max_wqe < 2)
253 wqe = &((volatile struct mlx5_wqe64 *)
254 txq->wqes)[wqe_ci & wq_mask].hdr;
256 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
257 const uint64_t is_tunneled = buf->ol_flags &
259 PKT_TX_TUNNEL_VXLAN);
261 if (is_tunneled && txq->tunnel_en) {
262 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
263 MLX5_ETH_WQE_L4_INNER_CSUM;
264 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
265 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
267 cs_flags = MLX5_ETH_WQE_L3_CSUM |
268 MLX5_ETH_WQE_L4_CSUM;
271 /* Title WQEBB pointer. */
272 t_wqe = (__m128i *)wqe;
273 dseg = (__m128i *)(wqe + 1);
275 if (!(ds++ % nb_dword_per_wqebb)) {
277 &((volatile struct mlx5_wqe64 *)
278 txq->wqes)[++wqe_ci & wq_mask];
280 txq_wr_dseg_v(txq, dseg++, &buf, 1);
281 (*txq->elts)[elts_head++ & elts_m] = buf;
285 /* Fill CTRL in the header. */
286 ctrl = _mm_set_epi32(0, 0, txq->qp_num_8s | ds,
287 MLX5_OPC_MOD_MPW << 24 |
288 txq->wqe_ci << 8 | MLX5_OPCODE_TSO);
289 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
290 _mm_store_si128(t_wqe, ctrl);
291 /* Fill ESEG in the header. */
292 _mm_store_si128(t_wqe + 1,
293 _mm_set_epi16(0, 0, 0, 0,
294 htons(len), cs_flags,
296 txq->wqe_ci = wqe_ci;
300 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
301 txq->elts_head = elts_head;
302 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
303 wqe->ctrl[2] = htonl(8);
304 wqe->ctrl[3] = txq->elts_head;
308 #ifdef MLX5_PMD_SOFT_COUNTERS
309 txq->stats.opackets += n;
311 mlx5_tx_dbrec(txq, wqe);
316 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
317 * it returns to make it processed by txq_scatter_v(). All the packets in
318 * the pkts list should be single segment packets having same offload flags.
319 * This must be checked by txq_check_multiseg() and txq_calc_offload().
322 * Pointer to TX queue structure.
324 * Pointer to array of packets to be sent.
326 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
328 * Checksum offload flags to be written in the descriptor.
331 * Number of packets successfully transmitted (<= pkts_n).
333 static inline uint16_t
334 txq_burst_v(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
337 struct rte_mbuf **elts;
338 uint16_t elts_head = txq->elts_head;
339 const uint16_t elts_n = 1 << txq->elts_n;
340 const uint16_t elts_m = elts_n - 1;
341 const unsigned int nb_dword_per_wqebb =
342 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
343 const unsigned int nb_dword_in_hdr =
344 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
349 uint32_t comp_req = 0;
350 const uint16_t wq_n = 1 << txq->wqe_n;
351 const uint16_t wq_mask = wq_n - 1;
352 uint16_t wq_idx = txq->wqe_ci & wq_mask;
353 volatile struct mlx5_wqe64 *wq =
354 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
355 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
356 const __m128i shuf_mask_ctrl =
357 _mm_set_epi8(15, 14, 13, 12,
358 8, 9, 10, 11, /* bswap32 */
359 4, 5, 6, 7, /* bswap32 */
360 0, 1, 2, 3 /* bswap32 */);
361 __m128i *t_wqe, *dseg;
364 /* Make sure all packets can fit into a single WQE. */
365 assert(elts_n > pkts_n);
366 mlx5_tx_complete(txq);
367 max_elts = (elts_n - (elts_head - txq->elts_tail));
368 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
369 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
370 if (unlikely(!pkts_n))
372 elts = &(*txq->elts)[elts_head & elts_m];
373 /* Loop for available tailroom first. */
374 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
375 for (pos = 0; pos < (n & -2); pos += 2)
376 _mm_storeu_si128((__m128i *)&elts[pos],
377 _mm_loadu_si128((__m128i *)&pkts[pos]));
379 elts[pos] = pkts[pos];
380 /* Check if it crosses the end of the queue. */
381 if (unlikely(n < pkts_n)) {
382 elts = &(*txq->elts)[0];
383 for (pos = 0; pos < pkts_n - n; ++pos)
384 elts[pos] = pkts[n + pos];
386 txq->elts_head += pkts_n;
387 /* Save title WQEBB pointer. */
388 t_wqe = (__m128i *)wqe;
389 dseg = (__m128i *)(wqe + 1);
390 /* Calculate the number of entries to the end. */
392 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
395 txq_wr_dseg_v(txq, dseg, pkts, n);
396 /* Check if it crosses the end of the queue. */
398 dseg = (__m128i *)txq->wqes;
399 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
401 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
402 txq->elts_comp += pkts_n;
404 /* Request a completion. */
409 /* Fill CTRL in the header. */
410 ctrl = _mm_set_epi32(txq->elts_head, comp_req,
411 txq->qp_num_8s | (pkts_n + 2),
412 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
413 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW);
414 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
415 _mm_store_si128(t_wqe, ctrl);
416 /* Fill ESEG in the header. */
417 _mm_store_si128(t_wqe + 1,
418 _mm_set_epi8(0, 0, 0, 0,
422 #ifdef MLX5_PMD_SOFT_COUNTERS
423 txq->stats.opackets += pkts_n;
425 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
427 /* Ring QP doorbell. */
428 mlx5_tx_dbrec(txq, wqe);
433 * DPDK callback for vectorized TX.
436 * Generic pointer to TX queue structure.
438 * Packets to transmit.
440 * Number of packets in array.
443 * Number of packets successfully transmitted (<= pkts_n).
446 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
449 struct txq *txq = (struct txq *)dpdk_txq;
452 while (pkts_n > nb_tx) {
456 n = RTE_MIN((uint16_t)(pkts_n - nb_tx), MLX5_VPMD_TX_MAX_BURST);
457 ret = txq_burst_v(txq, &pkts[nb_tx], n, 0);
466 * DPDK callback for vectorized TX with multi-seg packets and offload.
469 * Generic pointer to TX queue structure.
471 * Packets to transmit.
473 * Number of packets in array.
476 * Number of packets successfully transmitted (<= pkts_n).
479 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
481 struct txq *txq = (struct txq *)dpdk_txq;
484 while (pkts_n > nb_tx) {
485 uint8_t cs_flags = 0;
489 /* Transmit multi-seg packets in the head of pkts list. */
490 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS) &&
491 NB_SEGS(pkts[nb_tx]) > 1)
492 nb_tx += txq_scatter_v(txq,
495 n = RTE_MIN((uint16_t)(pkts_n - nb_tx), MLX5_VPMD_TX_MAX_BURST);
496 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS))
497 n = txq_check_multiseg(&pkts[nb_tx], n);
498 if (!(txq->flags & ETH_TXQ_FLAGS_NOOFFLOADS))
499 n = txq_calc_offload(txq, &pkts[nb_tx], n, &cs_flags);
500 ret = txq_burst_v(txq, &pkts[nb_tx], n, cs_flags);
509 * Store free buffers to RX SW ring.
512 * Pointer to RX queue structure.
514 * Pointer to array of packets to be stored.
516 * Number of packets to be stored.
519 rxq_copy_mbuf_v(struct rxq *rxq, struct rte_mbuf **pkts, uint16_t n)
521 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
522 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
526 for (pos = 0; pos < p; pos += 2) {
529 mbp = _mm_loadu_si128((__m128i *)&elts[pos]);
530 _mm_storeu_si128((__m128i *)&pkts[pos], mbp);
533 pkts[pos] = elts[pos];
537 * Replenish buffers for RX in bulk.
540 * Pointer to RX queue structure.
542 * Number of buffers to be replenished.
545 rxq_replenish_bulk_mbuf(struct rxq *rxq, uint16_t n)
547 const uint16_t q_n = 1 << rxq->elts_n;
548 const uint16_t q_mask = q_n - 1;
549 const uint16_t elts_idx = rxq->rq_ci & q_mask;
550 struct rte_mbuf **elts = &(*rxq->elts)[elts_idx];
551 volatile struct mlx5_wqe_data_seg *wq = &(*rxq->wqes)[elts_idx];
554 assert(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH);
555 assert(n <= (uint16_t)(q_n - (rxq->rq_ci - rxq->rq_pi)));
556 assert(MLX5_VPMD_RXQ_RPLNSH_THRESH > MLX5_VPMD_DESCS_PER_LOOP);
557 /* Not to cross queue end. */
558 n = RTE_MIN(n - MLX5_VPMD_DESCS_PER_LOOP, q_n - elts_idx);
559 if (rte_mempool_get_bulk(rxq->mp, (void *)elts, n) < 0) {
560 rxq->stats.rx_nombuf += n;
563 for (i = 0; i < n; ++i)
564 wq[i].addr = htonll((uintptr_t)elts[i]->buf_addr +
565 RTE_PKTMBUF_HEADROOM);
568 *rxq->rq_db = htonl(rxq->rq_ci);
572 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
573 * extracted from the title completion descriptor.
576 * Pointer to RX queue structure.
578 * Pointer to completion array having a compressed completion at first.
580 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
581 * the title completion descriptor to be copied to the rest of mbufs.
584 rxq_cq_decompress_v(struct rxq *rxq,
585 volatile struct mlx5_cqe *cq,
586 struct rte_mbuf **elts)
588 volatile struct mlx5_mini_cqe8 *mcq = (void *)(cq + 1);
589 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
592 unsigned int inv = 0;
593 /* Mask to shuffle from extracted mini CQE to mbuf. */
594 const __m128i shuf_mask1 =
595 _mm_set_epi8(0, 1, 2, 3, /* rss, bswap32 */
596 -1, -1, /* skip vlan_tci */
597 6, 7, /* data_len, bswap16 */
598 -1, -1, 6, 7, /* pkt_len, bswap16 */
599 -1, -1, -1, -1 /* skip packet_type */);
600 const __m128i shuf_mask2 =
601 _mm_set_epi8(8, 9, 10, 11, /* rss, bswap32 */
602 -1, -1, /* skip vlan_tci */
603 14, 15, /* data_len, bswap16 */
604 -1, -1, 14, 15, /* pkt_len, bswap16 */
605 -1, -1, -1, -1 /* skip packet_type */);
606 /* Restore the compressed count. Must be 16 bits. */
607 const uint16_t mcqe_n = t_pkt->data_len +
608 (rxq->crc_present * ETHER_CRC_LEN);
609 const __m128i rearm =
610 _mm_loadu_si128((__m128i *)&t_pkt->rearm_data);
612 _mm_loadu_si128((__m128i *)&t_pkt->rx_descriptor_fields1);
613 const __m128i crc_adj =
614 _mm_set_epi16(0, 0, 0,
615 rxq->crc_present * ETHER_CRC_LEN,
617 rxq->crc_present * ETHER_CRC_LEN,
619 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
620 #ifdef MLX5_PMD_SOFT_COUNTERS
621 const __m128i zero = _mm_setzero_si128();
622 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
623 uint32_t rcvd_byte = 0;
624 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
625 const __m128i len_shuf_mask =
626 _mm_set_epi8(-1, -1, -1, -1,
632 /* Compile time sanity check for this function. */
633 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
634 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
635 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
636 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
637 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
638 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
640 * A. load mCQEs into a 128bit register.
641 * B. store rearm data to mbuf.
642 * C. combine data from mCQEs with rx_descriptor_fields1.
643 * D. store rx_descriptor_fields1.
644 * E. store flow tag (rte_flow mark).
646 for (pos = 0; pos < mcqe_n; ) {
647 __m128i mcqe1, mcqe2;
648 __m128i rxdf1, rxdf2;
649 #ifdef MLX5_PMD_SOFT_COUNTERS
650 __m128i byte_cnt, invalid_mask;
653 if (!(pos & 0x7) && pos + 8 < mcqe_n)
654 rte_prefetch0((void *)(cq + pos + 8));
655 /* A.1 load mCQEs into a 128bit register. */
656 mcqe1 = _mm_loadu_si128((__m128i *)&mcq[pos % 8]);
657 mcqe2 = _mm_loadu_si128((__m128i *)&mcq[pos % 8 + 2]);
658 /* B.1 store rearm data to mbuf. */
659 _mm_storeu_si128((__m128i *)&elts[pos]->rearm_data, rearm);
660 _mm_storeu_si128((__m128i *)&elts[pos + 1]->rearm_data, rearm);
661 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
662 rxdf1 = _mm_shuffle_epi8(mcqe1, shuf_mask1);
663 rxdf2 = _mm_shuffle_epi8(mcqe1, shuf_mask2);
664 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
665 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
666 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
667 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
668 /* D.1 store rx_descriptor_fields1. */
669 _mm_storeu_si128((__m128i *)
670 &elts[pos]->rx_descriptor_fields1,
672 _mm_storeu_si128((__m128i *)
673 &elts[pos + 1]->rx_descriptor_fields1,
675 /* B.1 store rearm data to mbuf. */
676 _mm_storeu_si128((__m128i *)&elts[pos + 2]->rearm_data, rearm);
677 _mm_storeu_si128((__m128i *)&elts[pos + 3]->rearm_data, rearm);
678 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
679 rxdf1 = _mm_shuffle_epi8(mcqe2, shuf_mask1);
680 rxdf2 = _mm_shuffle_epi8(mcqe2, shuf_mask2);
681 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
682 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
683 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
684 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
685 /* D.1 store rx_descriptor_fields1. */
686 _mm_storeu_si128((__m128i *)
687 &elts[pos + 2]->rx_descriptor_fields1,
689 _mm_storeu_si128((__m128i *)
690 &elts[pos + 3]->rx_descriptor_fields1,
692 #ifdef MLX5_PMD_SOFT_COUNTERS
693 invalid_mask = _mm_set_epi64x(0,
695 sizeof(uint16_t) * 8);
696 invalid_mask = _mm_sll_epi64(ones, invalid_mask);
697 mcqe1 = _mm_srli_si128(mcqe1, 4);
698 byte_cnt = _mm_blend_epi16(mcqe1, mcqe2, 0xcc);
699 byte_cnt = _mm_shuffle_epi8(byte_cnt, len_shuf_mask);
700 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
701 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
702 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
705 /* E.1 store flow tag (rte_flow mark). */
706 elts[pos]->hash.fdir.hi = flow_tag;
707 elts[pos + 1]->hash.fdir.hi = flow_tag;
708 elts[pos + 2]->hash.fdir.hi = flow_tag;
709 elts[pos + 3]->hash.fdir.hi = flow_tag;
711 pos += MLX5_VPMD_DESCS_PER_LOOP;
712 /* Move to next CQE and invalidate consumed CQEs. */
713 if (!(pos & 0x7) && pos < mcqe_n) {
714 mcq = (void *)(cq + pos);
715 for (i = 0; i < 8; ++i)
716 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
719 /* Invalidate the rest of CQEs. */
720 for (; inv < mcqe_n; ++inv)
721 cq[inv].op_own = MLX5_CQE_INVALIDATE;
722 #ifdef MLX5_PMD_SOFT_COUNTERS
723 rxq->stats.ipackets += mcqe_n;
724 rxq->stats.ibytes += rcvd_byte;
726 rxq->cq_ci += mcqe_n;
730 * Calculate packet type and offload flag for mbuf and store it.
733 * Pointer to RX queue structure.
735 * Array of four 16bytes completions extracted from the original completion
738 * Opcode vector having responder error status. Each field is 4B.
740 * Pointer to array of packets to be filled.
743 rxq_cq_to_ptype_oflags_v(struct rxq *rxq, __m128i cqes[4], __m128i op_err,
744 struct rte_mbuf **pkts)
746 __m128i pinfo0, pinfo1;
747 __m128i pinfo, ptype;
748 __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH);
750 const __m128i zero = _mm_setzero_si128();
751 const __m128i ptype_mask =
752 _mm_set_epi32(0xfd06, 0xfd06, 0xfd06, 0xfd06);
753 const __m128i ptype_ol_mask =
754 _mm_set_epi32(0x106, 0x106, 0x106, 0x106);
755 const __m128i pinfo_mask =
756 _mm_set_epi32(0x3, 0x3, 0x3, 0x3);
757 const __m128i cv_flag_sel =
758 _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
759 (uint8_t)((PKT_RX_IP_CKSUM_GOOD |
760 PKT_RX_L4_CKSUM_GOOD) >> 1),
762 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
764 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
765 (uint8_t)(PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED),
767 const __m128i cv_mask =
768 _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
769 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
770 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
771 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
772 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
773 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
774 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
775 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED);
776 const __m128i mbuf_init =
777 _mm_loadl_epi64((__m128i *)&rxq->mbuf_initializer);
778 __m128i rearm0, rearm1, rearm2, rearm3;
780 /* Extract pkt_info field. */
781 pinfo0 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
782 pinfo1 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
783 pinfo = _mm_unpacklo_epi64(pinfo0, pinfo1);
784 /* Extract hdr_type_etc field. */
785 pinfo0 = _mm_unpackhi_epi32(cqes[0], cqes[1]);
786 pinfo1 = _mm_unpackhi_epi32(cqes[2], cqes[3]);
787 ptype = _mm_unpacklo_epi64(pinfo0, pinfo1);
789 const __m128i pinfo_ft_mask =
790 _mm_set_epi32(0xffffff00, 0xffffff00,
791 0xffffff00, 0xffffff00);
792 const __m128i fdir_flags = _mm_set1_epi32(PKT_RX_FDIR);
793 const __m128i fdir_id_flags = _mm_set1_epi32(PKT_RX_FDIR_ID);
794 __m128i flow_tag, invalid_mask;
796 flow_tag = _mm_and_si128(pinfo, pinfo_ft_mask);
797 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
798 invalid_mask = _mm_cmpeq_epi32(flow_tag, zero);
799 ol_flags = _mm_or_si128(ol_flags,
800 _mm_andnot_si128(invalid_mask,
802 /* Mask out invalid entries. */
803 flow_tag = _mm_andnot_si128(invalid_mask, flow_tag);
804 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
805 ol_flags = _mm_or_si128(ol_flags,
807 _mm_cmpeq_epi32(flow_tag,
812 * Merge the two fields to generate the following:
816 * bit[11:10] = l3_hdr_type
817 * bit[14:12] = l4_hdr_type
820 * bit[17] = outer_l3_type
822 ptype = _mm_and_si128(ptype, ptype_mask);
823 pinfo = _mm_and_si128(pinfo, pinfo_mask);
824 pinfo = _mm_slli_epi32(pinfo, 16);
825 /* Make pinfo has merged fields for ol_flags calculation. */
826 pinfo = _mm_or_si128(ptype, pinfo);
827 ptype = _mm_srli_epi32(pinfo, 10);
828 ptype = _mm_packs_epi32(ptype, zero);
829 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
830 op_err = _mm_srli_epi16(op_err, 8);
831 ptype = _mm_or_si128(ptype, op_err);
832 pkts[0]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 0)];
833 pkts[1]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 2)];
834 pkts[2]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 4)];
835 pkts[3]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 6)];
836 /* Fill flags for checksum and VLAN. */
837 pinfo = _mm_and_si128(pinfo, ptype_ol_mask);
838 pinfo = _mm_shuffle_epi8(cv_flag_sel, pinfo);
839 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
840 cv_flags = _mm_slli_epi32(pinfo, 9);
841 cv_flags = _mm_or_si128(pinfo, cv_flags);
842 /* Move back flags to start from byte[0]. */
843 cv_flags = _mm_srli_epi32(cv_flags, 8);
844 /* Mask out garbage bits. */
845 cv_flags = _mm_and_si128(cv_flags, cv_mask);
846 /* Merge to ol_flags. */
847 ol_flags = _mm_or_si128(ol_flags, cv_flags);
848 /* Merge mbuf_init and ol_flags. */
849 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
850 offsetof(struct rte_mbuf, rearm_data) + 8);
851 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 8), 0x30);
852 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 4), 0x30);
853 rearm2 = _mm_blend_epi16(mbuf_init, ol_flags, 0x30);
854 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(ol_flags, 4), 0x30);
855 /* Write 8B rearm_data and 8B ol_flags. */
856 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
857 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
858 _mm_store_si128((__m128i *)&pkts[0]->rearm_data, rearm0);
859 _mm_store_si128((__m128i *)&pkts[1]->rearm_data, rearm1);
860 _mm_store_si128((__m128i *)&pkts[2]->rearm_data, rearm2);
861 _mm_store_si128((__m128i *)&pkts[3]->rearm_data, rearm3);
865 * Skip error packets.
868 * Pointer to RX queue structure.
870 * Array to store received packets.
872 * Maximum number of packets in array.
875 * Number of packets successfully received (<= pkts_n).
878 rxq_handle_pending_error(struct rxq *rxq, struct rte_mbuf **pkts,
883 #ifdef MLX5_PMD_SOFT_COUNTERS
884 uint32_t err_bytes = 0;
887 for (i = 0; i < pkts_n; ++i) {
888 struct rte_mbuf *pkt = pkts[i];
890 if (pkt->packet_type == RTE_PTYPE_ALL_MASK) {
891 #ifdef MLX5_PMD_SOFT_COUNTERS
892 err_bytes += PKT_LEN(pkt);
894 rte_pktmbuf_free_seg(pkt);
899 rxq->stats.idropped += (pkts_n - n);
900 #ifdef MLX5_PMD_SOFT_COUNTERS
901 /* Correct counters of errored completions. */
902 rxq->stats.ipackets -= (pkts_n - n);
903 rxq->stats.ibytes -= err_bytes;
905 rxq->pending_err = 0;
910 * Receive burst of packets. An errored completion also consumes a mbuf, but the
911 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
912 * before returning to application.
915 * Pointer to RX queue structure.
917 * Array to store received packets.
919 * Maximum number of packets in array.
922 * Number of packets received including errors (<= pkts_n).
924 static inline uint16_t
925 rxq_burst_v(struct rxq *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
927 const uint16_t q_n = 1 << rxq->cqe_n;
928 const uint16_t q_mask = q_n - 1;
929 volatile struct mlx5_cqe *cq;
930 struct rte_mbuf **elts;
934 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
935 uint16_t nocmp_n = 0;
936 uint16_t rcvd_pkt = 0;
937 unsigned int cq_idx = rxq->cq_ci & q_mask;
938 unsigned int elts_idx;
939 unsigned int ownership = !!(rxq->cq_ci & (q_mask + 1));
940 const __m128i owner_check =
941 _mm_set_epi64x(0x0100000001000000LL, 0x0100000001000000LL);
942 const __m128i opcode_check =
943 _mm_set_epi64x(0xf0000000f0000000LL, 0xf0000000f0000000LL);
944 const __m128i format_check =
945 _mm_set_epi64x(0x0c0000000c000000LL, 0x0c0000000c000000LL);
946 const __m128i resp_err_check =
947 _mm_set_epi64x(0xe0000000e0000000LL, 0xe0000000e0000000LL);
948 #ifdef MLX5_PMD_SOFT_COUNTERS
949 uint32_t rcvd_byte = 0;
950 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
951 const __m128i len_shuf_mask =
952 _mm_set_epi8(-1, -1, -1, -1,
957 /* Mask to shuffle from extracted CQE to mbuf. */
958 const __m128i shuf_mask =
959 _mm_set_epi8(-1, 3, 2, 1, /* fdir.hi */
960 12, 13, 14, 15, /* rss, bswap32 */
961 10, 11, /* vlan_tci, bswap16 */
962 4, 5, /* data_len, bswap16 */
963 -1, -1, /* zero out 2nd half of pkt_len */
964 4, 5 /* pkt_len, bswap16 */);
965 /* Mask to blend from the last Qword to the first DQword. */
966 const __m128i blend_mask =
967 _mm_set_epi8(-1, -1, -1, -1,
971 const __m128i zero = _mm_setzero_si128();
972 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
973 const __m128i crc_adj =
974 _mm_set_epi16(0, 0, 0, 0, 0,
975 rxq->crc_present * ETHER_CRC_LEN,
977 rxq->crc_present * ETHER_CRC_LEN);
978 const __m128i flow_mark_adj = _mm_set_epi32(rxq->mark * (-1), 0, 0, 0);
980 /* Compile time sanity check for this function. */
981 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
982 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
983 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
984 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
985 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, pkt_info) != 0);
986 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rx_hash_res) !=
987 offsetof(struct mlx5_cqe, pkt_info) + 12);
988 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rsvd1) +
989 sizeof(((struct mlx5_cqe *)0)->rsvd1) !=
990 offsetof(struct mlx5_cqe, hdr_type_etc));
991 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, vlan_info) !=
992 offsetof(struct mlx5_cqe, hdr_type_etc) + 2);
993 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rsvd2) +
994 sizeof(((struct mlx5_cqe *)0)->rsvd2) !=
995 offsetof(struct mlx5_cqe, byte_cnt));
996 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, sop_drop_qpn) !=
997 RTE_ALIGN(offsetof(struct mlx5_cqe, sop_drop_qpn), 8));
998 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, op_own) !=
999 offsetof(struct mlx5_cqe, sop_drop_qpn) + 7);
1000 assert(rxq->sges_n == 0);
1001 assert(rxq->cqe_n == rxq->elts_n);
1002 cq = &(*rxq->cqes)[cq_idx];
1004 rte_prefetch0(cq + 1);
1005 rte_prefetch0(cq + 2);
1006 rte_prefetch0(cq + 3);
1007 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
1010 * rq_ci >= cq_ci >= rq_pi
1011 * Definition of indexes:
1012 * rq_ci - cq_ci := # of buffers owned by HW (posted).
1013 * cq_ci - rq_pi := # of buffers not returned to app (decompressed).
1014 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished).
1016 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
1017 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH)
1018 rxq_replenish_bulk_mbuf(rxq, repl_n);
1019 /* See if there're unreturned mbufs from compressed CQE. */
1020 rcvd_pkt = rxq->cq_ci - rxq->rq_pi;
1022 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
1023 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
1024 rxq->rq_pi += rcvd_pkt;
1027 elts_idx = rxq->rq_pi & q_mask;
1028 elts = &(*rxq->elts)[elts_idx];
1029 /* Not to overflow pkts array. */
1030 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
1031 /* Not to cross queue end. */
1032 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
1035 /* At this point, there shouldn't be any remained packets. */
1036 assert(rxq->rq_pi == rxq->cq_ci);
1038 * A. load first Qword (8bytes) in one loop.
1039 * B. copy 4 mbuf pointers from elts ring to returing pkts.
1040 * C. load remained CQE data and extract necessary fields.
1041 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
1042 * following structure:
1045 * uint8_t flow_tag[3];
1046 * uint16_t byte_cnt;
1049 * uint16_t hdr_type_etc;
1050 * uint16_t vlan_info;
1051 * uint32_t rx_has_res;
1054 * E. get valid CQEs.
1055 * F. find compressed CQE.
1059 pos += MLX5_VPMD_DESCS_PER_LOOP) {
1060 __m128i cqes[MLX5_VPMD_DESCS_PER_LOOP];
1061 __m128i cqe_tmp1, cqe_tmp2;
1062 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
1063 __m128i op_own, op_own_tmp1, op_own_tmp2;
1064 __m128i opcode, owner_mask, invalid_mask;
1067 #ifdef MLX5_PMD_SOFT_COUNTERS
1071 __m128i p = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0);
1072 unsigned int p1, p2, p3;
1074 /* Prefetch next 4 CQEs. */
1075 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
1076 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP]);
1077 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 1]);
1078 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 2]);
1079 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 3]);
1081 /* A.0 do not cross the end of CQ. */
1082 mask = _mm_set_epi64x(0, (pkts_n - pos) * sizeof(uint16_t) * 8);
1083 mask = _mm_sll_epi64(ones, mask);
1084 p = _mm_andnot_si128(mask, p);
1085 /* A.1 load cqes. */
1086 p3 = _mm_extract_epi16(p, 3);
1087 cqes[3] = _mm_loadl_epi64((__m128i *)
1088 &cq[pos + p3].sop_drop_qpn);
1089 rte_compiler_barrier();
1090 p2 = _mm_extract_epi16(p, 2);
1091 cqes[2] = _mm_loadl_epi64((__m128i *)
1092 &cq[pos + p2].sop_drop_qpn);
1093 rte_compiler_barrier();
1094 /* B.1 load mbuf pointers. */
1095 mbp1 = _mm_loadu_si128((__m128i *)&elts[pos]);
1096 mbp2 = _mm_loadu_si128((__m128i *)&elts[pos + 2]);
1097 /* A.1 load a block having op_own. */
1098 p1 = _mm_extract_epi16(p, 1);
1099 cqes[1] = _mm_loadl_epi64((__m128i *)
1100 &cq[pos + p1].sop_drop_qpn);
1101 rte_compiler_barrier();
1102 cqes[0] = _mm_loadl_epi64((__m128i *)
1103 &cq[pos].sop_drop_qpn);
1104 /* B.2 copy mbuf pointers. */
1105 _mm_storeu_si128((__m128i *)&pkts[pos], mbp1);
1106 _mm_storeu_si128((__m128i *)&pkts[pos + 2], mbp2);
1107 rte_compiler_barrier();
1108 /* C.1 load remained CQE data and extract necessary fields. */
1109 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p3]);
1110 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos + p2]);
1111 cqes[3] = _mm_blendv_epi8(cqes[3], cqe_tmp2, blend_mask);
1112 cqes[2] = _mm_blendv_epi8(cqes[2], cqe_tmp1, blend_mask);
1113 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p3].rsvd1[3]);
1114 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos + p2].rsvd1[3]);
1115 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x30);
1116 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x30);
1117 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p3].rsvd2[10]);
1118 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos + p2].rsvd2[10]);
1119 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x04);
1120 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x04);
1121 /* C.2 generate final structure for mbuf with swapping bytes. */
1122 pkt_mb3 = _mm_shuffle_epi8(cqes[3], shuf_mask);
1123 pkt_mb2 = _mm_shuffle_epi8(cqes[2], shuf_mask);
1124 /* C.3 adjust CRC length. */
1125 pkt_mb3 = _mm_sub_epi16(pkt_mb3, crc_adj);
1126 pkt_mb2 = _mm_sub_epi16(pkt_mb2, crc_adj);
1127 /* C.4 adjust flow mark. */
1128 pkt_mb3 = _mm_add_epi32(pkt_mb3, flow_mark_adj);
1129 pkt_mb2 = _mm_add_epi32(pkt_mb2, flow_mark_adj);
1130 /* D.1 fill in mbuf - rx_descriptor_fields1. */
1131 _mm_storeu_si128((void *)&pkts[pos + 3]->pkt_len, pkt_mb3);
1132 _mm_storeu_si128((void *)&pkts[pos + 2]->pkt_len, pkt_mb2);
1133 /* E.1 extract op_own field. */
1134 op_own_tmp2 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
1135 /* C.1 load remained CQE data and extract necessary fields. */
1136 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p1]);
1137 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos]);
1138 cqes[1] = _mm_blendv_epi8(cqes[1], cqe_tmp2, blend_mask);
1139 cqes[0] = _mm_blendv_epi8(cqes[0], cqe_tmp1, blend_mask);
1140 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p1].rsvd1[3]);
1141 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos].rsvd1[3]);
1142 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x30);
1143 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x30);
1144 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p1].rsvd2[10]);
1145 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos].rsvd2[10]);
1146 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x04);
1147 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x04);
1148 /* C.2 generate final structure for mbuf with swapping bytes. */
1149 pkt_mb1 = _mm_shuffle_epi8(cqes[1], shuf_mask);
1150 pkt_mb0 = _mm_shuffle_epi8(cqes[0], shuf_mask);
1151 /* C.3 adjust CRC length. */
1152 pkt_mb1 = _mm_sub_epi16(pkt_mb1, crc_adj);
1153 pkt_mb0 = _mm_sub_epi16(pkt_mb0, crc_adj);
1154 /* C.4 adjust flow mark. */
1155 pkt_mb1 = _mm_add_epi32(pkt_mb1, flow_mark_adj);
1156 pkt_mb0 = _mm_add_epi32(pkt_mb0, flow_mark_adj);
1157 /* E.1 extract op_own byte. */
1158 op_own_tmp1 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
1159 op_own = _mm_unpackhi_epi64(op_own_tmp1, op_own_tmp2);
1160 /* D.1 fill in mbuf - rx_descriptor_fields1. */
1161 _mm_storeu_si128((void *)&pkts[pos + 1]->pkt_len, pkt_mb1);
1162 _mm_storeu_si128((void *)&pkts[pos]->pkt_len, pkt_mb0);
1163 /* E.2 flip owner bit to mark CQEs from last round. */
1164 owner_mask = _mm_and_si128(op_own, owner_check);
1166 owner_mask = _mm_xor_si128(owner_mask, owner_check);
1167 owner_mask = _mm_cmpeq_epi32(owner_mask, owner_check);
1168 owner_mask = _mm_packs_epi32(owner_mask, zero);
1169 /* E.3 get mask for invalidated CQEs. */
1170 opcode = _mm_and_si128(op_own, opcode_check);
1171 invalid_mask = _mm_cmpeq_epi32(opcode_check, opcode);
1172 invalid_mask = _mm_packs_epi32(invalid_mask, zero);
1173 /* E.4 mask out beyond boundary. */
1174 invalid_mask = _mm_or_si128(invalid_mask, mask);
1175 /* E.5 merge invalid_mask with invalid owner. */
1176 invalid_mask = _mm_or_si128(invalid_mask, owner_mask);
1177 /* F.1 find compressed CQE format. */
1178 comp_mask = _mm_and_si128(op_own, format_check);
1179 comp_mask = _mm_cmpeq_epi32(comp_mask, format_check);
1180 comp_mask = _mm_packs_epi32(comp_mask, zero);
1181 /* F.2 mask out invalid entries. */
1182 comp_mask = _mm_andnot_si128(invalid_mask, comp_mask);
1183 comp_idx = _mm_cvtsi128_si64(comp_mask);
1184 /* F.3 get the first compressed CQE. */
1185 comp_idx = comp_idx ?
1186 __builtin_ctzll(comp_idx) /
1187 (sizeof(uint16_t) * 8) :
1188 MLX5_VPMD_DESCS_PER_LOOP;
1189 /* E.6 mask out entries after the compressed CQE. */
1190 mask = _mm_set_epi64x(0, comp_idx * sizeof(uint16_t) * 8);
1191 mask = _mm_sll_epi64(ones, mask);
1192 invalid_mask = _mm_or_si128(invalid_mask, mask);
1193 /* E.7 count non-compressed valid CQEs. */
1194 n = _mm_cvtsi128_si64(invalid_mask);
1195 n = n ? __builtin_ctzll(n) / (sizeof(uint16_t) * 8) :
1196 MLX5_VPMD_DESCS_PER_LOOP;
1198 /* D.2 get the final invalid mask. */
1199 mask = _mm_set_epi64x(0, n * sizeof(uint16_t) * 8);
1200 mask = _mm_sll_epi64(ones, mask);
1201 invalid_mask = _mm_or_si128(invalid_mask, mask);
1202 /* D.3 check error in opcode. */
1203 opcode = _mm_cmpeq_epi32(resp_err_check, opcode);
1204 opcode = _mm_packs_epi32(opcode, zero);
1205 opcode = _mm_andnot_si128(invalid_mask, opcode);
1206 /* D.4 mark if any error is set */
1207 rxq->pending_err |= !!_mm_cvtsi128_si64(opcode);
1208 /* D.5 fill in mbuf - rearm_data and packet_type. */
1209 rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
1210 #ifdef MLX5_PMD_SOFT_COUNTERS
1211 /* Add up received bytes count. */
1212 byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);
1213 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
1214 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
1215 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
1218 * Break the loop unless more valid CQE is expected, or if
1219 * there's a compressed CQE.
1221 if (n != MLX5_VPMD_DESCS_PER_LOOP)
1224 /* If no new CQE seen, return without updating cq_db. */
1225 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
1227 /* Update the consumer indexes for non-compressed CQEs. */
1228 assert(nocmp_n <= pkts_n);
1229 rxq->cq_ci += nocmp_n;
1230 rxq->rq_pi += nocmp_n;
1231 rcvd_pkt += nocmp_n;
1232 #ifdef MLX5_PMD_SOFT_COUNTERS
1233 rxq->stats.ipackets += nocmp_n;
1234 rxq->stats.ibytes += rcvd_byte;
1236 /* Decompress the last CQE if compressed. */
1237 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
1238 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
1239 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);
1240 /* Return more packets if needed. */
1241 if (nocmp_n < pkts_n) {
1242 uint16_t n = rxq->cq_ci - rxq->rq_pi;
1244 n = RTE_MIN(n, pkts_n - nocmp_n);
1245 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
1251 *rxq->cq_db = htonl(rxq->cq_ci);
1256 * DPDK callback for vectorized RX.
1259 * Generic pointer to RX queue structure.
1261 * Array to store received packets.
1263 * Maximum number of packets in array.
1266 * Number of packets successfully received (<= pkts_n).
1269 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1271 struct rxq *rxq = dpdk_rxq;
1274 nb_rx = rxq_burst_v(rxq, pkts, pkts_n);
1275 if (unlikely(rxq->pending_err))
1276 nb_rx = rxq_handle_pending_error(rxq, pkts, nb_rx);
1281 * Check Tx queue flags are set for raw vectorized Tx.
1284 * Pointer to private structure.
1287 * 1 if supported, negative errno value if not.
1289 int __attribute__((cold))
1290 priv_check_raw_vec_tx_support(struct priv *priv)
1294 /* All the configured queues should support. */
1295 for (i = 0; i < priv->txqs_n; ++i) {
1296 struct txq *txq = (*priv->txqs)[i];
1298 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS) ||
1299 !(txq->flags & ETH_TXQ_FLAGS_NOOFFLOADS))
1302 if (i != priv->txqs_n)
1308 * Check a device can support vectorized TX.
1311 * Pointer to private structure.
1314 * 1 if supported, negative errno value if not.
1316 int __attribute__((cold))
1317 priv_check_vec_tx_support(struct priv *priv)
1319 if (!priv->tx_vec_en ||
1320 priv->txqs_n > MLX5_VPMD_MIN_TXQS ||
1321 priv->mps != MLX5_MPW_ENHANCED ||
1328 * Check a RX queue can support vectorized RX.
1331 * Pointer to RX queue.
1334 * 1 if supported, negative errno value if not.
1336 int __attribute__((cold))
1337 rxq_check_vec_support(struct rxq *rxq)
1339 struct rxq_ctrl *ctrl = container_of(rxq, struct rxq_ctrl, rxq);
1341 if (!ctrl->priv->rx_vec_en || rxq->sges_n != 0)
1347 * Check a device can support vectorized RX.
1350 * Pointer to private structure.
1353 * 1 if supported, negative errno value if not.
1355 int __attribute__((cold))
1356 priv_check_vec_rx_support(struct priv *priv)
1360 if (!priv->rx_vec_en)
1362 /* All the configured queues should support. */
1363 for (i = 0; i < priv->rxqs_n; ++i) {
1364 struct rxq *rxq = (*priv->rxqs)[i];
1366 if (rxq_check_vec_support(rxq) < 0)
1369 if (i != priv->rxqs_n)