4 * Copyright 2017 6WIND S.A.
5 * Copyright 2017 Mellanox.
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38 #include <smmintrin.h>
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
46 #include <infiniband/mlx5_hw.h>
47 #include <infiniband/arch.h>
49 #pragma GCC diagnostic error "-Wpedantic"
52 /* DPDK headers don't like -pedantic. */
54 #pragma GCC diagnostic ignored "-Wpedantic"
57 #include <rte_mempool.h>
58 #include <rte_prefetch.h>
60 #pragma GCC diagnostic error "-Wpedantic"
64 #include "mlx5_utils.h"
65 #include "mlx5_rxtx.h"
66 #include "mlx5_autoconf.h"
67 #include "mlx5_defs.h"
70 #ifndef __INTEL_COMPILER
71 #pragma GCC diagnostic ignored "-Wcast-qual"
75 * Fill in buffer descriptors in a multi-packet send descriptor.
78 * Pointer to TX queue structure.
80 * Pointer to buffer descriptor to be writen.
82 * Pointer to array of packets to be sent.
84 * Number of packets to be filled.
87 txq_wr_dseg_v(struct txq *txq, __m128i *dseg,
88 struct rte_mbuf **pkts, unsigned int n)
92 const __m128i shuf_mask_dseg =
93 _mm_set_epi8(8, 9, 10, 11, /* addr, bswap64 */
95 7, 6, 5, 4, /* lkey */
96 0, 1, 2, 3 /* length, bswap32 */);
97 #ifdef MLX5_PMD_SOFT_COUNTERS
101 for (pos = 0; pos < n; ++pos, ++dseg) {
103 struct rte_mbuf *pkt = pkts[pos];
105 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
106 desc = _mm_set_epi32(addr >> 32,
108 mlx5_tx_mb2mr(txq, pkt),
110 desc = _mm_shuffle_epi8(desc, shuf_mask_dseg);
111 _mm_store_si128(dseg, desc);
112 #ifdef MLX5_PMD_SOFT_COUNTERS
113 tx_byte += DATA_LEN(pkt);
116 #ifdef MLX5_PMD_SOFT_COUNTERS
117 txq->stats.obytes += tx_byte;
122 * Count the number of continuous single segment packets. The first packet must
123 * be a single segment packet.
126 * Pointer to array of packets.
131 * Number of continuous single segment packets.
133 static inline unsigned int
134 txq_check_multiseg(struct rte_mbuf **pkts, uint16_t pkts_n)
140 assert(NB_SEGS(pkts[0]) == 1);
141 /* Count the number of continuous single segment packets. */
142 for (pos = 1; pos < pkts_n; ++pos)
143 if (NB_SEGS(pkts[pos]) > 1)
149 * Count the number of packets having same ol_flags and calculate cs_flags.
152 * Pointer to TX queue structure.
154 * Pointer to array of packets.
158 * Pointer of flags to be returned.
161 * Number of packets having same ol_flags.
163 static inline unsigned int
164 txq_calc_offload(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
168 const uint64_t ol_mask =
169 PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM |
170 PKT_TX_UDP_CKSUM | PKT_TX_TUNNEL_GRE |
171 PKT_TX_TUNNEL_VXLAN | PKT_TX_OUTER_IP_CKSUM;
175 /* Count the number of packets having same ol_flags. */
176 for (pos = 1; pos < pkts_n; ++pos)
177 if ((pkts[pos]->ol_flags ^ pkts[0]->ol_flags) & ol_mask)
179 /* Should open another MPW session for the rest. */
180 if (pkts[0]->ol_flags &
181 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
182 const uint64_t is_tunneled =
185 PKT_TX_TUNNEL_VXLAN);
187 if (is_tunneled && txq->tunnel_en) {
188 *cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
189 MLX5_ETH_WQE_L4_INNER_CSUM;
190 if (pkts[0]->ol_flags & PKT_TX_OUTER_IP_CKSUM)
191 *cs_flags |= MLX5_ETH_WQE_L3_CSUM;
193 *cs_flags = MLX5_ETH_WQE_L3_CSUM |
194 MLX5_ETH_WQE_L4_CSUM;
201 * Send multi-segmented packets until it encounters a single segment packet in
205 * Pointer to TX queue structure.
207 * Pointer to array of packets to be sent.
209 * Number of packets to be sent.
212 * Number of packets successfully transmitted (<= pkts_n).
215 txq_scatter_v(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n)
217 uint16_t elts_head = txq->elts_head;
218 const uint16_t elts_n = 1 << txq->elts_n;
219 const uint16_t elts_m = elts_n - 1;
220 const uint16_t wq_n = 1 << txq->wqe_n;
221 const uint16_t wq_mask = wq_n - 1;
222 const unsigned int nb_dword_per_wqebb =
223 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
224 const unsigned int nb_dword_in_hdr =
225 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
227 volatile struct mlx5_wqe *wqe = NULL;
229 assert(elts_n > pkts_n);
230 mlx5_tx_complete(txq);
231 if (unlikely(!pkts_n))
233 for (n = 0; n < pkts_n; ++n) {
234 struct rte_mbuf *buf = pkts[n];
235 unsigned int segs_n = buf->nb_segs;
236 unsigned int ds = nb_dword_in_hdr;
237 unsigned int len = PKT_LEN(buf);
238 uint16_t wqe_ci = txq->wqe_ci;
239 const __m128i shuf_mask_ctrl =
240 _mm_set_epi8(15, 14, 13, 12,
241 8, 9, 10, 11, /* bswap32 */
242 4, 5, 6, 7, /* bswap32 */
243 0, 1, 2, 3 /* bswap32 */);
244 uint8_t cs_flags = 0;
247 __m128i *t_wqe, *dseg;
251 max_elts = elts_n - (elts_head - txq->elts_tail);
252 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
254 * A MPW session consumes 2 WQEs at most to
255 * include MLX5_MPW_DSEG_MAX pointers.
258 max_elts < segs_n || max_wqe < 2)
260 wqe = &((volatile struct mlx5_wqe64 *)
261 txq->wqes)[wqe_ci & wq_mask].hdr;
263 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
264 const uint64_t is_tunneled = buf->ol_flags &
266 PKT_TX_TUNNEL_VXLAN);
268 if (is_tunneled && txq->tunnel_en) {
269 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
270 MLX5_ETH_WQE_L4_INNER_CSUM;
271 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
272 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
274 cs_flags = MLX5_ETH_WQE_L3_CSUM |
275 MLX5_ETH_WQE_L4_CSUM;
278 /* Title WQEBB pointer. */
279 t_wqe = (__m128i *)wqe;
280 dseg = (__m128i *)(wqe + 1);
282 if (!(ds++ % nb_dword_per_wqebb)) {
284 &((volatile struct mlx5_wqe64 *)
285 txq->wqes)[++wqe_ci & wq_mask];
287 txq_wr_dseg_v(txq, dseg++, &buf, 1);
288 (*txq->elts)[elts_head++ & elts_m] = buf;
292 /* Fill CTRL in the header. */
293 ctrl = _mm_set_epi32(0, 0, txq->qp_num_8s | ds,
294 MLX5_OPC_MOD_MPW << 24 |
295 txq->wqe_ci << 8 | MLX5_OPCODE_TSO);
296 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
297 _mm_store_si128(t_wqe, ctrl);
298 /* Fill ESEG in the header. */
299 _mm_store_si128(t_wqe + 1,
300 _mm_set_epi16(0, 0, 0, 0,
301 htons(len), cs_flags,
303 txq->wqe_ci = wqe_ci;
307 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
308 txq->elts_head = elts_head;
309 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
310 wqe->ctrl[2] = htonl(8);
311 wqe->ctrl[3] = txq->elts_head;
315 #ifdef MLX5_PMD_SOFT_COUNTERS
316 txq->stats.opackets += n;
318 mlx5_tx_dbrec(txq, wqe);
323 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
324 * it returns to make it processed by txq_scatter_v(). All the packets in
325 * the pkts list should be single segment packets having same offload flags.
326 * This must be checked by txq_check_multiseg() and txq_calc_offload().
329 * Pointer to TX queue structure.
331 * Pointer to array of packets to be sent.
333 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
335 * Checksum offload flags to be written in the descriptor.
338 * Number of packets successfully transmitted (<= pkts_n).
340 static inline uint16_t
341 txq_burst_v(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
344 struct rte_mbuf **elts;
345 uint16_t elts_head = txq->elts_head;
346 const uint16_t elts_n = 1 << txq->elts_n;
347 const uint16_t elts_m = elts_n - 1;
348 const unsigned int nb_dword_per_wqebb =
349 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
350 const unsigned int nb_dword_in_hdr =
351 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
356 uint32_t comp_req = 0;
357 const uint16_t wq_n = 1 << txq->wqe_n;
358 const uint16_t wq_mask = wq_n - 1;
359 uint16_t wq_idx = txq->wqe_ci & wq_mask;
360 volatile struct mlx5_wqe64 *wq =
361 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
362 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
363 const __m128i shuf_mask_ctrl =
364 _mm_set_epi8(15, 14, 13, 12,
365 8, 9, 10, 11, /* bswap32 */
366 4, 5, 6, 7, /* bswap32 */
367 0, 1, 2, 3 /* bswap32 */);
368 __m128i *t_wqe, *dseg;
371 /* Make sure all packets can fit into a single WQE. */
372 assert(elts_n > pkts_n);
373 mlx5_tx_complete(txq);
374 max_elts = (elts_n - (elts_head - txq->elts_tail));
375 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
376 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
377 if (unlikely(!pkts_n))
379 elts = &(*txq->elts)[elts_head & elts_m];
380 /* Loop for available tailroom first. */
381 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
382 for (pos = 0; pos < (n & -2); pos += 2)
383 _mm_storeu_si128((__m128i *)&elts[pos],
384 _mm_loadu_si128((__m128i *)&pkts[pos]));
386 elts[pos] = pkts[pos];
387 /* Check if it crosses the end of the queue. */
388 if (unlikely(n < pkts_n)) {
389 elts = &(*txq->elts)[0];
390 for (pos = 0; pos < pkts_n - n; ++pos)
391 elts[pos] = pkts[n + pos];
393 txq->elts_head += pkts_n;
394 /* Save title WQEBB pointer. */
395 t_wqe = (__m128i *)wqe;
396 dseg = (__m128i *)(wqe + 1);
397 /* Calculate the number of entries to the end. */
399 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
402 txq_wr_dseg_v(txq, dseg, pkts, n);
403 /* Check if it crosses the end of the queue. */
405 dseg = (__m128i *)txq->wqes;
406 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
408 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
409 txq->elts_comp += pkts_n;
411 /* Request a completion. */
416 /* Fill CTRL in the header. */
417 ctrl = _mm_set_epi32(txq->elts_head, comp_req,
418 txq->qp_num_8s | (pkts_n + 2),
419 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
420 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW);
421 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
422 _mm_store_si128(t_wqe, ctrl);
423 /* Fill ESEG in the header. */
424 _mm_store_si128(t_wqe + 1,
425 _mm_set_epi8(0, 0, 0, 0,
429 #ifdef MLX5_PMD_SOFT_COUNTERS
430 txq->stats.opackets += pkts_n;
432 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
434 /* Ring QP doorbell. */
435 mlx5_tx_dbrec(txq, wqe);
440 * DPDK callback for vectorized TX.
443 * Generic pointer to TX queue structure.
445 * Packets to transmit.
447 * Number of packets in array.
450 * Number of packets successfully transmitted (<= pkts_n).
453 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
456 struct txq *txq = (struct txq *)dpdk_txq;
459 while (pkts_n > nb_tx) {
463 n = RTE_MIN((uint16_t)(pkts_n - nb_tx), MLX5_VPMD_TX_MAX_BURST);
464 ret = txq_burst_v(txq, &pkts[nb_tx], n, 0);
473 * DPDK callback for vectorized TX with multi-seg packets and offload.
476 * Generic pointer to TX queue structure.
478 * Packets to transmit.
480 * Number of packets in array.
483 * Number of packets successfully transmitted (<= pkts_n).
486 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
488 struct txq *txq = (struct txq *)dpdk_txq;
491 while (pkts_n > nb_tx) {
492 uint8_t cs_flags = 0;
496 /* Transmit multi-seg packets in the head of pkts list. */
497 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS) &&
498 NB_SEGS(pkts[nb_tx]) > 1)
499 nb_tx += txq_scatter_v(txq,
502 n = RTE_MIN((uint16_t)(pkts_n - nb_tx), MLX5_VPMD_TX_MAX_BURST);
503 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS))
504 n = txq_check_multiseg(&pkts[nb_tx], n);
505 if (!(txq->flags & ETH_TXQ_FLAGS_NOOFFLOADS))
506 n = txq_calc_offload(txq, &pkts[nb_tx], n, &cs_flags);
507 ret = txq_burst_v(txq, &pkts[nb_tx], n, cs_flags);
516 * Store free buffers to RX SW ring.
519 * Pointer to RX queue structure.
521 * Pointer to array of packets to be stored.
523 * Number of packets to be stored.
526 rxq_copy_mbuf_v(struct rxq *rxq, struct rte_mbuf **pkts, uint16_t n)
528 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
529 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
533 for (pos = 0; pos < p; pos += 2) {
536 mbp = _mm_loadu_si128((__m128i *)&elts[pos]);
537 _mm_storeu_si128((__m128i *)&pkts[pos], mbp);
540 pkts[pos] = elts[pos];
544 * Replenish buffers for RX in bulk.
547 * Pointer to RX queue structure.
549 * Number of buffers to be replenished.
552 rxq_replenish_bulk_mbuf(struct rxq *rxq, uint16_t n)
554 const uint16_t q_n = 1 << rxq->elts_n;
555 const uint16_t q_mask = q_n - 1;
556 const uint16_t elts_idx = rxq->rq_ci & q_mask;
557 struct rte_mbuf **elts = &(*rxq->elts)[elts_idx];
558 volatile struct mlx5_wqe_data_seg *wq = &(*rxq->wqes)[elts_idx];
561 assert(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH);
562 assert(n <= (uint16_t)(q_n - (rxq->rq_ci - rxq->rq_pi)));
563 assert(MLX5_VPMD_RXQ_RPLNSH_THRESH > MLX5_VPMD_DESCS_PER_LOOP);
564 /* Not to cross queue end. */
565 n = RTE_MIN(n - MLX5_VPMD_DESCS_PER_LOOP, q_n - elts_idx);
566 if (rte_mempool_get_bulk(rxq->mp, (void *)elts, n) < 0) {
567 rxq->stats.rx_nombuf += n;
570 for (i = 0; i < n; ++i)
571 wq[i].addr = htonll((uintptr_t)elts[i]->buf_addr +
572 RTE_PKTMBUF_HEADROOM);
575 *rxq->rq_db = htonl(rxq->rq_ci);
579 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
580 * extracted from the title completion descriptor.
583 * Pointer to RX queue structure.
585 * Pointer to completion array having a compressed completion at first.
587 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
588 * the title completion descriptor to be copied to the rest of mbufs.
591 rxq_cq_decompress_v(struct rxq *rxq,
592 volatile struct mlx5_cqe *cq,
593 struct rte_mbuf **elts)
595 volatile struct mlx5_mini_cqe8 *mcq = (void *)(cq + 1);
596 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
599 unsigned int inv = 0;
600 /* Mask to shuffle from extracted mini CQE to mbuf. */
601 const __m128i shuf_mask1 =
602 _mm_set_epi8(0, 1, 2, 3, /* rss, bswap32 */
603 -1, -1, /* skip vlan_tci */
604 6, 7, /* data_len, bswap16 */
605 -1, -1, 6, 7, /* pkt_len, bswap16 */
606 -1, -1, -1, -1 /* skip packet_type */);
607 const __m128i shuf_mask2 =
608 _mm_set_epi8(8, 9, 10, 11, /* rss, bswap32 */
609 -1, -1, /* skip vlan_tci */
610 14, 15, /* data_len, bswap16 */
611 -1, -1, 14, 15, /* pkt_len, bswap16 */
612 -1, -1, -1, -1 /* skip packet_type */);
613 /* Restore the compressed count. Must be 16 bits. */
614 const uint16_t mcqe_n = t_pkt->data_len +
615 (rxq->crc_present * ETHER_CRC_LEN);
616 const __m128i rearm =
617 _mm_loadu_si128((__m128i *)&t_pkt->rearm_data);
619 _mm_loadu_si128((__m128i *)&t_pkt->rx_descriptor_fields1);
620 const __m128i crc_adj =
621 _mm_set_epi16(0, 0, 0,
622 rxq->crc_present * ETHER_CRC_LEN,
624 rxq->crc_present * ETHER_CRC_LEN,
626 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
627 #ifdef MLX5_PMD_SOFT_COUNTERS
628 const __m128i zero = _mm_setzero_si128();
629 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
630 uint32_t rcvd_byte = 0;
631 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
632 const __m128i len_shuf_mask =
633 _mm_set_epi8(-1, -1, -1, -1,
639 /* Compile time sanity check for this function. */
640 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
641 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
642 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
643 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
644 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
645 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
647 * A. load mCQEs into a 128bit register.
648 * B. store rearm data to mbuf.
649 * C. combine data from mCQEs with rx_descriptor_fields1.
650 * D. store rx_descriptor_fields1.
651 * E. store flow tag (rte_flow mark).
653 for (pos = 0; pos < mcqe_n; ) {
654 __m128i mcqe1, mcqe2;
655 __m128i rxdf1, rxdf2;
656 #ifdef MLX5_PMD_SOFT_COUNTERS
657 __m128i byte_cnt, invalid_mask;
660 if (!(pos & 0x7) && pos + 8 < mcqe_n)
661 rte_prefetch0((void *)(cq + pos + 8));
662 /* A.1 load mCQEs into a 128bit register. */
663 mcqe1 = _mm_loadu_si128((__m128i *)&mcq[pos % 8]);
664 mcqe2 = _mm_loadu_si128((__m128i *)&mcq[pos % 8 + 2]);
665 /* B.1 store rearm data to mbuf. */
666 _mm_storeu_si128((__m128i *)&elts[pos]->rearm_data, rearm);
667 _mm_storeu_si128((__m128i *)&elts[pos + 1]->rearm_data, rearm);
668 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
669 rxdf1 = _mm_shuffle_epi8(mcqe1, shuf_mask1);
670 rxdf2 = _mm_shuffle_epi8(mcqe1, shuf_mask2);
671 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
672 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
673 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
674 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
675 /* D.1 store rx_descriptor_fields1. */
676 _mm_storeu_si128((__m128i *)
677 &elts[pos]->rx_descriptor_fields1,
679 _mm_storeu_si128((__m128i *)
680 &elts[pos + 1]->rx_descriptor_fields1,
682 /* B.1 store rearm data to mbuf. */
683 _mm_storeu_si128((__m128i *)&elts[pos + 2]->rearm_data, rearm);
684 _mm_storeu_si128((__m128i *)&elts[pos + 3]->rearm_data, rearm);
685 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
686 rxdf1 = _mm_shuffle_epi8(mcqe2, shuf_mask1);
687 rxdf2 = _mm_shuffle_epi8(mcqe2, shuf_mask2);
688 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
689 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
690 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
691 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
692 /* D.1 store rx_descriptor_fields1. */
693 _mm_storeu_si128((__m128i *)
694 &elts[pos + 2]->rx_descriptor_fields1,
696 _mm_storeu_si128((__m128i *)
697 &elts[pos + 3]->rx_descriptor_fields1,
699 #ifdef MLX5_PMD_SOFT_COUNTERS
700 invalid_mask = _mm_set_epi64x(0,
702 sizeof(uint16_t) * 8);
703 invalid_mask = _mm_sll_epi64(ones, invalid_mask);
704 mcqe1 = _mm_srli_si128(mcqe1, 4);
705 byte_cnt = _mm_blend_epi16(mcqe1, mcqe2, 0xcc);
706 byte_cnt = _mm_shuffle_epi8(byte_cnt, len_shuf_mask);
707 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
708 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
709 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
712 /* E.1 store flow tag (rte_flow mark). */
713 elts[pos]->hash.fdir.hi = flow_tag;
714 elts[pos + 1]->hash.fdir.hi = flow_tag;
715 elts[pos + 2]->hash.fdir.hi = flow_tag;
716 elts[pos + 3]->hash.fdir.hi = flow_tag;
718 pos += MLX5_VPMD_DESCS_PER_LOOP;
719 /* Move to next CQE and invalidate consumed CQEs. */
720 if (!(pos & 0x7) && pos < mcqe_n) {
721 mcq = (void *)(cq + pos);
722 for (i = 0; i < 8; ++i)
723 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
726 /* Invalidate the rest of CQEs. */
727 for (; inv < mcqe_n; ++inv)
728 cq[inv].op_own = MLX5_CQE_INVALIDATE;
729 #ifdef MLX5_PMD_SOFT_COUNTERS
730 rxq->stats.ipackets += mcqe_n;
731 rxq->stats.ibytes += rcvd_byte;
733 rxq->cq_ci += mcqe_n;
737 * Calculate packet type and offload flag for mbuf and store it.
740 * Pointer to RX queue structure.
742 * Array of four 16bytes completions extracted from the original completion
745 * Opcode vector having responder error status. Each field is 4B.
747 * Pointer to array of packets to be filled.
750 rxq_cq_to_ptype_oflags_v(struct rxq *rxq, __m128i cqes[4], __m128i op_err,
751 struct rte_mbuf **pkts)
753 __m128i pinfo0, pinfo1;
754 __m128i pinfo, ptype;
755 __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH);
757 const __m128i zero = _mm_setzero_si128();
758 const __m128i ptype_mask =
759 _mm_set_epi32(0xfd06, 0xfd06, 0xfd06, 0xfd06);
760 const __m128i ptype_ol_mask =
761 _mm_set_epi32(0x106, 0x106, 0x106, 0x106);
762 const __m128i pinfo_mask =
763 _mm_set_epi32(0x3, 0x3, 0x3, 0x3);
764 const __m128i cv_flag_sel =
765 _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
766 (uint8_t)((PKT_RX_IP_CKSUM_GOOD |
767 PKT_RX_L4_CKSUM_GOOD) >> 1),
769 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
771 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
772 (uint8_t)(PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED),
774 const __m128i cv_mask =
775 _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
776 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
777 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
778 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
779 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
780 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
781 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
782 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED);
783 const __m128i mbuf_init =
784 _mm_loadl_epi64((__m128i *)&rxq->mbuf_initializer);
785 __m128i rearm0, rearm1, rearm2, rearm3;
787 /* Extract pkt_info field. */
788 pinfo0 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
789 pinfo1 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
790 pinfo = _mm_unpacklo_epi64(pinfo0, pinfo1);
791 /* Extract hdr_type_etc field. */
792 pinfo0 = _mm_unpackhi_epi32(cqes[0], cqes[1]);
793 pinfo1 = _mm_unpackhi_epi32(cqes[2], cqes[3]);
794 ptype = _mm_unpacklo_epi64(pinfo0, pinfo1);
796 const __m128i pinfo_ft_mask =
797 _mm_set_epi32(0xffffff00, 0xffffff00,
798 0xffffff00, 0xffffff00);
799 const __m128i fdir_flags = _mm_set1_epi32(PKT_RX_FDIR);
800 const __m128i fdir_id_flags = _mm_set1_epi32(PKT_RX_FDIR_ID);
801 __m128i flow_tag, invalid_mask;
803 flow_tag = _mm_and_si128(pinfo, pinfo_ft_mask);
804 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
805 invalid_mask = _mm_cmpeq_epi32(flow_tag, zero);
806 ol_flags = _mm_or_si128(ol_flags,
807 _mm_andnot_si128(invalid_mask,
809 /* Mask out invalid entries. */
810 flow_tag = _mm_andnot_si128(invalid_mask, flow_tag);
811 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
812 ol_flags = _mm_or_si128(ol_flags,
814 _mm_cmpeq_epi32(flow_tag,
819 * Merge the two fields to generate the following:
823 * bit[11:10] = l3_hdr_type
824 * bit[14:12] = l4_hdr_type
827 * bit[17] = outer_l3_type
829 ptype = _mm_and_si128(ptype, ptype_mask);
830 pinfo = _mm_and_si128(pinfo, pinfo_mask);
831 pinfo = _mm_slli_epi32(pinfo, 16);
832 /* Make pinfo has merged fields for ol_flags calculation. */
833 pinfo = _mm_or_si128(ptype, pinfo);
834 ptype = _mm_srli_epi32(pinfo, 10);
835 ptype = _mm_packs_epi32(ptype, zero);
836 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
837 op_err = _mm_srli_epi16(op_err, 8);
838 ptype = _mm_or_si128(ptype, op_err);
839 pkts[0]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 0)];
840 pkts[1]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 2)];
841 pkts[2]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 4)];
842 pkts[3]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 6)];
843 /* Fill flags for checksum and VLAN. */
844 pinfo = _mm_and_si128(pinfo, ptype_ol_mask);
845 pinfo = _mm_shuffle_epi8(cv_flag_sel, pinfo);
846 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
847 cv_flags = _mm_slli_epi32(pinfo, 9);
848 cv_flags = _mm_or_si128(pinfo, cv_flags);
849 /* Move back flags to start from byte[0]. */
850 cv_flags = _mm_srli_epi32(cv_flags, 8);
851 /* Mask out garbage bits. */
852 cv_flags = _mm_and_si128(cv_flags, cv_mask);
853 /* Merge to ol_flags. */
854 ol_flags = _mm_or_si128(ol_flags, cv_flags);
855 /* Merge mbuf_init and ol_flags. */
856 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
857 offsetof(struct rte_mbuf, rearm_data) + 8);
858 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 8), 0x30);
859 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 4), 0x30);
860 rearm2 = _mm_blend_epi16(mbuf_init, ol_flags, 0x30);
861 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(ol_flags, 4), 0x30);
862 /* Write 8B rearm_data and 8B ol_flags. */
863 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
864 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
865 _mm_store_si128((__m128i *)&pkts[0]->rearm_data, rearm0);
866 _mm_store_si128((__m128i *)&pkts[1]->rearm_data, rearm1);
867 _mm_store_si128((__m128i *)&pkts[2]->rearm_data, rearm2);
868 _mm_store_si128((__m128i *)&pkts[3]->rearm_data, rearm3);
872 * Skip error packets.
875 * Pointer to RX queue structure.
877 * Array to store received packets.
879 * Maximum number of packets in array.
882 * Number of packets successfully received (<= pkts_n).
885 rxq_handle_pending_error(struct rxq *rxq, struct rte_mbuf **pkts,
891 for (i = 0; i < pkts_n; ++i) {
892 struct rte_mbuf *pkt = pkts[i];
894 if (pkt->packet_type == RTE_PTYPE_ALL_MASK)
895 rte_pktmbuf_free_seg(pkt);
899 rxq->stats.idropped += (pkts_n - n);
900 rxq->pending_err = 0;
905 * Receive burst of packets. An errored completion also consumes a mbuf, but the
906 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
907 * before returning to application.
910 * Pointer to RX queue structure.
912 * Array to store received packets.
914 * Maximum number of packets in array.
917 * Number of packets received including errors (<= pkts_n).
919 static inline uint16_t
920 rxq_burst_v(struct rxq *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
922 const uint16_t q_n = 1 << rxq->cqe_n;
923 const uint16_t q_mask = q_n - 1;
924 volatile struct mlx5_cqe *cq;
925 struct rte_mbuf **elts;
929 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
930 uint16_t nocmp_n = 0;
931 uint16_t rcvd_pkt = 0;
932 unsigned int cq_idx = rxq->cq_ci & q_mask;
933 unsigned int elts_idx;
934 unsigned int ownership = !!(rxq->cq_ci & (q_mask + 1));
935 const __m128i owner_check =
936 _mm_set_epi64x(0x0100000001000000LL, 0x0100000001000000LL);
937 const __m128i opcode_check =
938 _mm_set_epi64x(0xf0000000f0000000LL, 0xf0000000f0000000LL);
939 const __m128i format_check =
940 _mm_set_epi64x(0x0c0000000c000000LL, 0x0c0000000c000000LL);
941 const __m128i resp_err_check =
942 _mm_set_epi64x(0xe0000000e0000000LL, 0xe0000000e0000000LL);
943 #ifdef MLX5_PMD_SOFT_COUNTERS
944 uint32_t rcvd_byte = 0;
945 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
946 const __m128i len_shuf_mask =
947 _mm_set_epi8(-1, -1, -1, -1,
952 /* Mask to shuffle from extracted CQE to mbuf. */
953 const __m128i shuf_mask =
954 _mm_set_epi8(-1, 3, 2, 1, /* fdir.hi */
955 12, 13, 14, 15, /* rss, bswap32 */
956 10, 11, /* vlan_tci, bswap16 */
957 4, 5, /* data_len, bswap16 */
958 -1, -1, /* zero out 2nd half of pkt_len */
959 4, 5 /* pkt_len, bswap16 */);
960 /* Mask to blend from the last Qword to the first DQword. */
961 const __m128i blend_mask =
962 _mm_set_epi8(-1, -1, -1, -1,
966 const __m128i zero = _mm_setzero_si128();
967 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
968 const __m128i crc_adj =
969 _mm_set_epi16(0, 0, 0, 0, 0,
970 rxq->crc_present * ETHER_CRC_LEN,
972 rxq->crc_present * ETHER_CRC_LEN);
973 const __m128i flow_mark_adj = _mm_set_epi32(rxq->mark * (-1), 0, 0, 0);
975 /* Compile time sanity check for this function. */
976 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
977 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
978 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
979 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
980 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, pkt_info) != 0);
981 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rx_hash_res) !=
982 offsetof(struct mlx5_cqe, pkt_info) + 12);
983 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rsvd1) +
984 sizeof(((struct mlx5_cqe *)0)->rsvd1) !=
985 offsetof(struct mlx5_cqe, hdr_type_etc));
986 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, vlan_info) !=
987 offsetof(struct mlx5_cqe, hdr_type_etc) + 2);
988 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rsvd2) +
989 sizeof(((struct mlx5_cqe *)0)->rsvd2) !=
990 offsetof(struct mlx5_cqe, byte_cnt));
991 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, sop_drop_qpn) !=
992 RTE_ALIGN(offsetof(struct mlx5_cqe, sop_drop_qpn), 8));
993 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, op_own) !=
994 offsetof(struct mlx5_cqe, sop_drop_qpn) + 7);
995 assert(rxq->sges_n == 0);
996 assert(rxq->cqe_n == rxq->elts_n);
997 cq = &(*rxq->cqes)[cq_idx];
999 rte_prefetch0(cq + 1);
1000 rte_prefetch0(cq + 2);
1001 rte_prefetch0(cq + 3);
1002 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
1005 * rq_ci >= cq_ci >= rq_pi
1006 * Definition of indexes:
1007 * rq_ci - cq_ci := # of buffers owned by HW (posted).
1008 * cq_ci - rq_pi := # of buffers not returned to app (decompressed).
1009 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished).
1011 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
1012 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH)
1013 rxq_replenish_bulk_mbuf(rxq, repl_n);
1014 /* See if there're unreturned mbufs from compressed CQE. */
1015 rcvd_pkt = rxq->cq_ci - rxq->rq_pi;
1017 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
1018 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
1019 rxq->rq_pi += rcvd_pkt;
1022 elts_idx = rxq->rq_pi & q_mask;
1023 elts = &(*rxq->elts)[elts_idx];
1024 /* Not to overflow pkts array. */
1025 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
1026 /* Not to cross queue end. */
1027 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
1030 /* At this point, there shouldn't be any remained packets. */
1031 assert(rxq->rq_pi == rxq->cq_ci);
1033 * A. load first Qword (8bytes) in one loop.
1034 * B. copy 4 mbuf pointers from elts ring to returing pkts.
1035 * C. load remained CQE data and extract necessary fields.
1036 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
1037 * following structure:
1040 * uint8_t flow_tag[3];
1041 * uint16_t byte_cnt;
1044 * uint16_t hdr_type_etc;
1045 * uint16_t vlan_info;
1046 * uint32_t rx_has_res;
1049 * E. get valid CQEs.
1050 * F. find compressed CQE.
1054 pos += MLX5_VPMD_DESCS_PER_LOOP) {
1055 __m128i cqes[MLX5_VPMD_DESCS_PER_LOOP];
1056 __m128i cqe_tmp1, cqe_tmp2;
1057 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
1058 __m128i op_own, op_own_tmp1, op_own_tmp2;
1059 __m128i opcode, owner_mask, invalid_mask;
1062 #ifdef MLX5_PMD_SOFT_COUNTERS
1066 __m128i p = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0);
1067 unsigned int p1, p2, p3;
1069 /* Prefetch next 4 CQEs. */
1070 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
1071 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP]);
1072 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 1]);
1073 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 2]);
1074 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 3]);
1076 /* A.0 do not cross the end of CQ. */
1077 mask = _mm_set_epi64x(0, (pkts_n - pos) * sizeof(uint16_t) * 8);
1078 mask = _mm_sll_epi64(ones, mask);
1079 p = _mm_andnot_si128(mask, p);
1080 /* A.1 load cqes. */
1081 p3 = _mm_extract_epi16(p, 3);
1082 cqes[3] = _mm_loadl_epi64((__m128i *)
1083 &cq[pos + p3].sop_drop_qpn);
1084 rte_compiler_barrier();
1085 p2 = _mm_extract_epi16(p, 2);
1086 cqes[2] = _mm_loadl_epi64((__m128i *)
1087 &cq[pos + p2].sop_drop_qpn);
1088 rte_compiler_barrier();
1089 /* B.1 load mbuf pointers. */
1090 mbp1 = _mm_loadu_si128((__m128i *)&elts[pos]);
1091 mbp2 = _mm_loadu_si128((__m128i *)&elts[pos + 2]);
1092 /* A.1 load a block having op_own. */
1093 p1 = _mm_extract_epi16(p, 1);
1094 cqes[1] = _mm_loadl_epi64((__m128i *)
1095 &cq[pos + p1].sop_drop_qpn);
1096 rte_compiler_barrier();
1097 cqes[0] = _mm_loadl_epi64((__m128i *)
1098 &cq[pos].sop_drop_qpn);
1099 /* B.2 copy mbuf pointers. */
1100 _mm_storeu_si128((__m128i *)&pkts[pos], mbp1);
1101 _mm_storeu_si128((__m128i *)&pkts[pos + 2], mbp2);
1102 rte_compiler_barrier();
1103 /* C.1 load remained CQE data and extract necessary fields. */
1104 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p3]);
1105 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos + p2]);
1106 cqes[3] = _mm_blendv_epi8(cqes[3], cqe_tmp2, blend_mask);
1107 cqes[2] = _mm_blendv_epi8(cqes[2], cqe_tmp1, blend_mask);
1108 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p3].rsvd1[3]);
1109 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos + p2].rsvd1[3]);
1110 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x30);
1111 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x30);
1112 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p3].rsvd2[10]);
1113 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos + p2].rsvd2[10]);
1114 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x04);
1115 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x04);
1116 /* C.2 generate final structure for mbuf with swapping bytes. */
1117 pkt_mb3 = _mm_shuffle_epi8(cqes[3], shuf_mask);
1118 pkt_mb2 = _mm_shuffle_epi8(cqes[2], shuf_mask);
1119 /* C.3 adjust CRC length. */
1120 pkt_mb3 = _mm_sub_epi16(pkt_mb3, crc_adj);
1121 pkt_mb2 = _mm_sub_epi16(pkt_mb2, crc_adj);
1122 /* C.4 adjust flow mark. */
1123 pkt_mb3 = _mm_add_epi32(pkt_mb3, flow_mark_adj);
1124 pkt_mb2 = _mm_add_epi32(pkt_mb2, flow_mark_adj);
1125 /* D.1 fill in mbuf - rx_descriptor_fields1. */
1126 _mm_storeu_si128((void *)&pkts[pos + 3]->pkt_len, pkt_mb3);
1127 _mm_storeu_si128((void *)&pkts[pos + 2]->pkt_len, pkt_mb2);
1128 /* E.1 extract op_own field. */
1129 op_own_tmp2 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
1130 /* C.1 load remained CQE data and extract necessary fields. */
1131 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p1]);
1132 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos]);
1133 cqes[1] = _mm_blendv_epi8(cqes[1], cqe_tmp2, blend_mask);
1134 cqes[0] = _mm_blendv_epi8(cqes[0], cqe_tmp1, blend_mask);
1135 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p1].rsvd1[3]);
1136 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos].rsvd1[3]);
1137 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x30);
1138 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x30);
1139 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p1].rsvd2[10]);
1140 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos].rsvd2[10]);
1141 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x04);
1142 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x04);
1143 /* C.2 generate final structure for mbuf with swapping bytes. */
1144 pkt_mb1 = _mm_shuffle_epi8(cqes[1], shuf_mask);
1145 pkt_mb0 = _mm_shuffle_epi8(cqes[0], shuf_mask);
1146 /* C.3 adjust CRC length. */
1147 pkt_mb1 = _mm_sub_epi16(pkt_mb1, crc_adj);
1148 pkt_mb0 = _mm_sub_epi16(pkt_mb0, crc_adj);
1149 /* C.4 adjust flow mark. */
1150 pkt_mb1 = _mm_add_epi32(pkt_mb1, flow_mark_adj);
1151 pkt_mb0 = _mm_add_epi32(pkt_mb0, flow_mark_adj);
1152 /* E.1 extract op_own byte. */
1153 op_own_tmp1 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
1154 op_own = _mm_unpackhi_epi64(op_own_tmp1, op_own_tmp2);
1155 /* D.1 fill in mbuf - rx_descriptor_fields1. */
1156 _mm_storeu_si128((void *)&pkts[pos + 1]->pkt_len, pkt_mb1);
1157 _mm_storeu_si128((void *)&pkts[pos]->pkt_len, pkt_mb0);
1158 /* E.2 flip owner bit to mark CQEs from last round. */
1159 owner_mask = _mm_and_si128(op_own, owner_check);
1161 owner_mask = _mm_xor_si128(owner_mask, owner_check);
1162 owner_mask = _mm_cmpeq_epi32(owner_mask, owner_check);
1163 owner_mask = _mm_packs_epi32(owner_mask, zero);
1164 /* E.3 get mask for invalidated CQEs. */
1165 opcode = _mm_and_si128(op_own, opcode_check);
1166 invalid_mask = _mm_cmpeq_epi32(opcode_check, opcode);
1167 invalid_mask = _mm_packs_epi32(invalid_mask, zero);
1168 /* E.4 mask out beyond boundary. */
1169 invalid_mask = _mm_or_si128(invalid_mask, mask);
1170 /* E.5 merge invalid_mask with invalid owner. */
1171 invalid_mask = _mm_or_si128(invalid_mask, owner_mask);
1172 /* F.1 find compressed CQE format. */
1173 comp_mask = _mm_and_si128(op_own, format_check);
1174 comp_mask = _mm_cmpeq_epi32(comp_mask, format_check);
1175 comp_mask = _mm_packs_epi32(comp_mask, zero);
1176 /* F.2 mask out invalid entries. */
1177 comp_mask = _mm_andnot_si128(invalid_mask, comp_mask);
1178 comp_idx = _mm_cvtsi128_si64(comp_mask);
1179 /* F.3 get the first compressed CQE. */
1180 comp_idx = comp_idx ?
1181 __builtin_ctzll(comp_idx) /
1182 (sizeof(uint16_t) * 8) :
1183 MLX5_VPMD_DESCS_PER_LOOP;
1184 /* E.6 mask out entries after the compressed CQE. */
1185 mask = _mm_set_epi64x(0, comp_idx * sizeof(uint16_t) * 8);
1186 mask = _mm_sll_epi64(ones, mask);
1187 invalid_mask = _mm_or_si128(invalid_mask, mask);
1188 /* E.7 count non-compressed valid CQEs. */
1189 n = _mm_cvtsi128_si64(invalid_mask);
1190 n = n ? __builtin_ctzll(n) / (sizeof(uint16_t) * 8) :
1191 MLX5_VPMD_DESCS_PER_LOOP;
1193 /* D.2 get the final invalid mask. */
1194 mask = _mm_set_epi64x(0, n * sizeof(uint16_t) * 8);
1195 mask = _mm_sll_epi64(ones, mask);
1196 invalid_mask = _mm_or_si128(invalid_mask, mask);
1197 /* D.3 check error in opcode. */
1198 opcode = _mm_cmpeq_epi32(resp_err_check, opcode);
1199 opcode = _mm_packs_epi32(opcode, zero);
1200 opcode = _mm_andnot_si128(invalid_mask, opcode);
1201 /* D.4 mark if any error is set */
1202 rxq->pending_err |= !!_mm_cvtsi128_si64(opcode);
1203 /* D.5 fill in mbuf - rearm_data and packet_type. */
1204 rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
1205 #ifdef MLX5_PMD_SOFT_COUNTERS
1206 /* Add up received bytes count. */
1207 byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);
1208 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
1209 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
1210 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
1213 * Break the loop unless more valid CQE is expected, or if
1214 * there's a compressed CQE.
1216 if (n != MLX5_VPMD_DESCS_PER_LOOP)
1219 /* If no new CQE seen, return without updating cq_db. */
1220 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
1222 /* Update the consumer indexes for non-compressed CQEs. */
1223 assert(nocmp_n <= pkts_n);
1224 rxq->cq_ci += nocmp_n;
1225 rxq->rq_pi += nocmp_n;
1226 rcvd_pkt += nocmp_n;
1227 #ifdef MLX5_PMD_SOFT_COUNTERS
1228 rxq->stats.ipackets += nocmp_n;
1229 rxq->stats.ibytes += rcvd_byte;
1231 /* Decompress the last CQE if compressed. */
1232 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
1233 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
1234 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);
1235 /* Return more packets if needed. */
1236 if (nocmp_n < pkts_n) {
1237 uint16_t n = rxq->cq_ci - rxq->rq_pi;
1239 n = RTE_MIN(n, pkts_n - nocmp_n);
1240 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
1246 *rxq->cq_db = htonl(rxq->cq_ci);
1251 * DPDK callback for vectorized RX.
1254 * Generic pointer to RX queue structure.
1256 * Array to store received packets.
1258 * Maximum number of packets in array.
1261 * Number of packets successfully received (<= pkts_n).
1264 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1266 struct rxq *rxq = dpdk_rxq;
1269 nb_rx = rxq_burst_v(rxq, pkts, pkts_n);
1270 if (unlikely(rxq->pending_err))
1271 nb_rx = rxq_handle_pending_error(rxq, pkts, nb_rx);
1276 * Check Tx queue flags are set for raw vectorized Tx.
1279 * Pointer to private structure.
1282 * 1 if supported, negative errno value if not.
1284 int __attribute__((cold))
1285 priv_check_raw_vec_tx_support(struct priv *priv)
1289 /* All the configured queues should support. */
1290 for (i = 0; i < priv->txqs_n; ++i) {
1291 struct txq *txq = (*priv->txqs)[i];
1293 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS) ||
1294 !(txq->flags & ETH_TXQ_FLAGS_NOOFFLOADS))
1297 if (i != priv->txqs_n)
1303 * Check a device can support vectorized TX.
1306 * Pointer to private structure.
1309 * 1 if supported, negative errno value if not.
1311 int __attribute__((cold))
1312 priv_check_vec_tx_support(struct priv *priv)
1314 if (priv->txqs_n > MLX5_VPMD_MIN_TXQS ||
1315 priv->mps != MLX5_MPW_ENHANCED ||
1322 * Check a RX queue can support vectorized RX.
1325 * Pointer to RX queue.
1328 * 1 if supported, negative errno value if not.
1330 int __attribute__((cold))
1331 rxq_check_vec_support(struct rxq *rxq)
1333 if (rxq->sges_n != 0)
1339 * Check a device can support vectorized RX.
1342 * Pointer to private structure.
1345 * 1 if supported, negative errno value if not.
1347 int __attribute__((cold))
1348 priv_check_vec_rx_support(struct priv *priv)
1352 /* All the configured queues should support. */
1353 for (i = 0; i < priv->rxqs_n; ++i) {
1354 struct rxq *rxq = (*priv->rxqs)[i];
1356 if (rxq_check_vec_support(rxq) < 0)
1359 if (i != priv->rxqs_n)
1365 * Prepare for vectorized RX.
1368 * Pointer to private structure.
1371 priv_prep_vec_rx_function(struct priv *priv)
1375 for (i = 0; i < priv->rxqs_n; ++i) {
1376 struct rxq *rxq = (*priv->rxqs)[i];
1377 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
1378 const uint16_t desc = 1 << rxq->elts_n;
1381 assert(rxq->elts_n == rxq->cqe_n);
1382 /* Initialize default rearm_data for vPMD. */
1383 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
1384 rte_mbuf_refcnt_set(mbuf_init, 1);
1385 mbuf_init->nb_segs = 1;
1386 mbuf_init->port = rxq->port_id;
1388 * prevent compiler reordering:
1389 * rearm_data covers previous fields.
1391 rte_compiler_barrier();
1392 rxq->mbuf_initializer =
1393 *(uint64_t *)&mbuf_init->rearm_data;
1394 /* Padding with a fake mbuf for vectorized Rx. */
1395 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
1396 (*rxq->elts)[desc + j] = &rxq->fake_mbuf;
1397 /* Mark that it need to be cleaned up for rxq_alloc_elts(). */