4 * Copyright 2017 6WIND S.A.
5 * Copyright 2017 Mellanox.
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8 * modification, are permitted provided that the following conditions
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38 #include <smmintrin.h>
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
46 #include <infiniband/mlx5_hw.h>
47 #include <infiniband/arch.h>
49 #pragma GCC diagnostic error "-Wpedantic"
52 /* DPDK headers don't like -pedantic. */
54 #pragma GCC diagnostic ignored "-Wpedantic"
57 #include <rte_mempool.h>
58 #include <rte_prefetch.h>
60 #pragma GCC diagnostic error "-Wpedantic"
64 #include "mlx5_utils.h"
65 #include "mlx5_rxtx.h"
66 #include "mlx5_autoconf.h"
67 #include "mlx5_defs.h"
70 #ifndef __INTEL_COMPILER
71 #pragma GCC diagnostic ignored "-Wcast-qual"
75 * Fill in buffer descriptors in a multi-packet send descriptor.
78 * Pointer to TX queue structure.
80 * Pointer to buffer descriptor to be writen.
82 * Pointer to array of packets to be sent.
84 * Number of packets to be filled.
87 txq_wr_dseg_v(struct txq *txq, __m128i *dseg,
88 struct rte_mbuf **pkts, unsigned int n)
92 const __m128i shuf_mask_dseg =
93 _mm_set_epi8(8, 9, 10, 11, /* addr, bswap64 */
95 7, 6, 5, 4, /* lkey */
96 0, 1, 2, 3 /* length, bswap32 */);
97 #ifdef MLX5_PMD_SOFT_COUNTERS
101 for (pos = 0; pos < n; ++pos, ++dseg) {
103 struct rte_mbuf *pkt = pkts[pos];
105 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
106 desc = _mm_set_epi32(addr >> 32,
108 mlx5_tx_mb2mr(txq, pkt),
110 desc = _mm_shuffle_epi8(desc, shuf_mask_dseg);
111 _mm_store_si128(dseg, desc);
112 #ifdef MLX5_PMD_SOFT_COUNTERS
113 tx_byte += DATA_LEN(pkt);
116 #ifdef MLX5_PMD_SOFT_COUNTERS
117 txq->stats.obytes += tx_byte;
122 * Count the number of continuous single segment packets. The first packet must
123 * be a single segment packet.
126 * Pointer to array of packets.
131 * Number of continuous single segment packets.
133 static inline unsigned int
134 txq_check_multiseg(struct rte_mbuf **pkts, uint16_t pkts_n)
140 assert(NB_SEGS(pkts[0]) == 1);
141 /* Count the number of continuous single segment packets. */
142 for (pos = 1; pos < pkts_n; ++pos)
143 if (NB_SEGS(pkts[pos]) > 1)
149 * Count the number of packets having same ol_flags and calculate cs_flags.
152 * Pointer to TX queue structure.
154 * Pointer to array of packets.
158 * Pointer of flags to be returned.
161 * Number of packets having same ol_flags.
163 static inline unsigned int
164 txq_calc_offload(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
168 const uint64_t ol_mask =
169 PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM |
170 PKT_TX_UDP_CKSUM | PKT_TX_TUNNEL_GRE |
171 PKT_TX_TUNNEL_VXLAN | PKT_TX_OUTER_IP_CKSUM;
175 /* Count the number of packets having same ol_flags. */
176 for (pos = 1; pos < pkts_n; ++pos)
177 if ((pkts[pos]->ol_flags ^ pkts[0]->ol_flags) & ol_mask)
179 /* Should open another MPW session for the rest. */
180 if (pkts[0]->ol_flags &
181 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
182 const uint64_t is_tunneled =
185 PKT_TX_TUNNEL_VXLAN);
187 if (is_tunneled && txq->tunnel_en) {
188 *cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
189 MLX5_ETH_WQE_L4_INNER_CSUM;
190 if (pkts[0]->ol_flags & PKT_TX_OUTER_IP_CKSUM)
191 *cs_flags |= MLX5_ETH_WQE_L3_CSUM;
193 *cs_flags = MLX5_ETH_WQE_L3_CSUM |
194 MLX5_ETH_WQE_L4_CSUM;
201 * Send multi-segmented packets until it encounters a single segment packet in
205 * Pointer to TX queue structure.
207 * Pointer to array of packets to be sent.
209 * Number of packets to be sent.
212 * Number of packets successfully transmitted (<= pkts_n).
215 txq_scatter_v(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n)
217 uint16_t elts_head = txq->elts_head;
218 const uint16_t elts_n = 1 << txq->elts_n;
219 const uint16_t elts_m = elts_n - 1;
220 const uint16_t wq_n = 1 << txq->wqe_n;
221 const uint16_t wq_mask = wq_n - 1;
222 const unsigned int nb_dword_per_wqebb =
223 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
224 const unsigned int nb_dword_in_hdr =
225 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
227 volatile struct mlx5_wqe *wqe = NULL;
229 assert(elts_n > pkts_n);
230 mlx5_tx_complete(txq);
231 if (unlikely(!pkts_n))
233 for (n = 0; n < pkts_n; ++n) {
234 struct rte_mbuf *buf = pkts[n];
235 unsigned int segs_n = buf->nb_segs;
236 unsigned int ds = nb_dword_in_hdr;
237 unsigned int len = PKT_LEN(buf);
238 uint16_t wqe_ci = txq->wqe_ci;
239 const __m128i shuf_mask_ctrl =
240 _mm_set_epi8(15, 14, 13, 12,
241 8, 9, 10, 11, /* bswap32 */
242 4, 5, 6, 7, /* bswap32 */
243 0, 1, 2, 3 /* bswap32 */);
244 uint8_t cs_flags = 0;
247 __m128i *t_wqe, *dseg;
251 max_elts = elts_n - (elts_head - txq->elts_tail);
252 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
254 * A MPW session consumes 2 WQEs at most to
255 * include MLX5_MPW_DSEG_MAX pointers.
258 max_elts < segs_n || max_wqe < 2)
260 wqe = &((volatile struct mlx5_wqe64 *)
261 txq->wqes)[wqe_ci & wq_mask].hdr;
263 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
264 const uint64_t is_tunneled = buf->ol_flags &
266 PKT_TX_TUNNEL_VXLAN);
268 if (is_tunneled && txq->tunnel_en) {
269 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
270 MLX5_ETH_WQE_L4_INNER_CSUM;
271 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
272 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
274 cs_flags = MLX5_ETH_WQE_L3_CSUM |
275 MLX5_ETH_WQE_L4_CSUM;
278 /* Title WQEBB pointer. */
279 t_wqe = (__m128i *)wqe;
280 dseg = (__m128i *)(wqe + 1);
282 if (!(ds++ % nb_dword_per_wqebb)) {
284 &((volatile struct mlx5_wqe64 *)
285 txq->wqes)[++wqe_ci & wq_mask];
287 txq_wr_dseg_v(txq, dseg++, &buf, 1);
288 (*txq->elts)[elts_head++ & elts_m] = buf;
291 if (ds % nb_dword_per_wqebb)
293 /* Fill CTRL in the header. */
294 ctrl = _mm_set_epi32(0, 0, txq->qp_num_8s | ds,
295 MLX5_OPC_MOD_MPW << 24 |
296 txq->wqe_ci << 8 | MLX5_OPCODE_TSO);
297 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
298 _mm_store_si128(t_wqe, ctrl);
299 /* Fill ESEG in the header. */
300 _mm_store_si128(t_wqe + 1,
301 _mm_set_epi16(0, 0, 0, 0,
302 htons(len), cs_flags,
304 txq->wqe_ci = wqe_ci;
308 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
309 txq->elts_head = elts_head;
310 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
311 wqe->ctrl[2] = htonl(8);
312 wqe->ctrl[3] = txq->elts_head;
316 #ifdef MLX5_PMD_SOFT_COUNTERS
317 txq->stats.opackets += n;
319 mlx5_tx_dbrec(txq, wqe);
324 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
325 * it returns to make it processed by txq_scatter_v(). All the packets in
326 * the pkts list should be single segment packets having same offload flags.
327 * This must be checked by txq_check_multiseg() and txq_calc_offload().
330 * Pointer to TX queue structure.
332 * Pointer to array of packets to be sent.
334 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
336 * Checksum offload flags to be written in the descriptor.
339 * Number of packets successfully transmitted (<= pkts_n).
341 static inline uint16_t
342 txq_burst_v(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
345 struct rte_mbuf **elts;
346 uint16_t elts_head = txq->elts_head;
347 const uint16_t elts_n = 1 << txq->elts_n;
348 const uint16_t elts_m = elts_n - 1;
349 const unsigned int nb_dword_per_wqebb =
350 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
351 const unsigned int nb_dword_in_hdr =
352 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
357 uint32_t comp_req = 0;
358 const uint16_t wq_n = 1 << txq->wqe_n;
359 const uint16_t wq_mask = wq_n - 1;
360 uint16_t wq_idx = txq->wqe_ci & wq_mask;
361 volatile struct mlx5_wqe64 *wq =
362 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
363 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
364 const __m128i shuf_mask_ctrl =
365 _mm_set_epi8(15, 14, 13, 12,
366 8, 9, 10, 11, /* bswap32 */
367 4, 5, 6, 7, /* bswap32 */
368 0, 1, 2, 3 /* bswap32 */);
369 __m128i *t_wqe, *dseg;
372 /* Make sure all packets can fit into a single WQE. */
373 assert(elts_n > pkts_n);
374 mlx5_tx_complete(txq);
375 max_elts = (elts_n - (elts_head - txq->elts_tail));
376 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
377 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
378 if (unlikely(!pkts_n))
380 elts = &(*txq->elts)[elts_head & elts_m];
381 /* Loop for available tailroom first. */
382 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
383 for (pos = 0; pos < (n & -2); pos += 2)
384 _mm_storeu_si128((__m128i *)&elts[pos],
385 _mm_loadu_si128((__m128i *)&pkts[pos]));
387 elts[pos] = pkts[pos];
388 /* Check if it crosses the end of the queue. */
389 if (unlikely(n < pkts_n)) {
390 elts = &(*txq->elts)[0];
391 for (pos = 0; pos < pkts_n - n; ++pos)
392 elts[pos] = pkts[n + pos];
394 txq->elts_head += pkts_n;
395 /* Save title WQEBB pointer. */
396 t_wqe = (__m128i *)wqe;
397 dseg = (__m128i *)(wqe + 1);
398 /* Calculate the number of entries to the end. */
400 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
403 txq_wr_dseg_v(txq, dseg, pkts, n);
404 /* Check if it crosses the end of the queue. */
406 dseg = (__m128i *)txq->wqes;
407 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
409 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
410 txq->elts_comp += pkts_n;
412 /* Request a completion. */
417 /* Fill CTRL in the header. */
418 ctrl = _mm_set_epi32(txq->elts_head, comp_req,
419 txq->qp_num_8s | (pkts_n + 2),
420 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
421 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW);
422 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
423 _mm_store_si128(t_wqe, ctrl);
424 /* Fill ESEG in the header. */
425 _mm_store_si128(t_wqe + 1,
426 _mm_set_epi8(0, 0, 0, 0,
430 #ifdef MLX5_PMD_SOFT_COUNTERS
431 txq->stats.opackets += pkts_n;
433 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
435 /* Ring QP doorbell. */
436 mlx5_tx_dbrec(txq, wqe);
441 * DPDK callback for vectorized TX.
444 * Generic pointer to TX queue structure.
446 * Packets to transmit.
448 * Number of packets in array.
451 * Number of packets successfully transmitted (<= pkts_n).
454 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
457 struct txq *txq = (struct txq *)dpdk_txq;
460 while (pkts_n > nb_tx) {
464 n = RTE_MIN((uint16_t)(pkts_n - nb_tx), MLX5_VPMD_TX_MAX_BURST);
465 ret = txq_burst_v(txq, &pkts[nb_tx], n, 0);
474 * DPDK callback for vectorized TX with multi-seg packets and offload.
477 * Generic pointer to TX queue structure.
479 * Packets to transmit.
481 * Number of packets in array.
484 * Number of packets successfully transmitted (<= pkts_n).
487 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
489 struct txq *txq = (struct txq *)dpdk_txq;
492 while (pkts_n > nb_tx) {
493 uint8_t cs_flags = 0;
497 /* Transmit multi-seg packets in the head of pkts list. */
498 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS) &&
499 NB_SEGS(pkts[nb_tx]) > 1)
500 nb_tx += txq_scatter_v(txq,
503 n = RTE_MIN((uint16_t)(pkts_n - nb_tx), MLX5_VPMD_TX_MAX_BURST);
504 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS))
505 n = txq_check_multiseg(&pkts[nb_tx], n);
506 if (!(txq->flags & ETH_TXQ_FLAGS_NOOFFLOADS))
507 n = txq_calc_offload(txq, &pkts[nb_tx], n, &cs_flags);
508 ret = txq_burst_v(txq, &pkts[nb_tx], n, cs_flags);
517 * Store free buffers to RX SW ring.
520 * Pointer to RX queue structure.
522 * Pointer to array of packets to be stored.
524 * Number of packets to be stored.
527 rxq_copy_mbuf_v(struct rxq *rxq, struct rte_mbuf **pkts, uint16_t n)
529 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
530 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
534 for (pos = 0; pos < p; pos += 2) {
537 mbp = _mm_loadu_si128((__m128i *)&elts[pos]);
538 _mm_storeu_si128((__m128i *)&pkts[pos], mbp);
541 pkts[pos] = elts[pos];
545 * Replenish buffers for RX in bulk.
548 * Pointer to RX queue structure.
550 * Number of buffers to be replenished.
553 rxq_replenish_bulk_mbuf(struct rxq *rxq, uint16_t n)
555 const uint16_t q_n = 1 << rxq->elts_n;
556 const uint16_t q_mask = q_n - 1;
557 const uint16_t elts_idx = rxq->rq_ci & q_mask;
558 struct rte_mbuf **elts = &(*rxq->elts)[elts_idx];
559 volatile struct mlx5_wqe_data_seg *wq = &(*rxq->wqes)[elts_idx];
562 assert(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH);
563 assert(n <= (uint16_t)(q_n - (rxq->rq_ci - rxq->rq_pi)));
564 assert(MLX5_VPMD_RXQ_RPLNSH_THRESH > MLX5_VPMD_DESCS_PER_LOOP);
565 /* Not to cross queue end. */
566 n = RTE_MIN(n - MLX5_VPMD_DESCS_PER_LOOP, q_n - elts_idx);
567 if (rte_mempool_get_bulk(rxq->mp, (void *)elts, n) < 0) {
568 rxq->stats.rx_nombuf += n;
571 for (i = 0; i < n; ++i)
572 wq[i].addr = htonll(rte_pktmbuf_mtod(elts[i], uintptr_t));
575 *rxq->rq_db = htonl(rxq->rq_ci);
579 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
580 * extracted from the title completion descriptor.
583 * Pointer to RX queue structure.
585 * Pointer to completion array having a compressed completion at first.
587 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
588 * the title completion descriptor to be copied to the rest of mbufs.
591 rxq_cq_decompress_v(struct rxq *rxq,
592 volatile struct mlx5_cqe *cq,
593 struct rte_mbuf **elts)
595 volatile struct mlx5_mini_cqe8 *mcq = (void *)(cq + 1);
596 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
599 unsigned int inv = 0;
600 /* Mask to shuffle from extracted mini CQE to mbuf. */
601 const __m128i shuf_mask1 =
602 _mm_set_epi8(0, 1, 2, 3, /* rss, bswap32 */
603 -1, -1, /* skip vlan_tci */
604 6, 7, /* data_len, bswap16 */
605 -1, -1, 6, 7, /* pkt_len, bswap16 */
606 -1, -1, -1, -1 /* skip packet_type */);
607 const __m128i shuf_mask2 =
608 _mm_set_epi8(8, 9, 10, 11, /* rss, bswap32 */
609 -1, -1, /* skip vlan_tci */
610 14, 15, /* data_len, bswap16 */
611 -1, -1, 14, 15, /* pkt_len, bswap16 */
612 -1, -1, -1, -1 /* skip packet_type */);
613 /* Restore the compressed count. Must be 16 bits. */
614 const uint16_t mcqe_n = t_pkt->data_len +
615 (rxq->crc_present * ETHER_CRC_LEN);
616 const __m128i rearm =
617 _mm_loadu_si128((__m128i *)&t_pkt->rearm_data);
619 _mm_loadu_si128((__m128i *)&t_pkt->rx_descriptor_fields1);
620 const __m128i crc_adj =
621 _mm_set_epi16(0, 0, 0,
622 rxq->crc_present * ETHER_CRC_LEN,
624 rxq->crc_present * ETHER_CRC_LEN,
626 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
627 #ifdef MLX5_PMD_SOFT_COUNTERS
628 const __m128i zero = _mm_setzero_si128();
629 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
630 uint32_t rcvd_byte = 0;
631 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
632 const __m128i len_shuf_mask =
633 _mm_set_epi8(-1, -1, -1, -1,
639 /* Compile time sanity check for this function. */
640 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
641 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
642 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
643 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
644 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
645 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
647 * A. load mCQEs into a 128bit register.
648 * B. store rearm data to mbuf.
649 * C. combine data from mCQEs with rx_descriptor_fields1.
650 * D. store rx_descriptor_fields1.
651 * E. store flow tag (rte_flow mark).
653 for (pos = 0; pos < mcqe_n; ) {
654 __m128i mcqe1, mcqe2;
655 __m128i rxdf1, rxdf2;
656 #ifdef MLX5_PMD_SOFT_COUNTERS
657 __m128i byte_cnt, invalid_mask;
660 if (!(pos & 0x7) && pos + 8 < mcqe_n)
661 rte_prefetch0((void *)(cq + pos + 8));
662 /* A.1 load mCQEs into a 128bit register. */
663 mcqe1 = _mm_loadu_si128((__m128i *)&mcq[pos % 8]);
664 mcqe2 = _mm_loadu_si128((__m128i *)&mcq[pos % 8 + 2]);
665 /* B.1 store rearm data to mbuf. */
666 _mm_storeu_si128((__m128i *)&elts[pos]->rearm_data, rearm);
667 _mm_storeu_si128((__m128i *)&elts[pos + 1]->rearm_data, rearm);
668 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
669 rxdf1 = _mm_shuffle_epi8(mcqe1, shuf_mask1);
670 rxdf2 = _mm_shuffle_epi8(mcqe1, shuf_mask2);
671 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
672 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
673 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
674 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
675 /* D.1 store rx_descriptor_fields1. */
676 _mm_storeu_si128((__m128i *)
677 &elts[pos]->rx_descriptor_fields1,
679 _mm_storeu_si128((__m128i *)
680 &elts[pos + 1]->rx_descriptor_fields1,
682 /* B.1 store rearm data to mbuf. */
683 _mm_storeu_si128((__m128i *)&elts[pos + 2]->rearm_data, rearm);
684 _mm_storeu_si128((__m128i *)&elts[pos + 3]->rearm_data, rearm);
685 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
686 rxdf1 = _mm_shuffle_epi8(mcqe2, shuf_mask1);
687 rxdf2 = _mm_shuffle_epi8(mcqe2, shuf_mask2);
688 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
689 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
690 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
691 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
692 /* D.1 store rx_descriptor_fields1. */
693 _mm_storeu_si128((__m128i *)
694 &elts[pos + 2]->rx_descriptor_fields1,
696 _mm_storeu_si128((__m128i *)
697 &elts[pos + 3]->rx_descriptor_fields1,
699 #ifdef MLX5_PMD_SOFT_COUNTERS
700 invalid_mask = _mm_set_epi64x(0,
702 sizeof(uint16_t) * 8);
703 invalid_mask = _mm_sll_epi64(ones, invalid_mask);
704 mcqe1 = _mm_srli_si128(mcqe1, 4);
705 byte_cnt = _mm_blend_epi16(mcqe1, mcqe2, 0xcc);
706 byte_cnt = _mm_shuffle_epi8(byte_cnt, len_shuf_mask);
707 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
708 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
709 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
712 /* E.1 store flow tag (rte_flow mark). */
713 elts[pos]->hash.fdir.hi = flow_tag;
714 elts[pos + 1]->hash.fdir.hi = flow_tag;
715 elts[pos + 2]->hash.fdir.hi = flow_tag;
716 elts[pos + 3]->hash.fdir.hi = flow_tag;
718 pos += MLX5_VPMD_DESCS_PER_LOOP;
719 /* Move to next CQE and invalidate consumed CQEs. */
720 if (!(pos & 0x7) && pos < mcqe_n) {
721 mcq = (void *)(cq + pos);
722 for (i = 0; i < 8; ++i)
723 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
726 /* Invalidate the rest of CQEs. */
727 for (; inv < mcqe_n; ++inv)
728 cq[inv].op_own = MLX5_CQE_INVALIDATE;
729 #ifdef MLX5_PMD_SOFT_COUNTERS
730 rxq->stats.ipackets += mcqe_n;
731 rxq->stats.ibytes += rcvd_byte;
733 rxq->cq_ci += mcqe_n;
737 * Calculate packet type and offload flag for mbuf and store it.
740 * Pointer to RX queue structure.
742 * Array of four 16bytes completions extracted from the original completion
745 * Opcode vector having responder error status. Each field is 4B.
747 * Pointer to array of packets to be filled.
750 rxq_cq_to_ptype_oflags_v(struct rxq *rxq, __m128i cqes[4], __m128i op_err,
751 struct rte_mbuf **pkts)
753 __m128i pinfo0, pinfo1;
754 __m128i pinfo, ptype;
755 __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH);
757 const __m128i zero = _mm_setzero_si128();
758 const __m128i ptype_mask =
759 _mm_set_epi32(0xd06, 0xd06, 0xd06, 0xd06);
760 const __m128i ptype_ol_mask =
761 _mm_set_epi32(0x106, 0x106, 0x106, 0x106);
762 const __m128i pinfo_mask =
763 _mm_set_epi32(0x3, 0x3, 0x3, 0x3);
764 const __m128i cv_flag_sel =
765 _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
766 (uint8_t)((PKT_RX_IP_CKSUM_GOOD |
767 PKT_RX_L4_CKSUM_GOOD) >> 1),
769 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
771 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
772 (uint8_t)(PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED),
774 const __m128i cv_mask =
775 _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
776 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
777 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
778 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
779 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
780 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
781 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
782 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED);
783 const __m128i mbuf_init =
784 _mm_loadl_epi64((__m128i *)&rxq->mbuf_initializer);
785 __m128i rearm0, rearm1, rearm2, rearm3;
787 /* Extract pkt_info field. */
788 pinfo0 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
789 pinfo1 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
790 pinfo = _mm_unpacklo_epi64(pinfo0, pinfo1);
791 /* Extract hdr_type_etc field. */
792 pinfo0 = _mm_unpackhi_epi32(cqes[0], cqes[1]);
793 pinfo1 = _mm_unpackhi_epi32(cqes[2], cqes[3]);
794 ptype = _mm_unpacklo_epi64(pinfo0, pinfo1);
796 const __m128i pinfo_ft_mask =
797 _mm_set_epi32(0xffffff00, 0xffffff00,
798 0xffffff00, 0xffffff00);
799 const __m128i fdir_flags = _mm_set1_epi32(PKT_RX_FDIR);
800 const __m128i fdir_id_flags = _mm_set1_epi32(PKT_RX_FDIR_ID);
801 __m128i flow_tag, invalid_mask;
803 flow_tag = _mm_and_si128(pinfo, pinfo_ft_mask);
804 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
805 invalid_mask = _mm_cmpeq_epi32(flow_tag, zero);
806 ol_flags = _mm_or_si128(ol_flags,
807 _mm_andnot_si128(invalid_mask,
809 /* Mask out invalid entries. */
810 flow_tag = _mm_andnot_si128(invalid_mask, flow_tag);
811 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
812 ol_flags = _mm_or_si128(ol_flags,
814 _mm_cmpeq_epi32(flow_tag,
819 * Merge the two fields to generate the following:
820 * bit[1] = l3_ok, bit[2] = l4_ok
821 * bit[8] = cv, bit[11:10] = l3_hdr_type
822 * bit[12] = tunneled, bit[13] = outer_l3_type
824 ptype = _mm_and_si128(ptype, ptype_mask);
825 pinfo = _mm_and_si128(pinfo, pinfo_mask);
826 pinfo = _mm_slli_epi32(pinfo, 12);
827 ptype = _mm_or_si128(ptype, pinfo);
828 ptype = _mm_srli_epi32(ptype, 10);
829 ptype = _mm_packs_epi32(ptype, zero);
830 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
831 op_err = _mm_srli_epi16(op_err, 12);
832 ptype = _mm_or_si128(ptype, op_err);
833 pkts[0]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 0)];
834 pkts[1]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 2)];
835 pkts[2]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 4)];
836 pkts[3]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 6)];
837 /* Fill flags for checksum and VLAN. */
838 pinfo = _mm_and_si128(pinfo, ptype_ol_mask);
839 pinfo = _mm_shuffle_epi8(cv_flag_sel, pinfo);
840 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
841 cv_flags = _mm_slli_epi32(pinfo, 9);
842 cv_flags = _mm_or_si128(pinfo, cv_flags);
843 /* Move back flags to start from byte[0]. */
844 cv_flags = _mm_srli_epi32(cv_flags, 8);
845 /* Mask out garbage bits. */
846 cv_flags = _mm_and_si128(cv_flags, cv_mask);
847 /* Merge to ol_flags. */
848 ol_flags = _mm_or_si128(ol_flags, cv_flags);
849 /* Merge mbuf_init and ol_flags. */
850 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
851 offsetof(struct rte_mbuf, rearm_data) + 8);
852 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 8), 0x30);
853 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 4), 0x30);
854 rearm2 = _mm_blend_epi16(mbuf_init, ol_flags, 0x30);
855 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(ol_flags, 4), 0x30);
856 /* Write 8B rearm_data and 8B ol_flags. */
857 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
858 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
859 _mm_store_si128((__m128i *)&pkts[0]->rearm_data, rearm0);
860 _mm_store_si128((__m128i *)&pkts[1]->rearm_data, rearm1);
861 _mm_store_si128((__m128i *)&pkts[2]->rearm_data, rearm2);
862 _mm_store_si128((__m128i *)&pkts[3]->rearm_data, rearm3);
866 * Skip error packets.
869 * Pointer to RX queue structure.
871 * Array to store received packets.
873 * Maximum number of packets in array.
876 * Number of packets successfully received (<= pkts_n).
879 rxq_handle_pending_error(struct rxq *rxq, struct rte_mbuf **pkts,
885 for (i = 0; i < pkts_n; ++i) {
886 struct rte_mbuf *pkt = pkts[i];
888 if (pkt->packet_type == RTE_PTYPE_ALL_MASK)
889 rte_pktmbuf_free_seg(pkt);
893 rxq->stats.idropped += (pkts_n - n);
894 rxq->pending_err = 0;
899 * Receive burst of packets. An errored completion also consumes a mbuf, but the
900 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
901 * before returning to application.
904 * Pointer to RX queue structure.
906 * Array to store received packets.
908 * Maximum number of packets in array.
911 * Number of packets received including errors (<= pkts_n).
913 static inline uint16_t
914 rxq_burst_v(struct rxq *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
916 const uint16_t q_n = 1 << rxq->cqe_n;
917 const uint16_t q_mask = q_n - 1;
918 volatile struct mlx5_cqe *cq;
919 struct rte_mbuf **elts;
923 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
924 uint16_t nocmp_n = 0;
925 uint16_t rcvd_pkt = 0;
926 unsigned int cq_idx = rxq->cq_ci & q_mask;
927 unsigned int elts_idx;
928 unsigned int ownership = !!(rxq->cq_ci & (q_mask + 1));
929 const __m128i owner_check =
930 _mm_set_epi64x(0x0100000001000000LL, 0x0100000001000000LL);
931 const __m128i opcode_check =
932 _mm_set_epi64x(0xf0000000f0000000LL, 0xf0000000f0000000LL);
933 const __m128i format_check =
934 _mm_set_epi64x(0x0c0000000c000000LL, 0x0c0000000c000000LL);
935 const __m128i resp_err_check =
936 _mm_set_epi64x(0xe0000000e0000000LL, 0xe0000000e0000000LL);
937 #ifdef MLX5_PMD_SOFT_COUNTERS
938 uint32_t rcvd_byte = 0;
939 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
940 const __m128i len_shuf_mask =
941 _mm_set_epi8(-1, -1, -1, -1,
946 /* Mask to shuffle from extracted CQE to mbuf. */
947 const __m128i shuf_mask =
948 _mm_set_epi8(-1, 3, 2, 1, /* fdir.hi */
949 12, 13, 14, 15, /* rss, bswap32 */
950 10, 11, /* vlan_tci, bswap16 */
951 4, 5, /* data_len, bswap16 */
952 -1, -1, /* zero out 2nd half of pkt_len */
953 4, 5 /* pkt_len, bswap16 */);
954 /* Mask to blend from the last Qword to the first DQword. */
955 const __m128i blend_mask =
956 _mm_set_epi8(-1, -1, -1, -1,
960 const __m128i zero = _mm_setzero_si128();
961 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
962 const __m128i crc_adj =
963 _mm_set_epi16(0, 0, 0, 0, 0,
964 rxq->crc_present * ETHER_CRC_LEN,
966 rxq->crc_present * ETHER_CRC_LEN);
967 const __m128i flow_mark_adj = _mm_set_epi32(rxq->mark * (-1), 0, 0, 0);
969 /* Compile time sanity check for this function. */
970 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
971 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
972 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
973 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
974 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, pkt_info) != 0);
975 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rx_hash_res) !=
976 offsetof(struct mlx5_cqe, pkt_info) + 12);
977 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rsvd1) +
978 sizeof(((struct mlx5_cqe *)0)->rsvd1) !=
979 offsetof(struct mlx5_cqe, hdr_type_etc));
980 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, vlan_info) !=
981 offsetof(struct mlx5_cqe, hdr_type_etc) + 2);
982 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rsvd2) +
983 sizeof(((struct mlx5_cqe *)0)->rsvd2) !=
984 offsetof(struct mlx5_cqe, byte_cnt));
985 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, sop_drop_qpn) !=
986 RTE_ALIGN(offsetof(struct mlx5_cqe, sop_drop_qpn), 8));
987 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, op_own) !=
988 offsetof(struct mlx5_cqe, sop_drop_qpn) + 7);
989 assert(rxq->sges_n == 0);
990 assert(rxq->cqe_n == rxq->elts_n);
991 cq = &(*rxq->cqes)[cq_idx];
993 rte_prefetch0(cq + 1);
994 rte_prefetch0(cq + 2);
995 rte_prefetch0(cq + 3);
996 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
999 * rq_ci >= cq_ci >= rq_pi
1000 * Definition of indexes:
1001 * rq_ci - cq_ci := # of buffers owned by HW (posted).
1002 * cq_ci - rq_pi := # of buffers not returned to app (decompressed).
1003 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished).
1005 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
1006 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH)
1007 rxq_replenish_bulk_mbuf(rxq, repl_n);
1008 /* See if there're unreturned mbufs from compressed CQE. */
1009 rcvd_pkt = rxq->cq_ci - rxq->rq_pi;
1011 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
1012 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
1013 rxq->rq_pi += rcvd_pkt;
1016 elts_idx = rxq->rq_pi & q_mask;
1017 elts = &(*rxq->elts)[elts_idx];
1018 /* Not to overflow pkts array. */
1019 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
1020 /* Not to cross queue end. */
1021 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
1024 /* At this point, there shouldn't be any remained packets. */
1025 assert(rxq->rq_pi == rxq->cq_ci);
1027 * A. load first Qword (8bytes) in one loop.
1028 * B. copy 4 mbuf pointers from elts ring to returing pkts.
1029 * C. load remained CQE data and extract necessary fields.
1030 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
1031 * following structure:
1034 * uint8_t flow_tag[3];
1035 * uint16_t byte_cnt;
1038 * uint16_t hdr_type_etc;
1039 * uint16_t vlan_info;
1040 * uint32_t rx_has_res;
1043 * E. get valid CQEs.
1044 * F. find compressed CQE.
1048 pos += MLX5_VPMD_DESCS_PER_LOOP) {
1049 __m128i cqes[MLX5_VPMD_DESCS_PER_LOOP];
1050 __m128i cqe_tmp1, cqe_tmp2;
1051 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
1052 __m128i op_own, op_own_tmp1, op_own_tmp2;
1053 __m128i opcode, owner_mask, invalid_mask;
1056 #ifdef MLX5_PMD_SOFT_COUNTERS
1060 __m128i p = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0);
1061 unsigned int p1, p2, p3;
1063 /* Prefetch next 4 CQEs. */
1064 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
1065 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP]);
1066 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 1]);
1067 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 2]);
1068 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 3]);
1070 /* A.0 do not cross the end of CQ. */
1071 mask = _mm_set_epi64x(0, (pkts_n - pos) * sizeof(uint16_t) * 8);
1072 mask = _mm_sll_epi64(ones, mask);
1073 p = _mm_andnot_si128(mask, p);
1074 /* A.1 load cqes. */
1075 p3 = _mm_extract_epi16(p, 3);
1076 cqes[3] = _mm_loadl_epi64((__m128i *)
1077 &cq[pos + p3].sop_drop_qpn);
1078 rte_compiler_barrier();
1079 p2 = _mm_extract_epi16(p, 2);
1080 cqes[2] = _mm_loadl_epi64((__m128i *)
1081 &cq[pos + p2].sop_drop_qpn);
1082 rte_compiler_barrier();
1083 /* B.1 load mbuf pointers. */
1084 mbp1 = _mm_loadu_si128((__m128i *)&elts[pos]);
1085 mbp2 = _mm_loadu_si128((__m128i *)&elts[pos + 2]);
1086 /* A.1 load a block having op_own. */
1087 p1 = _mm_extract_epi16(p, 1);
1088 cqes[1] = _mm_loadl_epi64((__m128i *)
1089 &cq[pos + p1].sop_drop_qpn);
1090 rte_compiler_barrier();
1091 cqes[0] = _mm_loadl_epi64((__m128i *)
1092 &cq[pos].sop_drop_qpn);
1093 /* B.2 copy mbuf pointers. */
1094 _mm_storeu_si128((__m128i *)&pkts[pos], mbp1);
1095 _mm_storeu_si128((__m128i *)&pkts[pos + 2], mbp2);
1096 rte_compiler_barrier();
1097 /* C.1 load remained CQE data and extract necessary fields. */
1098 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p3]);
1099 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos + p2]);
1100 cqes[3] = _mm_blendv_epi8(cqes[3], cqe_tmp2, blend_mask);
1101 cqes[2] = _mm_blendv_epi8(cqes[2], cqe_tmp1, blend_mask);
1102 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p3].rsvd1[3]);
1103 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos + p2].rsvd1[3]);
1104 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x30);
1105 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x30);
1106 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p3].rsvd2[10]);
1107 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos + p2].rsvd2[10]);
1108 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x04);
1109 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x04);
1110 /* C.2 generate final structure for mbuf with swapping bytes. */
1111 pkt_mb3 = _mm_shuffle_epi8(cqes[3], shuf_mask);
1112 pkt_mb2 = _mm_shuffle_epi8(cqes[2], shuf_mask);
1113 /* C.3 adjust CRC length. */
1114 pkt_mb3 = _mm_sub_epi16(pkt_mb3, crc_adj);
1115 pkt_mb2 = _mm_sub_epi16(pkt_mb2, crc_adj);
1116 /* C.4 adjust flow mark. */
1117 pkt_mb3 = _mm_add_epi32(pkt_mb3, flow_mark_adj);
1118 pkt_mb2 = _mm_add_epi32(pkt_mb2, flow_mark_adj);
1119 /* D.1 fill in mbuf - rx_descriptor_fields1. */
1120 _mm_storeu_si128((void *)&pkts[pos + 3]->pkt_len, pkt_mb3);
1121 _mm_storeu_si128((void *)&pkts[pos + 2]->pkt_len, pkt_mb2);
1122 /* E.1 extract op_own field. */
1123 op_own_tmp2 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
1124 /* C.1 load remained CQE data and extract necessary fields. */
1125 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p1]);
1126 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos]);
1127 cqes[1] = _mm_blendv_epi8(cqes[1], cqe_tmp2, blend_mask);
1128 cqes[0] = _mm_blendv_epi8(cqes[0], cqe_tmp1, blend_mask);
1129 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p1].rsvd1[3]);
1130 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos].rsvd1[3]);
1131 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x30);
1132 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x30);
1133 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p1].rsvd2[10]);
1134 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos].rsvd2[10]);
1135 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x04);
1136 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x04);
1137 /* C.2 generate final structure for mbuf with swapping bytes. */
1138 pkt_mb1 = _mm_shuffle_epi8(cqes[1], shuf_mask);
1139 pkt_mb0 = _mm_shuffle_epi8(cqes[0], shuf_mask);
1140 /* C.3 adjust CRC length. */
1141 pkt_mb1 = _mm_sub_epi16(pkt_mb1, crc_adj);
1142 pkt_mb0 = _mm_sub_epi16(pkt_mb0, crc_adj);
1143 /* C.4 adjust flow mark. */
1144 pkt_mb1 = _mm_add_epi32(pkt_mb1, flow_mark_adj);
1145 pkt_mb0 = _mm_add_epi32(pkt_mb0, flow_mark_adj);
1146 /* E.1 extract op_own byte. */
1147 op_own_tmp1 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
1148 op_own = _mm_unpackhi_epi64(op_own_tmp1, op_own_tmp2);
1149 /* D.1 fill in mbuf - rx_descriptor_fields1. */
1150 _mm_storeu_si128((void *)&pkts[pos + 1]->pkt_len, pkt_mb1);
1151 _mm_storeu_si128((void *)&pkts[pos]->pkt_len, pkt_mb0);
1152 /* E.2 flip owner bit to mark CQEs from last round. */
1153 owner_mask = _mm_and_si128(op_own, owner_check);
1155 owner_mask = _mm_xor_si128(owner_mask, owner_check);
1156 owner_mask = _mm_cmpeq_epi32(owner_mask, owner_check);
1157 owner_mask = _mm_packs_epi32(owner_mask, zero);
1158 /* E.3 get mask for invalidated CQEs. */
1159 opcode = _mm_and_si128(op_own, opcode_check);
1160 invalid_mask = _mm_cmpeq_epi32(opcode_check, opcode);
1161 invalid_mask = _mm_packs_epi32(invalid_mask, zero);
1162 /* E.4 mask out beyond boundary. */
1163 invalid_mask = _mm_or_si128(invalid_mask, mask);
1164 /* E.5 merge invalid_mask with invalid owner. */
1165 invalid_mask = _mm_or_si128(invalid_mask, owner_mask);
1166 /* F.1 find compressed CQE format. */
1167 comp_mask = _mm_and_si128(op_own, format_check);
1168 comp_mask = _mm_cmpeq_epi32(comp_mask, format_check);
1169 comp_mask = _mm_packs_epi32(comp_mask, zero);
1170 /* F.2 mask out invalid entries. */
1171 comp_mask = _mm_andnot_si128(invalid_mask, comp_mask);
1172 comp_idx = _mm_cvtsi128_si64(comp_mask);
1173 /* F.3 get the first compressed CQE. */
1174 comp_idx = comp_idx ?
1175 __builtin_ctzll(comp_idx) /
1176 (sizeof(uint16_t) * 8) :
1177 MLX5_VPMD_DESCS_PER_LOOP;
1178 /* E.6 mask out entries after the compressed CQE. */
1179 mask = _mm_set_epi64x(0, comp_idx * sizeof(uint16_t) * 8);
1180 mask = _mm_sll_epi64(ones, mask);
1181 invalid_mask = _mm_or_si128(invalid_mask, mask);
1182 /* E.7 count non-compressed valid CQEs. */
1183 n = _mm_cvtsi128_si64(invalid_mask);
1184 n = n ? __builtin_ctzll(n) / (sizeof(uint16_t) * 8) :
1185 MLX5_VPMD_DESCS_PER_LOOP;
1187 /* D.2 get the final invalid mask. */
1188 mask = _mm_set_epi64x(0, n * sizeof(uint16_t) * 8);
1189 mask = _mm_sll_epi64(ones, mask);
1190 invalid_mask = _mm_or_si128(invalid_mask, mask);
1191 /* D.3 check error in opcode. */
1192 opcode = _mm_cmpeq_epi32(resp_err_check, opcode);
1193 opcode = _mm_packs_epi32(opcode, zero);
1194 opcode = _mm_andnot_si128(invalid_mask, opcode);
1195 /* D.4 mark if any error is set */
1196 rxq->pending_err |= !!_mm_cvtsi128_si64(opcode);
1197 /* D.5 fill in mbuf - rearm_data and packet_type. */
1198 rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
1199 #ifdef MLX5_PMD_SOFT_COUNTERS
1200 /* Add up received bytes count. */
1201 byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);
1202 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
1203 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
1204 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
1207 * Break the loop unless more valid CQE is expected, or if
1208 * there's a compressed CQE.
1210 if (n != MLX5_VPMD_DESCS_PER_LOOP)
1213 /* If no new CQE seen, return without updating cq_db. */
1214 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
1216 /* Update the consumer indexes for non-compressed CQEs. */
1217 assert(nocmp_n <= pkts_n);
1218 rxq->cq_ci += nocmp_n;
1219 rxq->rq_pi += nocmp_n;
1220 rcvd_pkt += nocmp_n;
1221 #ifdef MLX5_PMD_SOFT_COUNTERS
1222 rxq->stats.ipackets += nocmp_n;
1223 rxq->stats.ibytes += rcvd_byte;
1225 /* Decompress the last CQE if compressed. */
1226 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
1227 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
1228 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);
1229 /* Return more packets if needed. */
1230 if (nocmp_n < pkts_n) {
1231 uint16_t n = rxq->cq_ci - rxq->rq_pi;
1233 n = RTE_MIN(n, pkts_n - nocmp_n);
1234 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
1240 *rxq->cq_db = htonl(rxq->cq_ci);
1245 * DPDK callback for vectorized RX.
1248 * Generic pointer to RX queue structure.
1250 * Array to store received packets.
1252 * Maximum number of packets in array.
1255 * Number of packets successfully received (<= pkts_n).
1258 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1260 struct rxq *rxq = dpdk_rxq;
1263 nb_rx = rxq_burst_v(rxq, pkts, pkts_n);
1264 if (unlikely(rxq->pending_err))
1265 nb_rx = rxq_handle_pending_error(rxq, pkts, nb_rx);
1270 * Check Tx queue flags are set for raw vectorized Tx.
1273 * Pointer to private structure.
1276 * 1 if supported, negative errno value if not.
1278 int __attribute__((cold))
1279 priv_check_raw_vec_tx_support(struct priv *priv)
1283 /* All the configured queues should support. */
1284 for (i = 0; i < priv->txqs_n; ++i) {
1285 struct txq *txq = (*priv->txqs)[i];
1287 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS) ||
1288 !(txq->flags & ETH_TXQ_FLAGS_NOOFFLOADS))
1291 if (i != priv->txqs_n)
1297 * Check a device can support vectorized TX.
1300 * Pointer to private structure.
1303 * 1 if supported, negative errno value if not.
1305 int __attribute__((cold))
1306 priv_check_vec_tx_support(struct priv *priv)
1308 if (priv->txqs_n > MLX5_VPMD_MIN_TXQS ||
1309 priv->mps != MLX5_MPW_ENHANCED ||
1316 * Check a RX queue can support vectorized RX.
1319 * Pointer to RX queue.
1322 * 1 if supported, negative errno value if not.
1324 int __attribute__((cold))
1325 rxq_check_vec_support(struct rxq *rxq)
1327 if (rxq->sges_n != 0)
1333 * Check a device can support vectorized RX.
1336 * Pointer to private structure.
1339 * 1 if supported, negative errno value if not.
1341 int __attribute__((cold))
1342 priv_check_vec_rx_support(struct priv *priv)
1346 /* All the configured queues should support. */
1347 for (i = 0; i < priv->rxqs_n; ++i) {
1348 struct rxq *rxq = (*priv->rxqs)[i];
1350 if (rxq_check_vec_support(rxq) < 0)
1353 if (i != priv->rxqs_n)
1359 * Prepare for vectorized RX.
1362 * Pointer to private structure.
1365 priv_prep_vec_rx_function(struct priv *priv)
1369 for (i = 0; i < priv->rxqs_n; ++i) {
1370 struct rxq *rxq = (*priv->rxqs)[i];
1371 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
1372 const uint16_t desc = 1 << rxq->elts_n;
1375 assert(rxq->elts_n == rxq->cqe_n);
1376 /* Initialize default rearm_data for vPMD. */
1377 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
1378 rte_mbuf_refcnt_set(mbuf_init, 1);
1379 mbuf_init->nb_segs = 1;
1380 mbuf_init->port = rxq->port_id;
1382 * prevent compiler reordering:
1383 * rearm_data covers previous fields.
1385 rte_compiler_barrier();
1386 rxq->mbuf_initializer =
1387 *(uint64_t *)&mbuf_init->rearm_data;
1388 /* Padding with a fake mbuf for vectorized Rx. */
1389 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
1390 (*rxq->elts)[desc + j] = &rxq->fake_mbuf;
1391 /* Mark that it need to be cleaned up for rxq_alloc_elts(). */