1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox.
6 #ifndef RTE_PMD_MLX5_RXTX_VEC_SSE_H_
7 #define RTE_PMD_MLX5_RXTX_VEC_SSE_H_
13 #include <smmintrin.h>
16 #include <rte_mempool.h>
17 #include <rte_prefetch.h>
20 #include "mlx5_utils.h"
21 #include "mlx5_rxtx.h"
22 #include "mlx5_rxtx_vec.h"
23 #include "mlx5_autoconf.h"
24 #include "mlx5_defs.h"
27 #ifndef __INTEL_COMPILER
28 #pragma GCC diagnostic ignored "-Wcast-qual"
32 * Fill in buffer descriptors in a multi-packet send descriptor.
35 * Pointer to TX queue structure.
37 * Pointer to buffer descriptor to be written.
39 * Pointer to array of packets to be sent.
41 * Number of packets to be filled.
44 txq_wr_dseg_v(struct mlx5_txq_data *txq, __m128i *dseg,
45 struct rte_mbuf **pkts, unsigned int n)
49 const __m128i shuf_mask_dseg =
50 _mm_set_epi8(8, 9, 10, 11, /* addr, bswap64 */
52 7, 6, 5, 4, /* lkey */
53 0, 1, 2, 3 /* length, bswap32 */);
54 #ifdef MLX5_PMD_SOFT_COUNTERS
58 for (pos = 0; pos < n; ++pos, ++dseg) {
60 struct rte_mbuf *pkt = pkts[pos];
62 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
63 desc = _mm_set_epi32(addr >> 32,
65 mlx5_tx_mb2mr(txq, pkt),
67 desc = _mm_shuffle_epi8(desc, shuf_mask_dseg);
68 _mm_store_si128(dseg, desc);
69 #ifdef MLX5_PMD_SOFT_COUNTERS
70 tx_byte += DATA_LEN(pkt);
73 #ifdef MLX5_PMD_SOFT_COUNTERS
74 txq->stats.obytes += tx_byte;
79 * Send multi-segmented packets until it encounters a single segment packet in
83 * Pointer to TX queue structure.
85 * Pointer to array of packets to be sent.
87 * Number of packets to be sent.
90 * Number of packets successfully transmitted (<= pkts_n).
93 txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
96 uint16_t elts_head = txq->elts_head;
97 const uint16_t elts_n = 1 << txq->elts_n;
98 const uint16_t elts_m = elts_n - 1;
99 const uint16_t wq_n = 1 << txq->wqe_n;
100 const uint16_t wq_mask = wq_n - 1;
101 const unsigned int nb_dword_per_wqebb =
102 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
103 const unsigned int nb_dword_in_hdr =
104 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
106 volatile struct mlx5_wqe *wqe = NULL;
108 assert(elts_n > pkts_n);
109 mlx5_tx_complete(txq);
110 /* A CQE slot must always be available. */
111 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
112 if (unlikely(!pkts_n))
114 for (n = 0; n < pkts_n; ++n) {
115 struct rte_mbuf *buf = pkts[n];
116 unsigned int segs_n = buf->nb_segs;
117 unsigned int ds = nb_dword_in_hdr;
118 unsigned int len = PKT_LEN(buf);
119 uint16_t wqe_ci = txq->wqe_ci;
120 const __m128i shuf_mask_ctrl =
121 _mm_set_epi8(15, 14, 13, 12,
122 8, 9, 10, 11, /* bswap32 */
123 4, 5, 6, 7, /* bswap32 */
124 0, 1, 2, 3 /* bswap32 */);
128 __m128i *t_wqe, *dseg;
132 max_elts = elts_n - (elts_head - txq->elts_tail);
133 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
135 * A MPW session consumes 2 WQEs at most to
136 * include MLX5_MPW_DSEG_MAX pointers.
139 max_elts < segs_n || max_wqe < 2)
141 if (segs_n > MLX5_MPW_DSEG_MAX) {
142 txq->stats.oerrors++;
145 wqe = &((volatile struct mlx5_wqe64 *)
146 txq->wqes)[wqe_ci & wq_mask].hdr;
147 cs_flags = txq_ol_cksum_to_cs(txq, buf);
148 /* Title WQEBB pointer. */
149 t_wqe = (__m128i *)wqe;
150 dseg = (__m128i *)(wqe + 1);
152 if (!(ds++ % nb_dword_per_wqebb)) {
154 &((volatile struct mlx5_wqe64 *)
155 txq->wqes)[++wqe_ci & wq_mask];
157 txq_wr_dseg_v(txq, dseg++, &buf, 1);
158 (*txq->elts)[elts_head++ & elts_m] = buf;
162 /* Fill CTRL in the header. */
163 ctrl = _mm_set_epi32(0, 0, txq->qp_num_8s | ds,
164 MLX5_OPC_MOD_MPW << 24 |
165 txq->wqe_ci << 8 | MLX5_OPCODE_TSO);
166 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
167 _mm_store_si128(t_wqe, ctrl);
168 /* Fill ESEG in the header. */
169 _mm_store_si128(t_wqe + 1,
170 _mm_set_epi16(0, 0, 0, 0,
171 rte_cpu_to_be_16(len), cs_flags,
173 txq->wqe_ci = wqe_ci;
177 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
178 txq->elts_head = elts_head;
179 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
180 wqe->ctrl[2] = rte_cpu_to_be_32(8);
181 wqe->ctrl[3] = txq->elts_head;
187 #ifdef MLX5_PMD_SOFT_COUNTERS
188 txq->stats.opackets += n;
190 mlx5_tx_dbrec(txq, wqe);
195 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
196 * it returns to make it processed by txq_scatter_v(). All the packets in
197 * the pkts list should be single segment packets having same offload flags.
198 * This must be checked by txq_count_contig_single_seg() and txq_calc_offload().
201 * Pointer to TX queue structure.
203 * Pointer to array of packets to be sent.
205 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
207 * Checksum offload flags to be written in the descriptor.
210 * Number of packets successfully transmitted (<= pkts_n).
212 static inline uint16_t
213 txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
216 struct rte_mbuf **elts;
217 uint16_t elts_head = txq->elts_head;
218 const uint16_t elts_n = 1 << txq->elts_n;
219 const uint16_t elts_m = elts_n - 1;
220 const unsigned int nb_dword_per_wqebb =
221 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
222 const unsigned int nb_dword_in_hdr =
223 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
228 uint32_t comp_req = 0;
229 const uint16_t wq_n = 1 << txq->wqe_n;
230 const uint16_t wq_mask = wq_n - 1;
231 uint16_t wq_idx = txq->wqe_ci & wq_mask;
232 volatile struct mlx5_wqe64 *wq =
233 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
234 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
235 const __m128i shuf_mask_ctrl =
236 _mm_set_epi8(15, 14, 13, 12,
237 8, 9, 10, 11, /* bswap32 */
238 4, 5, 6, 7, /* bswap32 */
239 0, 1, 2, 3 /* bswap32 */);
240 __m128i *t_wqe, *dseg;
243 /* Make sure all packets can fit into a single WQE. */
244 assert(elts_n > pkts_n);
245 mlx5_tx_complete(txq);
246 max_elts = (elts_n - (elts_head - txq->elts_tail));
247 /* A CQE slot must always be available. */
248 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
249 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
250 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
251 assert(pkts_n <= MLX5_DSEG_MAX - nb_dword_in_hdr);
252 if (unlikely(!pkts_n))
254 elts = &(*txq->elts)[elts_head & elts_m];
255 /* Loop for available tailroom first. */
256 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
257 for (pos = 0; pos < (n & -2); pos += 2)
258 _mm_storeu_si128((__m128i *)&elts[pos],
259 _mm_loadu_si128((__m128i *)&pkts[pos]));
261 elts[pos] = pkts[pos];
262 /* Check if it crosses the end of the queue. */
263 if (unlikely(n < pkts_n)) {
264 elts = &(*txq->elts)[0];
265 for (pos = 0; pos < pkts_n - n; ++pos)
266 elts[pos] = pkts[n + pos];
268 txq->elts_head += pkts_n;
269 /* Save title WQEBB pointer. */
270 t_wqe = (__m128i *)wqe;
271 dseg = (__m128i *)(wqe + 1);
272 /* Calculate the number of entries to the end. */
274 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
277 txq_wr_dseg_v(txq, dseg, pkts, n);
278 /* Check if it crosses the end of the queue. */
280 dseg = (__m128i *)txq->wqes;
281 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
283 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
284 txq->elts_comp += pkts_n;
286 /* Request a completion. */
293 /* Fill CTRL in the header. */
294 ctrl = _mm_set_epi32(txq->elts_head, comp_req,
295 txq->qp_num_8s | (pkts_n + 2),
296 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
297 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW);
298 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
299 _mm_store_si128(t_wqe, ctrl);
300 /* Fill ESEG in the header. */
301 _mm_store_si128(t_wqe + 1,
302 _mm_set_epi8(0, 0, 0, 0,
306 #ifdef MLX5_PMD_SOFT_COUNTERS
307 txq->stats.opackets += pkts_n;
309 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
311 /* Ring QP doorbell. */
312 mlx5_tx_dbrec_cond_wmb(txq, wqe, pkts_n < MLX5_VPMD_TX_MAX_BURST);
317 * Store free buffers to RX SW ring.
320 * Pointer to RX queue structure.
322 * Pointer to array of packets to be stored.
324 * Number of packets to be stored.
327 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
329 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
330 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
334 for (pos = 0; pos < p; pos += 2) {
337 mbp = _mm_loadu_si128((__m128i *)&elts[pos]);
338 _mm_storeu_si128((__m128i *)&pkts[pos], mbp);
341 pkts[pos] = elts[pos];
345 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
346 * extracted from the title completion descriptor.
349 * Pointer to RX queue structure.
351 * Pointer to completion array having a compressed completion at first.
353 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
354 * the title completion descriptor to be copied to the rest of mbufs.
357 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
358 struct rte_mbuf **elts)
360 volatile struct mlx5_mini_cqe8 *mcq = (void *)(cq + 1);
361 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
364 unsigned int inv = 0;
365 /* Mask to shuffle from extracted mini CQE to mbuf. */
366 const __m128i shuf_mask1 =
367 _mm_set_epi8(0, 1, 2, 3, /* rss, bswap32 */
368 -1, -1, /* skip vlan_tci */
369 6, 7, /* data_len, bswap16 */
370 -1, -1, 6, 7, /* pkt_len, bswap16 */
371 -1, -1, -1, -1 /* skip packet_type */);
372 const __m128i shuf_mask2 =
373 _mm_set_epi8(8, 9, 10, 11, /* rss, bswap32 */
374 -1, -1, /* skip vlan_tci */
375 14, 15, /* data_len, bswap16 */
376 -1, -1, 14, 15, /* pkt_len, bswap16 */
377 -1, -1, -1, -1 /* skip packet_type */);
378 /* Restore the compressed count. Must be 16 bits. */
379 const uint16_t mcqe_n = t_pkt->data_len +
380 (rxq->crc_present * ETHER_CRC_LEN);
381 const __m128i rearm =
382 _mm_loadu_si128((__m128i *)&t_pkt->rearm_data);
384 _mm_loadu_si128((__m128i *)&t_pkt->rx_descriptor_fields1);
385 const __m128i crc_adj =
386 _mm_set_epi16(0, 0, 0,
387 rxq->crc_present * ETHER_CRC_LEN,
389 rxq->crc_present * ETHER_CRC_LEN,
391 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
392 #ifdef MLX5_PMD_SOFT_COUNTERS
393 const __m128i zero = _mm_setzero_si128();
394 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
395 uint32_t rcvd_byte = 0;
396 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
397 const __m128i len_shuf_mask =
398 _mm_set_epi8(-1, -1, -1, -1,
405 * A. load mCQEs into a 128bit register.
406 * B. store rearm data to mbuf.
407 * C. combine data from mCQEs with rx_descriptor_fields1.
408 * D. store rx_descriptor_fields1.
409 * E. store flow tag (rte_flow mark).
411 for (pos = 0; pos < mcqe_n; ) {
412 __m128i mcqe1, mcqe2;
413 __m128i rxdf1, rxdf2;
414 #ifdef MLX5_PMD_SOFT_COUNTERS
415 __m128i byte_cnt, invalid_mask;
418 if (!(pos & 0x7) && pos + 8 < mcqe_n)
419 rte_prefetch0((void *)(cq + pos + 8));
420 /* A.1 load mCQEs into a 128bit register. */
421 mcqe1 = _mm_loadu_si128((__m128i *)&mcq[pos % 8]);
422 mcqe2 = _mm_loadu_si128((__m128i *)&mcq[pos % 8 + 2]);
423 /* B.1 store rearm data to mbuf. */
424 _mm_storeu_si128((__m128i *)&elts[pos]->rearm_data, rearm);
425 _mm_storeu_si128((__m128i *)&elts[pos + 1]->rearm_data, rearm);
426 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
427 rxdf1 = _mm_shuffle_epi8(mcqe1, shuf_mask1);
428 rxdf2 = _mm_shuffle_epi8(mcqe1, shuf_mask2);
429 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
430 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
431 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
432 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
433 /* D.1 store rx_descriptor_fields1. */
434 _mm_storeu_si128((__m128i *)
435 &elts[pos]->rx_descriptor_fields1,
437 _mm_storeu_si128((__m128i *)
438 &elts[pos + 1]->rx_descriptor_fields1,
440 /* B.1 store rearm data to mbuf. */
441 _mm_storeu_si128((__m128i *)&elts[pos + 2]->rearm_data, rearm);
442 _mm_storeu_si128((__m128i *)&elts[pos + 3]->rearm_data, rearm);
443 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
444 rxdf1 = _mm_shuffle_epi8(mcqe2, shuf_mask1);
445 rxdf2 = _mm_shuffle_epi8(mcqe2, shuf_mask2);
446 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
447 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
448 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
449 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
450 /* D.1 store rx_descriptor_fields1. */
451 _mm_storeu_si128((__m128i *)
452 &elts[pos + 2]->rx_descriptor_fields1,
454 _mm_storeu_si128((__m128i *)
455 &elts[pos + 3]->rx_descriptor_fields1,
457 #ifdef MLX5_PMD_SOFT_COUNTERS
458 invalid_mask = _mm_set_epi64x(0,
460 sizeof(uint16_t) * 8);
461 invalid_mask = _mm_sll_epi64(ones, invalid_mask);
462 mcqe1 = _mm_srli_si128(mcqe1, 4);
463 byte_cnt = _mm_blend_epi16(mcqe1, mcqe2, 0xcc);
464 byte_cnt = _mm_shuffle_epi8(byte_cnt, len_shuf_mask);
465 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
466 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
467 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
470 /* E.1 store flow tag (rte_flow mark). */
471 elts[pos]->hash.fdir.hi = flow_tag;
472 elts[pos + 1]->hash.fdir.hi = flow_tag;
473 elts[pos + 2]->hash.fdir.hi = flow_tag;
474 elts[pos + 3]->hash.fdir.hi = flow_tag;
476 pos += MLX5_VPMD_DESCS_PER_LOOP;
477 /* Move to next CQE and invalidate consumed CQEs. */
478 if (!(pos & 0x7) && pos < mcqe_n) {
479 mcq = (void *)(cq + pos);
480 for (i = 0; i < 8; ++i)
481 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
484 /* Invalidate the rest of CQEs. */
485 for (; inv < mcqe_n; ++inv)
486 cq[inv].op_own = MLX5_CQE_INVALIDATE;
487 #ifdef MLX5_PMD_SOFT_COUNTERS
488 rxq->stats.ipackets += mcqe_n;
489 rxq->stats.ibytes += rcvd_byte;
491 rxq->cq_ci += mcqe_n;
495 * Calculate packet type and offload flag for mbuf and store it.
498 * Pointer to RX queue structure.
500 * Array of four 16bytes completions extracted from the original completion
503 * Opcode vector having responder error status. Each field is 4B.
505 * Pointer to array of packets to be filled.
508 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, __m128i cqes[4],
509 __m128i op_err, struct rte_mbuf **pkts)
511 __m128i pinfo0, pinfo1;
512 __m128i pinfo, ptype;
513 __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH |
514 rxq->hw_timestamp * PKT_RX_TIMESTAMP);
516 const __m128i zero = _mm_setzero_si128();
517 const __m128i ptype_mask =
518 _mm_set_epi32(0xfd06, 0xfd06, 0xfd06, 0xfd06);
519 const __m128i ptype_ol_mask =
520 _mm_set_epi32(0x106, 0x106, 0x106, 0x106);
521 const __m128i pinfo_mask =
522 _mm_set_epi32(0x3, 0x3, 0x3, 0x3);
523 const __m128i cv_flag_sel =
524 _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
525 (uint8_t)((PKT_RX_IP_CKSUM_GOOD |
526 PKT_RX_L4_CKSUM_GOOD) >> 1),
528 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
530 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
531 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
533 const __m128i cv_mask =
534 _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
535 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
536 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
537 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
538 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
539 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
540 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
541 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
542 const __m128i mbuf_init =
543 _mm_loadl_epi64((__m128i *)&rxq->mbuf_initializer);
544 __m128i rearm0, rearm1, rearm2, rearm3;
546 /* Extract pkt_info field. */
547 pinfo0 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
548 pinfo1 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
549 pinfo = _mm_unpacklo_epi64(pinfo0, pinfo1);
550 /* Extract hdr_type_etc field. */
551 pinfo0 = _mm_unpackhi_epi32(cqes[0], cqes[1]);
552 pinfo1 = _mm_unpackhi_epi32(cqes[2], cqes[3]);
553 ptype = _mm_unpacklo_epi64(pinfo0, pinfo1);
555 const __m128i pinfo_ft_mask =
556 _mm_set_epi32(0xffffff00, 0xffffff00,
557 0xffffff00, 0xffffff00);
558 const __m128i fdir_flags = _mm_set1_epi32(PKT_RX_FDIR);
559 __m128i fdir_id_flags = _mm_set1_epi32(PKT_RX_FDIR_ID);
560 __m128i flow_tag, invalid_mask;
562 flow_tag = _mm_and_si128(pinfo, pinfo_ft_mask);
563 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
564 invalid_mask = _mm_cmpeq_epi32(flow_tag, zero);
565 ol_flags = _mm_or_si128(ol_flags,
566 _mm_andnot_si128(invalid_mask,
568 /* Mask out invalid entries. */
569 fdir_id_flags = _mm_andnot_si128(invalid_mask, fdir_id_flags);
570 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
571 ol_flags = _mm_or_si128(ol_flags,
573 _mm_cmpeq_epi32(flow_tag,
578 * Merge the two fields to generate the following:
582 * bit[11:10] = l3_hdr_type
583 * bit[14:12] = l4_hdr_type
586 * bit[17] = outer_l3_type
588 ptype = _mm_and_si128(ptype, ptype_mask);
589 pinfo = _mm_and_si128(pinfo, pinfo_mask);
590 pinfo = _mm_slli_epi32(pinfo, 16);
591 /* Make pinfo has merged fields for ol_flags calculation. */
592 pinfo = _mm_or_si128(ptype, pinfo);
593 ptype = _mm_srli_epi32(pinfo, 10);
594 ptype = _mm_packs_epi32(ptype, zero);
595 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
596 op_err = _mm_srli_epi16(op_err, 8);
597 ptype = _mm_or_si128(ptype, op_err);
598 pkts[0]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 0)];
599 pkts[1]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 2)];
600 pkts[2]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 4)];
601 pkts[3]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 6)];
602 /* Fill flags for checksum and VLAN. */
603 pinfo = _mm_and_si128(pinfo, ptype_ol_mask);
604 pinfo = _mm_shuffle_epi8(cv_flag_sel, pinfo);
605 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
606 cv_flags = _mm_slli_epi32(pinfo, 9);
607 cv_flags = _mm_or_si128(pinfo, cv_flags);
608 /* Move back flags to start from byte[0]. */
609 cv_flags = _mm_srli_epi32(cv_flags, 8);
610 /* Mask out garbage bits. */
611 cv_flags = _mm_and_si128(cv_flags, cv_mask);
612 /* Merge to ol_flags. */
613 ol_flags = _mm_or_si128(ol_flags, cv_flags);
614 /* Merge mbuf_init and ol_flags. */
615 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 8), 0x30);
616 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 4), 0x30);
617 rearm2 = _mm_blend_epi16(mbuf_init, ol_flags, 0x30);
618 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(ol_flags, 4), 0x30);
619 /* Write 8B rearm_data and 8B ol_flags. */
620 _mm_store_si128((__m128i *)&pkts[0]->rearm_data, rearm0);
621 _mm_store_si128((__m128i *)&pkts[1]->rearm_data, rearm1);
622 _mm_store_si128((__m128i *)&pkts[2]->rearm_data, rearm2);
623 _mm_store_si128((__m128i *)&pkts[3]->rearm_data, rearm3);
627 * Receive burst of packets. An errored completion also consumes a mbuf, but the
628 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
629 * before returning to application.
632 * Pointer to RX queue structure.
634 * Array to store received packets.
636 * Maximum number of packets in array.
638 * Pointer to a flag. Set non-zero value if pkts array has at least one error
642 * Number of packets received including errors (<= pkts_n).
644 static inline uint16_t
645 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
648 const uint16_t q_n = 1 << rxq->cqe_n;
649 const uint16_t q_mask = q_n - 1;
650 volatile struct mlx5_cqe *cq;
651 struct rte_mbuf **elts;
655 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
656 uint16_t nocmp_n = 0;
657 uint16_t rcvd_pkt = 0;
658 unsigned int cq_idx = rxq->cq_ci & q_mask;
659 unsigned int elts_idx;
660 unsigned int ownership = !!(rxq->cq_ci & (q_mask + 1));
661 const __m128i owner_check =
662 _mm_set_epi64x(0x0100000001000000LL, 0x0100000001000000LL);
663 const __m128i opcode_check =
664 _mm_set_epi64x(0xf0000000f0000000LL, 0xf0000000f0000000LL);
665 const __m128i format_check =
666 _mm_set_epi64x(0x0c0000000c000000LL, 0x0c0000000c000000LL);
667 const __m128i resp_err_check =
668 _mm_set_epi64x(0xe0000000e0000000LL, 0xe0000000e0000000LL);
669 #ifdef MLX5_PMD_SOFT_COUNTERS
670 uint32_t rcvd_byte = 0;
671 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
672 const __m128i len_shuf_mask =
673 _mm_set_epi8(-1, -1, -1, -1,
678 /* Mask to shuffle from extracted CQE to mbuf. */
679 const __m128i shuf_mask =
680 _mm_set_epi8(-1, 3, 2, 1, /* fdir.hi */
681 12, 13, 14, 15, /* rss, bswap32 */
682 10, 11, /* vlan_tci, bswap16 */
683 4, 5, /* data_len, bswap16 */
684 -1, -1, /* zero out 2nd half of pkt_len */
685 4, 5 /* pkt_len, bswap16 */);
686 /* Mask to blend from the last Qword to the first DQword. */
687 const __m128i blend_mask =
688 _mm_set_epi8(-1, -1, -1, -1,
692 const __m128i zero = _mm_setzero_si128();
693 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
694 const __m128i crc_adj =
695 _mm_set_epi16(0, 0, 0, 0, 0,
696 rxq->crc_present * ETHER_CRC_LEN,
698 rxq->crc_present * ETHER_CRC_LEN);
699 const __m128i flow_mark_adj = _mm_set_epi32(rxq->mark * (-1), 0, 0, 0);
701 assert(rxq->sges_n == 0);
702 assert(rxq->cqe_n == rxq->elts_n);
703 cq = &(*rxq->cqes)[cq_idx];
705 rte_prefetch0(cq + 1);
706 rte_prefetch0(cq + 2);
707 rte_prefetch0(cq + 3);
708 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
711 * rq_ci >= cq_ci >= rq_pi
712 * Definition of indexes:
713 * rq_ci - cq_ci := # of buffers owned by HW (posted).
714 * cq_ci - rq_pi := # of buffers not returned to app (decompressed).
715 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished).
717 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
718 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH)
719 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
720 /* See if there're unreturned mbufs from compressed CQE. */
721 rcvd_pkt = rxq->cq_ci - rxq->rq_pi;
723 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
724 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
725 rxq->rq_pi += rcvd_pkt;
728 elts_idx = rxq->rq_pi & q_mask;
729 elts = &(*rxq->elts)[elts_idx];
730 /* Not to overflow pkts array. */
731 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
732 /* Not to cross queue end. */
733 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
736 /* At this point, there shouldn't be any remained packets. */
737 assert(rxq->rq_pi == rxq->cq_ci);
739 * A. load first Qword (8bytes) in one loop.
740 * B. copy 4 mbuf pointers from elts ring to returing pkts.
741 * C. load remained CQE data and extract necessary fields.
742 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
743 * following structure:
746 * uint8_t flow_tag[3];
750 * uint16_t hdr_type_etc;
751 * uint16_t vlan_info;
752 * uint32_t rx_has_res;
756 * F. find compressed CQE.
760 pos += MLX5_VPMD_DESCS_PER_LOOP) {
761 __m128i cqes[MLX5_VPMD_DESCS_PER_LOOP];
762 __m128i cqe_tmp1, cqe_tmp2;
763 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
764 __m128i op_own, op_own_tmp1, op_own_tmp2;
765 __m128i opcode, owner_mask, invalid_mask;
768 #ifdef MLX5_PMD_SOFT_COUNTERS
772 __m128i p = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0);
773 unsigned int p1, p2, p3;
775 /* Prefetch next 4 CQEs. */
776 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
777 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP]);
778 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 1]);
779 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 2]);
780 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 3]);
782 /* A.0 do not cross the end of CQ. */
783 mask = _mm_set_epi64x(0, (pkts_n - pos) * sizeof(uint16_t) * 8);
784 mask = _mm_sll_epi64(ones, mask);
785 p = _mm_andnot_si128(mask, p);
787 p3 = _mm_extract_epi16(p, 3);
788 cqes[3] = _mm_loadl_epi64((__m128i *)
789 &cq[pos + p3].sop_drop_qpn);
790 rte_compiler_barrier();
791 p2 = _mm_extract_epi16(p, 2);
792 cqes[2] = _mm_loadl_epi64((__m128i *)
793 &cq[pos + p2].sop_drop_qpn);
794 rte_compiler_barrier();
795 /* B.1 load mbuf pointers. */
796 mbp1 = _mm_loadu_si128((__m128i *)&elts[pos]);
797 mbp2 = _mm_loadu_si128((__m128i *)&elts[pos + 2]);
798 /* A.1 load a block having op_own. */
799 p1 = _mm_extract_epi16(p, 1);
800 cqes[1] = _mm_loadl_epi64((__m128i *)
801 &cq[pos + p1].sop_drop_qpn);
802 rte_compiler_barrier();
803 cqes[0] = _mm_loadl_epi64((__m128i *)
804 &cq[pos].sop_drop_qpn);
805 /* B.2 copy mbuf pointers. */
806 _mm_storeu_si128((__m128i *)&pkts[pos], mbp1);
807 _mm_storeu_si128((__m128i *)&pkts[pos + 2], mbp2);
809 /* C.1 load remained CQE data and extract necessary fields. */
810 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p3]);
811 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos + p2]);
812 cqes[3] = _mm_blendv_epi8(cqes[3], cqe_tmp2, blend_mask);
813 cqes[2] = _mm_blendv_epi8(cqes[2], cqe_tmp1, blend_mask);
814 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p3].rsvd1[3]);
815 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos + p2].rsvd1[3]);
816 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x30);
817 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x30);
818 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p3].rsvd2[10]);
819 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos + p2].rsvd2[10]);
820 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x04);
821 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x04);
822 /* C.2 generate final structure for mbuf with swapping bytes. */
823 pkt_mb3 = _mm_shuffle_epi8(cqes[3], shuf_mask);
824 pkt_mb2 = _mm_shuffle_epi8(cqes[2], shuf_mask);
825 /* C.3 adjust CRC length. */
826 pkt_mb3 = _mm_sub_epi16(pkt_mb3, crc_adj);
827 pkt_mb2 = _mm_sub_epi16(pkt_mb2, crc_adj);
828 /* C.4 adjust flow mark. */
829 pkt_mb3 = _mm_add_epi32(pkt_mb3, flow_mark_adj);
830 pkt_mb2 = _mm_add_epi32(pkt_mb2, flow_mark_adj);
831 /* D.1 fill in mbuf - rx_descriptor_fields1. */
832 _mm_storeu_si128((void *)&pkts[pos + 3]->pkt_len, pkt_mb3);
833 _mm_storeu_si128((void *)&pkts[pos + 2]->pkt_len, pkt_mb2);
834 /* E.1 extract op_own field. */
835 op_own_tmp2 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
836 /* C.1 load remained CQE data and extract necessary fields. */
837 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p1]);
838 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos]);
839 cqes[1] = _mm_blendv_epi8(cqes[1], cqe_tmp2, blend_mask);
840 cqes[0] = _mm_blendv_epi8(cqes[0], cqe_tmp1, blend_mask);
841 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p1].rsvd1[3]);
842 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos].rsvd1[3]);
843 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x30);
844 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x30);
845 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p1].rsvd2[10]);
846 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos].rsvd2[10]);
847 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x04);
848 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x04);
849 /* C.2 generate final structure for mbuf with swapping bytes. */
850 pkt_mb1 = _mm_shuffle_epi8(cqes[1], shuf_mask);
851 pkt_mb0 = _mm_shuffle_epi8(cqes[0], shuf_mask);
852 /* C.3 adjust CRC length. */
853 pkt_mb1 = _mm_sub_epi16(pkt_mb1, crc_adj);
854 pkt_mb0 = _mm_sub_epi16(pkt_mb0, crc_adj);
855 /* C.4 adjust flow mark. */
856 pkt_mb1 = _mm_add_epi32(pkt_mb1, flow_mark_adj);
857 pkt_mb0 = _mm_add_epi32(pkt_mb0, flow_mark_adj);
858 /* E.1 extract op_own byte. */
859 op_own_tmp1 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
860 op_own = _mm_unpackhi_epi64(op_own_tmp1, op_own_tmp2);
861 /* D.1 fill in mbuf - rx_descriptor_fields1. */
862 _mm_storeu_si128((void *)&pkts[pos + 1]->pkt_len, pkt_mb1);
863 _mm_storeu_si128((void *)&pkts[pos]->pkt_len, pkt_mb0);
864 /* E.2 flip owner bit to mark CQEs from last round. */
865 owner_mask = _mm_and_si128(op_own, owner_check);
867 owner_mask = _mm_xor_si128(owner_mask, owner_check);
868 owner_mask = _mm_cmpeq_epi32(owner_mask, owner_check);
869 owner_mask = _mm_packs_epi32(owner_mask, zero);
870 /* E.3 get mask for invalidated CQEs. */
871 opcode = _mm_and_si128(op_own, opcode_check);
872 invalid_mask = _mm_cmpeq_epi32(opcode_check, opcode);
873 invalid_mask = _mm_packs_epi32(invalid_mask, zero);
874 /* E.4 mask out beyond boundary. */
875 invalid_mask = _mm_or_si128(invalid_mask, mask);
876 /* E.5 merge invalid_mask with invalid owner. */
877 invalid_mask = _mm_or_si128(invalid_mask, owner_mask);
878 /* F.1 find compressed CQE format. */
879 comp_mask = _mm_and_si128(op_own, format_check);
880 comp_mask = _mm_cmpeq_epi32(comp_mask, format_check);
881 comp_mask = _mm_packs_epi32(comp_mask, zero);
882 /* F.2 mask out invalid entries. */
883 comp_mask = _mm_andnot_si128(invalid_mask, comp_mask);
884 comp_idx = _mm_cvtsi128_si64(comp_mask);
885 /* F.3 get the first compressed CQE. */
886 comp_idx = comp_idx ?
887 __builtin_ctzll(comp_idx) /
888 (sizeof(uint16_t) * 8) :
889 MLX5_VPMD_DESCS_PER_LOOP;
890 /* E.6 mask out entries after the compressed CQE. */
891 mask = _mm_set_epi64x(0, comp_idx * sizeof(uint16_t) * 8);
892 mask = _mm_sll_epi64(ones, mask);
893 invalid_mask = _mm_or_si128(invalid_mask, mask);
894 /* E.7 count non-compressed valid CQEs. */
895 n = _mm_cvtsi128_si64(invalid_mask);
896 n = n ? __builtin_ctzll(n) / (sizeof(uint16_t) * 8) :
897 MLX5_VPMD_DESCS_PER_LOOP;
899 /* D.2 get the final invalid mask. */
900 mask = _mm_set_epi64x(0, n * sizeof(uint16_t) * 8);
901 mask = _mm_sll_epi64(ones, mask);
902 invalid_mask = _mm_or_si128(invalid_mask, mask);
903 /* D.3 check error in opcode. */
904 opcode = _mm_cmpeq_epi32(resp_err_check, opcode);
905 opcode = _mm_packs_epi32(opcode, zero);
906 opcode = _mm_andnot_si128(invalid_mask, opcode);
907 /* D.4 mark if any error is set */
908 *err |= _mm_cvtsi128_si64(opcode);
909 /* D.5 fill in mbuf - rearm_data and packet_type. */
910 rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
911 if (rxq->hw_timestamp) {
912 pkts[pos]->timestamp =
913 rte_be_to_cpu_64(cq[pos].timestamp);
914 pkts[pos + 1]->timestamp =
915 rte_be_to_cpu_64(cq[pos + p1].timestamp);
916 pkts[pos + 2]->timestamp =
917 rte_be_to_cpu_64(cq[pos + p2].timestamp);
918 pkts[pos + 3]->timestamp =
919 rte_be_to_cpu_64(cq[pos + p3].timestamp);
921 #ifdef MLX5_PMD_SOFT_COUNTERS
922 /* Add up received bytes count. */
923 byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);
924 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
925 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
926 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
929 * Break the loop unless more valid CQE is expected, or if
930 * there's a compressed CQE.
932 if (n != MLX5_VPMD_DESCS_PER_LOOP)
935 /* If no new CQE seen, return without updating cq_db. */
936 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
938 /* Update the consumer indexes for non-compressed CQEs. */
939 assert(nocmp_n <= pkts_n);
940 rxq->cq_ci += nocmp_n;
941 rxq->rq_pi += nocmp_n;
943 #ifdef MLX5_PMD_SOFT_COUNTERS
944 rxq->stats.ipackets += nocmp_n;
945 rxq->stats.ibytes += rcvd_byte;
947 /* Decompress the last CQE if compressed. */
948 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
949 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
950 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);
951 /* Return more packets if needed. */
952 if (nocmp_n < pkts_n) {
953 uint16_t n = rxq->cq_ci - rxq->rq_pi;
955 n = RTE_MIN(n, pkts_n - nocmp_n);
956 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
961 rte_compiler_barrier();
962 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
966 #endif /* RTE_PMD_MLX5_RXTX_VEC_SSE_H_ */