1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_VEC_SSE_H_
7 #define RTE_PMD_MLX5_RXTX_VEC_SSE_H_
12 #include <smmintrin.h>
15 #include <rte_mempool.h>
16 #include <rte_prefetch.h>
20 #include "mlx5_defs.h"
22 #include "mlx5_utils.h"
23 #include "mlx5_rxtx.h"
24 #include "mlx5_rxtx_vec.h"
25 #include "mlx5_autoconf.h"
27 #ifndef __INTEL_COMPILER
28 #pragma GCC diagnostic ignored "-Wcast-qual"
32 * Store free buffers to RX SW ring.
35 * Pointer to RX queue structure.
37 * Pointer to array of packets to be stored.
39 * Number of packets to be stored.
42 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
44 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
45 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
49 for (pos = 0; pos < p; pos += 2) {
52 mbp = _mm_loadu_si128((__m128i *)&elts[pos]);
53 _mm_storeu_si128((__m128i *)&pkts[pos], mbp);
56 pkts[pos] = elts[pos];
60 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
61 * extracted from the title completion descriptor.
64 * Pointer to RX queue structure.
66 * Pointer to completion array having a compressed completion at first.
68 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
69 * the title completion descriptor to be copied to the rest of mbufs.
72 * Number of mini-CQEs successfully decompressed.
74 static inline uint16_t
75 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
76 struct rte_mbuf **elts)
78 volatile struct mlx5_mini_cqe8 *mcq = (void *)(cq + 1);
79 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
83 /* Mask to shuffle from extracted mini CQE to mbuf. */
84 const __m128i shuf_mask1 =
85 _mm_set_epi8(0, 1, 2, 3, /* rss, bswap32 */
86 -1, -1, /* skip vlan_tci */
87 6, 7, /* data_len, bswap16 */
88 -1, -1, 6, 7, /* pkt_len, bswap16 */
89 -1, -1, -1, -1 /* skip packet_type */);
90 const __m128i shuf_mask2 =
91 _mm_set_epi8(8, 9, 10, 11, /* rss, bswap32 */
92 -1, -1, /* skip vlan_tci */
93 14, 15, /* data_len, bswap16 */
94 -1, -1, 14, 15, /* pkt_len, bswap16 */
95 -1, -1, -1, -1 /* skip packet_type */);
96 /* Restore the compressed count. Must be 16 bits. */
97 const uint16_t mcqe_n = t_pkt->data_len +
98 (rxq->crc_present * RTE_ETHER_CRC_LEN);
100 _mm_loadu_si128((__m128i *)&t_pkt->rearm_data);
102 _mm_loadu_si128((__m128i *)&t_pkt->rx_descriptor_fields1);
103 const __m128i crc_adj =
104 _mm_set_epi16(0, 0, 0,
105 rxq->crc_present * RTE_ETHER_CRC_LEN,
107 rxq->crc_present * RTE_ETHER_CRC_LEN,
109 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
110 #ifdef MLX5_PMD_SOFT_COUNTERS
111 const __m128i zero = _mm_setzero_si128();
112 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
113 uint32_t rcvd_byte = 0;
114 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
115 const __m128i len_shuf_mask =
116 _mm_set_epi8(-1, -1, -1, -1,
122 * A. load mCQEs into a 128bit register.
123 * B. store rearm data to mbuf.
124 * C. combine data from mCQEs with rx_descriptor_fields1.
125 * D. store rx_descriptor_fields1.
126 * E. store flow tag (rte_flow mark).
128 for (pos = 0; pos < mcqe_n; ) {
129 __m128i mcqe1, mcqe2;
130 __m128i rxdf1, rxdf2;
131 #ifdef MLX5_PMD_SOFT_COUNTERS
132 __m128i byte_cnt, invalid_mask;
135 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
136 if (likely(pos + i < mcqe_n))
137 rte_prefetch0((void *)(cq + pos + i));
139 /* A.1 load mCQEs into a 128bit register. */
140 mcqe1 = _mm_loadu_si128((__m128i *)&mcq[pos % 8]);
141 mcqe2 = _mm_loadu_si128((__m128i *)&mcq[pos % 8 + 2]);
142 /* B.1 store rearm data to mbuf. */
143 _mm_storeu_si128((__m128i *)&elts[pos]->rearm_data, rearm);
144 _mm_storeu_si128((__m128i *)&elts[pos + 1]->rearm_data, rearm);
145 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
146 rxdf1 = _mm_shuffle_epi8(mcqe1, shuf_mask1);
147 rxdf2 = _mm_shuffle_epi8(mcqe1, shuf_mask2);
148 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
149 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
150 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
151 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
152 /* D.1 store rx_descriptor_fields1. */
153 _mm_storeu_si128((__m128i *)
154 &elts[pos]->rx_descriptor_fields1,
156 _mm_storeu_si128((__m128i *)
157 &elts[pos + 1]->rx_descriptor_fields1,
159 /* B.1 store rearm data to mbuf. */
160 _mm_storeu_si128((__m128i *)&elts[pos + 2]->rearm_data, rearm);
161 _mm_storeu_si128((__m128i *)&elts[pos + 3]->rearm_data, rearm);
162 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
163 rxdf1 = _mm_shuffle_epi8(mcqe2, shuf_mask1);
164 rxdf2 = _mm_shuffle_epi8(mcqe2, shuf_mask2);
165 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
166 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
167 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
168 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
169 /* D.1 store rx_descriptor_fields1. */
170 _mm_storeu_si128((__m128i *)
171 &elts[pos + 2]->rx_descriptor_fields1,
173 _mm_storeu_si128((__m128i *)
174 &elts[pos + 3]->rx_descriptor_fields1,
176 #ifdef MLX5_PMD_SOFT_COUNTERS
177 invalid_mask = _mm_set_epi64x(0,
179 sizeof(uint16_t) * 8);
180 invalid_mask = _mm_sll_epi64(ones, invalid_mask);
181 mcqe1 = _mm_srli_si128(mcqe1, 4);
182 byte_cnt = _mm_blend_epi16(mcqe1, mcqe2, 0xcc);
183 byte_cnt = _mm_shuffle_epi8(byte_cnt, len_shuf_mask);
184 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
185 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
186 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
189 /* E.1 store flow tag (rte_flow mark). */
190 elts[pos]->hash.fdir.hi = flow_tag;
191 elts[pos + 1]->hash.fdir.hi = flow_tag;
192 elts[pos + 2]->hash.fdir.hi = flow_tag;
193 elts[pos + 3]->hash.fdir.hi = flow_tag;
195 if (rxq->dynf_meta) {
196 int32_t offs = rxq->flow_meta_offset;
197 const uint32_t meta =
198 *RTE_MBUF_DYNFIELD(t_pkt, offs, uint32_t *);
200 /* Check if title packet has valid metadata. */
202 MLX5_ASSERT(t_pkt->ol_flags & offs);
203 *RTE_MBUF_DYNFIELD(elts[pos], offs,
205 *RTE_MBUF_DYNFIELD(elts[pos + 1], offs,
207 *RTE_MBUF_DYNFIELD(elts[pos + 2], offs,
209 *RTE_MBUF_DYNFIELD(elts[pos + 3], offs,
213 pos += MLX5_VPMD_DESCS_PER_LOOP;
214 /* Move to next CQE and invalidate consumed CQEs. */
215 if (!(pos & 0x7) && pos < mcqe_n) {
216 mcq = (void *)(cq + pos);
217 for (i = 0; i < 8; ++i)
218 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
221 /* Invalidate the rest of CQEs. */
222 for (; inv < mcqe_n; ++inv)
223 cq[inv].op_own = MLX5_CQE_INVALIDATE;
224 #ifdef MLX5_PMD_SOFT_COUNTERS
225 rxq->stats.ipackets += mcqe_n;
226 rxq->stats.ibytes += rcvd_byte;
228 rxq->cq_ci += mcqe_n;
233 * Calculate packet type and offload flag for mbuf and store it.
236 * Pointer to RX queue structure.
238 * Array of four 16bytes completions extracted from the original completion
241 * Opcode vector having responder error status. Each field is 4B.
243 * Pointer to array of packets to be filled.
246 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, __m128i cqes[4],
247 __m128i op_err, struct rte_mbuf **pkts)
249 __m128i pinfo0, pinfo1;
250 __m128i pinfo, ptype;
251 __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH |
252 rxq->hw_timestamp * PKT_RX_TIMESTAMP);
254 const __m128i zero = _mm_setzero_si128();
255 const __m128i ptype_mask =
256 _mm_set_epi32(0xfd06, 0xfd06, 0xfd06, 0xfd06);
257 const __m128i ptype_ol_mask =
258 _mm_set_epi32(0x106, 0x106, 0x106, 0x106);
259 const __m128i pinfo_mask =
260 _mm_set_epi32(0x3, 0x3, 0x3, 0x3);
261 const __m128i cv_flag_sel =
262 _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
263 (uint8_t)((PKT_RX_IP_CKSUM_GOOD |
264 PKT_RX_L4_CKSUM_GOOD) >> 1),
266 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
268 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
269 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
271 const __m128i cv_mask =
272 _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
273 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
274 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
275 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
276 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
277 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
278 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
279 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
280 const __m128i mbuf_init =
281 _mm_load_si128((__m128i *)&rxq->mbuf_initializer);
282 __m128i rearm0, rearm1, rearm2, rearm3;
283 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3;
285 /* Extract pkt_info field. */
286 pinfo0 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
287 pinfo1 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
288 pinfo = _mm_unpacklo_epi64(pinfo0, pinfo1);
289 /* Extract hdr_type_etc field. */
290 pinfo0 = _mm_unpackhi_epi32(cqes[0], cqes[1]);
291 pinfo1 = _mm_unpackhi_epi32(cqes[2], cqes[3]);
292 ptype = _mm_unpacklo_epi64(pinfo0, pinfo1);
294 const __m128i pinfo_ft_mask =
295 _mm_set_epi32(0xffffff00, 0xffffff00,
296 0xffffff00, 0xffffff00);
297 const __m128i fdir_flags = _mm_set1_epi32(PKT_RX_FDIR);
298 __m128i fdir_id_flags = _mm_set1_epi32(PKT_RX_FDIR_ID);
299 __m128i flow_tag, invalid_mask;
301 flow_tag = _mm_and_si128(pinfo, pinfo_ft_mask);
302 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
303 invalid_mask = _mm_cmpeq_epi32(flow_tag, zero);
304 ol_flags = _mm_or_si128(ol_flags,
305 _mm_andnot_si128(invalid_mask,
307 /* Mask out invalid entries. */
308 fdir_id_flags = _mm_andnot_si128(invalid_mask, fdir_id_flags);
309 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
310 ol_flags = _mm_or_si128(ol_flags,
312 _mm_cmpeq_epi32(flow_tag,
317 * Merge the two fields to generate the following:
321 * bit[11:10] = l3_hdr_type
322 * bit[14:12] = l4_hdr_type
325 * bit[17] = outer_l3_type
327 ptype = _mm_and_si128(ptype, ptype_mask);
328 pinfo = _mm_and_si128(pinfo, pinfo_mask);
329 pinfo = _mm_slli_epi32(pinfo, 16);
330 /* Make pinfo has merged fields for ol_flags calculation. */
331 pinfo = _mm_or_si128(ptype, pinfo);
332 ptype = _mm_srli_epi32(pinfo, 10);
333 ptype = _mm_packs_epi32(ptype, zero);
334 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
335 op_err = _mm_srli_epi16(op_err, 8);
336 ptype = _mm_or_si128(ptype, op_err);
337 pt_idx0 = _mm_extract_epi8(ptype, 0);
338 pt_idx1 = _mm_extract_epi8(ptype, 2);
339 pt_idx2 = _mm_extract_epi8(ptype, 4);
340 pt_idx3 = _mm_extract_epi8(ptype, 6);
341 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] |
342 !!(pt_idx0 & (1 << 6)) * rxq->tunnel;
343 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] |
344 !!(pt_idx1 & (1 << 6)) * rxq->tunnel;
345 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] |
346 !!(pt_idx2 & (1 << 6)) * rxq->tunnel;
347 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] |
348 !!(pt_idx3 & (1 << 6)) * rxq->tunnel;
349 /* Fill flags for checksum and VLAN. */
350 pinfo = _mm_and_si128(pinfo, ptype_ol_mask);
351 pinfo = _mm_shuffle_epi8(cv_flag_sel, pinfo);
352 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
353 cv_flags = _mm_slli_epi32(pinfo, 9);
354 cv_flags = _mm_or_si128(pinfo, cv_flags);
355 /* Move back flags to start from byte[0]. */
356 cv_flags = _mm_srli_epi32(cv_flags, 8);
357 /* Mask out garbage bits. */
358 cv_flags = _mm_and_si128(cv_flags, cv_mask);
359 /* Merge to ol_flags. */
360 ol_flags = _mm_or_si128(ol_flags, cv_flags);
361 /* Merge mbuf_init and ol_flags. */
362 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 8), 0x30);
363 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 4), 0x30);
364 rearm2 = _mm_blend_epi16(mbuf_init, ol_flags, 0x30);
365 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(ol_flags, 4), 0x30);
366 /* Write 8B rearm_data and 8B ol_flags. */
367 _mm_store_si128((__m128i *)&pkts[0]->rearm_data, rearm0);
368 _mm_store_si128((__m128i *)&pkts[1]->rearm_data, rearm1);
369 _mm_store_si128((__m128i *)&pkts[2]->rearm_data, rearm2);
370 _mm_store_si128((__m128i *)&pkts[3]->rearm_data, rearm3);
374 * Receive burst of packets. An errored completion also consumes a mbuf, but the
375 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
376 * before returning to application.
379 * Pointer to RX queue structure.
381 * Array to store received packets.
383 * Maximum number of packets in array.
385 * Pointer to a flag. Set non-zero value if pkts array has at least one error
389 * Number of packets received including errors (<= pkts_n).
391 static inline uint16_t
392 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
395 const uint16_t q_n = 1 << rxq->cqe_n;
396 const uint16_t q_mask = q_n - 1;
397 volatile struct mlx5_cqe *cq;
398 struct rte_mbuf **elts;
402 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
403 uint16_t nocmp_n = 0;
404 uint16_t rcvd_pkt = 0;
405 unsigned int cq_idx = rxq->cq_ci & q_mask;
406 unsigned int elts_idx;
407 unsigned int ownership = !!(rxq->cq_ci & (q_mask + 1));
408 const __m128i owner_check =
409 _mm_set_epi64x(0x0100000001000000LL, 0x0100000001000000LL);
410 const __m128i opcode_check =
411 _mm_set_epi64x(0xf0000000f0000000LL, 0xf0000000f0000000LL);
412 const __m128i format_check =
413 _mm_set_epi64x(0x0c0000000c000000LL, 0x0c0000000c000000LL);
414 const __m128i resp_err_check =
415 _mm_set_epi64x(0xe0000000e0000000LL, 0xe0000000e0000000LL);
416 #ifdef MLX5_PMD_SOFT_COUNTERS
417 uint32_t rcvd_byte = 0;
418 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
419 const __m128i len_shuf_mask =
420 _mm_set_epi8(-1, -1, -1, -1,
425 /* Mask to shuffle from extracted CQE to mbuf. */
426 const __m128i shuf_mask =
427 _mm_set_epi8(-1, 3, 2, 1, /* fdir.hi */
428 12, 13, 14, 15, /* rss, bswap32 */
429 10, 11, /* vlan_tci, bswap16 */
430 4, 5, /* data_len, bswap16 */
431 -1, -1, /* zero out 2nd half of pkt_len */
432 4, 5 /* pkt_len, bswap16 */);
433 /* Mask to blend from the last Qword to the first DQword. */
434 const __m128i blend_mask =
435 _mm_set_epi8(-1, -1, -1, -1,
439 const __m128i zero = _mm_setzero_si128();
440 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
441 const __m128i crc_adj =
442 _mm_set_epi16(0, 0, 0, 0, 0,
443 rxq->crc_present * RTE_ETHER_CRC_LEN,
445 rxq->crc_present * RTE_ETHER_CRC_LEN);
446 const __m128i flow_mark_adj = _mm_set_epi32(rxq->mark * (-1), 0, 0, 0);
448 MLX5_ASSERT(rxq->sges_n == 0);
449 MLX5_ASSERT(rxq->cqe_n == rxq->elts_n);
450 cq = &(*rxq->cqes)[cq_idx];
452 rte_prefetch0(cq + 1);
453 rte_prefetch0(cq + 2);
454 rte_prefetch0(cq + 3);
455 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
456 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
457 if (repl_n >= rxq->rq_repl_thresh)
458 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
459 /* See if there're unreturned mbufs from compressed CQE. */
460 rcvd_pkt = rxq->decompressed;
462 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
463 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
464 rxq->rq_pi += rcvd_pkt;
465 rxq->decompressed -= rcvd_pkt;
468 elts_idx = rxq->rq_pi & q_mask;
469 elts = &(*rxq->elts)[elts_idx];
470 /* Not to overflow pkts array. */
471 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
472 /* Not to cross queue end. */
473 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
474 pkts_n = RTE_MIN(pkts_n, q_n - cq_idx);
477 /* At this point, there shouldn't be any remained packets. */
478 MLX5_ASSERT(rxq->decompressed == 0);
480 * A. load first Qword (8bytes) in one loop.
481 * B. copy 4 mbuf pointers from elts ring to returing pkts.
482 * C. load remained CQE data and extract necessary fields.
483 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
484 * following structure:
487 * uint8_t flow_tag[3];
491 * uint16_t hdr_type_etc;
492 * uint16_t vlan_info;
493 * uint32_t rx_has_res;
497 * F. find compressed CQE.
501 pos += MLX5_VPMD_DESCS_PER_LOOP) {
502 __m128i cqes[MLX5_VPMD_DESCS_PER_LOOP];
503 __m128i cqe_tmp1, cqe_tmp2;
504 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
505 __m128i op_own, op_own_tmp1, op_own_tmp2;
506 __m128i opcode, owner_mask, invalid_mask;
509 #ifdef MLX5_PMD_SOFT_COUNTERS
513 __m128i p = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0);
514 unsigned int p1, p2, p3;
516 /* Prefetch next 4 CQEs. */
517 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
518 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP]);
519 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 1]);
520 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 2]);
521 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 3]);
523 /* A.0 do not cross the end of CQ. */
524 mask = _mm_set_epi64x(0, (pkts_n - pos) * sizeof(uint16_t) * 8);
525 mask = _mm_sll_epi64(ones, mask);
526 p = _mm_andnot_si128(mask, p);
528 p3 = _mm_extract_epi16(p, 3);
529 cqes[3] = _mm_loadl_epi64((__m128i *)
530 &cq[pos + p3].sop_drop_qpn);
531 rte_compiler_barrier();
532 p2 = _mm_extract_epi16(p, 2);
533 cqes[2] = _mm_loadl_epi64((__m128i *)
534 &cq[pos + p2].sop_drop_qpn);
535 rte_compiler_barrier();
536 /* B.1 load mbuf pointers. */
537 mbp1 = _mm_loadu_si128((__m128i *)&elts[pos]);
538 mbp2 = _mm_loadu_si128((__m128i *)&elts[pos + 2]);
539 /* A.1 load a block having op_own. */
540 p1 = _mm_extract_epi16(p, 1);
541 cqes[1] = _mm_loadl_epi64((__m128i *)
542 &cq[pos + p1].sop_drop_qpn);
543 rte_compiler_barrier();
544 cqes[0] = _mm_loadl_epi64((__m128i *)
545 &cq[pos].sop_drop_qpn);
546 /* B.2 copy mbuf pointers. */
547 _mm_storeu_si128((__m128i *)&pkts[pos], mbp1);
548 _mm_storeu_si128((__m128i *)&pkts[pos + 2], mbp2);
550 /* C.1 load remained CQE data and extract necessary fields. */
551 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p3]);
552 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos + p2]);
553 cqes[3] = _mm_blendv_epi8(cqes[3], cqe_tmp2, blend_mask);
554 cqes[2] = _mm_blendv_epi8(cqes[2], cqe_tmp1, blend_mask);
555 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p3].csum);
556 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos + p2].csum);
557 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x30);
558 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x30);
559 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p3].rsvd4[2]);
560 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos + p2].rsvd4[2]);
561 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x04);
562 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x04);
563 /* C.2 generate final structure for mbuf with swapping bytes. */
564 pkt_mb3 = _mm_shuffle_epi8(cqes[3], shuf_mask);
565 pkt_mb2 = _mm_shuffle_epi8(cqes[2], shuf_mask);
566 /* C.3 adjust CRC length. */
567 pkt_mb3 = _mm_sub_epi16(pkt_mb3, crc_adj);
568 pkt_mb2 = _mm_sub_epi16(pkt_mb2, crc_adj);
569 /* C.4 adjust flow mark. */
570 pkt_mb3 = _mm_add_epi32(pkt_mb3, flow_mark_adj);
571 pkt_mb2 = _mm_add_epi32(pkt_mb2, flow_mark_adj);
572 /* D.1 fill in mbuf - rx_descriptor_fields1. */
573 _mm_storeu_si128((void *)&pkts[pos + 3]->pkt_len, pkt_mb3);
574 _mm_storeu_si128((void *)&pkts[pos + 2]->pkt_len, pkt_mb2);
575 /* E.1 extract op_own field. */
576 op_own_tmp2 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
577 /* C.1 load remained CQE data and extract necessary fields. */
578 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p1]);
579 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos]);
580 cqes[1] = _mm_blendv_epi8(cqes[1], cqe_tmp2, blend_mask);
581 cqes[0] = _mm_blendv_epi8(cqes[0], cqe_tmp1, blend_mask);
582 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p1].csum);
583 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos].csum);
584 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x30);
585 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x30);
586 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p1].rsvd4[2]);
587 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos].rsvd4[2]);
588 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x04);
589 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x04);
590 /* C.2 generate final structure for mbuf with swapping bytes. */
591 pkt_mb1 = _mm_shuffle_epi8(cqes[1], shuf_mask);
592 pkt_mb0 = _mm_shuffle_epi8(cqes[0], shuf_mask);
593 /* C.3 adjust CRC length. */
594 pkt_mb1 = _mm_sub_epi16(pkt_mb1, crc_adj);
595 pkt_mb0 = _mm_sub_epi16(pkt_mb0, crc_adj);
596 /* C.4 adjust flow mark. */
597 pkt_mb1 = _mm_add_epi32(pkt_mb1, flow_mark_adj);
598 pkt_mb0 = _mm_add_epi32(pkt_mb0, flow_mark_adj);
599 /* E.1 extract op_own byte. */
600 op_own_tmp1 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
601 op_own = _mm_unpackhi_epi64(op_own_tmp1, op_own_tmp2);
602 /* D.1 fill in mbuf - rx_descriptor_fields1. */
603 _mm_storeu_si128((void *)&pkts[pos + 1]->pkt_len, pkt_mb1);
604 _mm_storeu_si128((void *)&pkts[pos]->pkt_len, pkt_mb0);
605 /* E.2 flip owner bit to mark CQEs from last round. */
606 owner_mask = _mm_and_si128(op_own, owner_check);
608 owner_mask = _mm_xor_si128(owner_mask, owner_check);
609 owner_mask = _mm_cmpeq_epi32(owner_mask, owner_check);
610 owner_mask = _mm_packs_epi32(owner_mask, zero);
611 /* E.3 get mask for invalidated CQEs. */
612 opcode = _mm_and_si128(op_own, opcode_check);
613 invalid_mask = _mm_cmpeq_epi32(opcode_check, opcode);
614 invalid_mask = _mm_packs_epi32(invalid_mask, zero);
615 /* E.4 mask out beyond boundary. */
616 invalid_mask = _mm_or_si128(invalid_mask, mask);
617 /* E.5 merge invalid_mask with invalid owner. */
618 invalid_mask = _mm_or_si128(invalid_mask, owner_mask);
619 /* F.1 find compressed CQE format. */
620 comp_mask = _mm_and_si128(op_own, format_check);
621 comp_mask = _mm_cmpeq_epi32(comp_mask, format_check);
622 comp_mask = _mm_packs_epi32(comp_mask, zero);
623 /* F.2 mask out invalid entries. */
624 comp_mask = _mm_andnot_si128(invalid_mask, comp_mask);
625 comp_idx = _mm_cvtsi128_si64(comp_mask);
626 /* F.3 get the first compressed CQE. */
627 comp_idx = comp_idx ?
628 __builtin_ctzll(comp_idx) /
629 (sizeof(uint16_t) * 8) :
630 MLX5_VPMD_DESCS_PER_LOOP;
631 /* E.6 mask out entries after the compressed CQE. */
632 mask = _mm_set_epi64x(0, comp_idx * sizeof(uint16_t) * 8);
633 mask = _mm_sll_epi64(ones, mask);
634 invalid_mask = _mm_or_si128(invalid_mask, mask);
635 /* E.7 count non-compressed valid CQEs. */
636 n = _mm_cvtsi128_si64(invalid_mask);
637 n = n ? __builtin_ctzll(n) / (sizeof(uint16_t) * 8) :
638 MLX5_VPMD_DESCS_PER_LOOP;
640 /* D.2 get the final invalid mask. */
641 mask = _mm_set_epi64x(0, n * sizeof(uint16_t) * 8);
642 mask = _mm_sll_epi64(ones, mask);
643 invalid_mask = _mm_or_si128(invalid_mask, mask);
644 /* D.3 check error in opcode. */
645 opcode = _mm_cmpeq_epi32(resp_err_check, opcode);
646 opcode = _mm_packs_epi32(opcode, zero);
647 opcode = _mm_andnot_si128(invalid_mask, opcode);
648 /* D.4 mark if any error is set */
649 *err |= _mm_cvtsi128_si64(opcode);
650 /* D.5 fill in mbuf - rearm_data and packet_type. */
651 rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
652 if (rxq->hw_timestamp) {
653 pkts[pos]->timestamp =
654 rte_be_to_cpu_64(cq[pos].timestamp);
655 pkts[pos + 1]->timestamp =
656 rte_be_to_cpu_64(cq[pos + p1].timestamp);
657 pkts[pos + 2]->timestamp =
658 rte_be_to_cpu_64(cq[pos + p2].timestamp);
659 pkts[pos + 3]->timestamp =
660 rte_be_to_cpu_64(cq[pos + p3].timestamp);
662 if (rxq->dynf_meta) {
663 /* This code is subject for futher optimization. */
664 int32_t offs = rxq->flow_meta_offset;
666 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) =
667 cq[pos].flow_table_metadata;
668 *RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *) =
669 cq[pos + p1].flow_table_metadata;
670 *RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *) =
671 cq[pos + p2].flow_table_metadata;
672 *RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *) =
673 cq[pos + p3].flow_table_metadata;
674 if (*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *))
675 pkts[pos]->ol_flags |= rxq->flow_meta_mask;
676 if (*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *))
677 pkts[pos + 1]->ol_flags |= rxq->flow_meta_mask;
678 if (*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *))
679 pkts[pos + 2]->ol_flags |= rxq->flow_meta_mask;
680 if (*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *))
681 pkts[pos + 3]->ol_flags |= rxq->flow_meta_mask;
683 #ifdef MLX5_PMD_SOFT_COUNTERS
684 /* Add up received bytes count. */
685 byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);
686 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
687 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
688 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
691 * Break the loop unless more valid CQE is expected, or if
692 * there's a compressed CQE.
694 if (n != MLX5_VPMD_DESCS_PER_LOOP)
697 /* If no new CQE seen, return without updating cq_db. */
698 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
700 /* Update the consumer indexes for non-compressed CQEs. */
701 MLX5_ASSERT(nocmp_n <= pkts_n);
702 rxq->cq_ci += nocmp_n;
703 rxq->rq_pi += nocmp_n;
705 #ifdef MLX5_PMD_SOFT_COUNTERS
706 rxq->stats.ipackets += nocmp_n;
707 rxq->stats.ibytes += rcvd_byte;
709 /* Decompress the last CQE if compressed. */
710 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
711 MLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
712 rxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n],
714 /* Return more packets if needed. */
715 if (nocmp_n < pkts_n) {
716 uint16_t n = rxq->decompressed;
718 n = RTE_MIN(n, pkts_n - nocmp_n);
719 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
722 rxq->decompressed -= n;
725 rte_compiler_barrier();
726 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
730 #endif /* RTE_PMD_MLX5_RXTX_VEC_SSE_H_ */