drivers/net/mlx5/mlx5_trigger.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_ether.h>
   9 #include <rte_ethdev_driver.h>
  10 #include <rte_interrupts.h>
  11 #include <rte_alarm.h>
  12
  13 #include "mlx5.h"
  14 #include "mlx5_mr.h"
  15 #include "mlx5_rxtx.h"
  16 #include "mlx5_utils.h"
  17 #include "rte_pmd_mlx5.h"
  18
  19 /**
  20  * Stop traffic on Tx queues.
  21  *
  22  * @param dev
  23  *   Pointer to Ethernet device structure.
  24  */
  25 static void
  26 mlx5_txq_stop(struct rte_eth_dev *dev)
  27 {
  28         struct mlx5_priv *priv = dev->data->dev_private;
  29         unsigned int i;
  30
  31         for (i = 0; i != priv->txqs_n; ++i)
  32                 mlx5_txq_release(dev, i);
  33 }
  34
  35 /**
  36  * Start traffic on Tx queues.
  37  *
  38  * @param dev
  39  *   Pointer to Ethernet device structure.
  40  *
  41  * @return
  42  *   0 on success, a negative errno value otherwise and rte_errno is set.
  43  */
  44 static int
  45 mlx5_txq_start(struct rte_eth_dev *dev)
  46 {
  47         struct mlx5_priv *priv = dev->data->dev_private;
  48         unsigned int i;
  49         int ret;
  50
  51         for (i = 0; i != priv->txqs_n; ++i) {
  52                 struct mlx5_txq_ctrl *txq_ctrl = mlx5_txq_get(dev, i);
  53
  54                 if (!txq_ctrl)
  55                         continue;
  56                 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {
  57                         txq_ctrl->obj = mlx5_txq_obj_new
  58                                 (dev, i, MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN);
  59                 } else {
  60                         txq_alloc_elts(txq_ctrl);
  61                         txq_ctrl->obj = mlx5_txq_obj_new
  62                                 (dev, i, MLX5_TXQ_OBJ_TYPE_IBV);
  63                 }
  64                 if (!txq_ctrl->obj) {
  65                         rte_errno = ENOMEM;
  66                         goto error;
  67                 }
  68         }
  69         return 0;
  70 error:
  71         ret = rte_errno; /* Save rte_errno before cleanup. */
  72         do {
  73                 mlx5_txq_release(dev, i);
  74         } while (i-- != 0);
  75         rte_errno = ret; /* Restore rte_errno. */
  76         return -rte_errno;
  77 }
  78
  79 /**
  80  * Stop traffic on Rx queues.
  81  *
  82  * @param dev
  83  *   Pointer to Ethernet device structure.
  84  */
  85 static void
  86 mlx5_rxq_stop(struct rte_eth_dev *dev)
  87 {
  88         struct mlx5_priv *priv = dev->data->dev_private;
  89         unsigned int i;
  90
  91         for (i = 0; i != priv->rxqs_n; ++i)
  92                 mlx5_rxq_release(dev, i);
  93 }
  94
  95 /**
  96  * Start traffic on Rx queues.
  97  *
  98  * @param dev
  99  *   Pointer to Ethernet device structure.
 100  *
 101  * @return
 102  *   0 on success, a negative errno value otherwise and rte_errno is set.
 103  */
 104 static int
 105 mlx5_rxq_start(struct rte_eth_dev *dev)
 106 {
 107         struct mlx5_priv *priv = dev->data->dev_private;
 108         unsigned int i;
 109         int ret = 0;
 110         enum mlx5_rxq_obj_type obj_type = MLX5_RXQ_OBJ_TYPE_IBV;
 111         struct mlx5_rxq_data *rxq = NULL;
 112
 113         for (i = 0; i < priv->rxqs_n; ++i) {
 114                 rxq = (*priv->rxqs)[i];
 115                 if (rxq && rxq->lro) {
 116                         obj_type =  MLX5_RXQ_OBJ_TYPE_DEVX_RQ;
 117                         break;
 118                 }
 119         }
 120         /* Allocate/reuse/resize mempool for Multi-Packet RQ. */
 121         if (mlx5_mprq_alloc_mp(dev)) {
 122                 /* Should not release Rx queues but return immediately. */
 123                 return -rte_errno;
 124         }
 125         for (i = 0; i != priv->rxqs_n; ++i) {
 126                 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i);
 127                 struct rte_mempool *mp;
 128
 129                 if (!rxq_ctrl)
 130                         continue;
 131                 if (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) {
 132                         rxq_ctrl->obj = mlx5_rxq_obj_new
 133                                 (dev, i, MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN);
 134                         if (!rxq_ctrl->obj)
 135                                 goto error;
 136                         continue;
 137                 }
 138                 /* Pre-register Rx mempool. */
 139                 mp = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 140                      rxq_ctrl->rxq.mprq_mp : rxq_ctrl->rxq.mp;
 141                 DRV_LOG(DEBUG,
 142                         "port %u Rx queue %u registering"
 143                         " mp %s having %u chunks",
 144                         dev->data->port_id, rxq_ctrl->rxq.idx,
 145                         mp->name, mp->nb_mem_chunks);
 146                 mlx5_mr_update_mp(dev, &rxq_ctrl->rxq.mr_ctrl, mp);
 147                 ret = rxq_alloc_elts(rxq_ctrl);
 148                 if (ret)
 149                         goto error;
 150                 rxq_ctrl->obj = mlx5_rxq_obj_new(dev, i, obj_type);
 151                 if (!rxq_ctrl->obj)
 152                         goto error;
 153                 if (obj_type == MLX5_RXQ_OBJ_TYPE_IBV)
 154                         rxq_ctrl->wqn = rxq_ctrl->obj->wq->wq_num;
 155                 else if (obj_type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
 156                         rxq_ctrl->wqn = rxq_ctrl->obj->rq->id;
 157         }
 158         return 0;
 159 error:
 160         ret = rte_errno; /* Save rte_errno before cleanup. */
 161         do {
 162                 mlx5_rxq_release(dev, i);
 163         } while (i-- != 0);
 164         rte_errno = ret; /* Restore rte_errno. */
 165         return -rte_errno;
 166 }
 167
 168 /**
 169  * Binds Tx queues to Rx queues for hairpin.
 170  *
 171  * Binds Tx queues to the target Rx queues.
 172  *
 173  * @param dev
 174  *   Pointer to Ethernet device structure.
 175  *
 176  * @return
 177  *   0 on success, a negative errno value otherwise and rte_errno is set.
 178  */
 179 static int
 180 mlx5_hairpin_bind(struct rte_eth_dev *dev)
 181 {
 182         struct mlx5_priv *priv = dev->data->dev_private;
 183         struct mlx5_devx_modify_sq_attr sq_attr = { 0 };
 184         struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
 185         struct mlx5_txq_ctrl *txq_ctrl;
 186         struct mlx5_rxq_ctrl *rxq_ctrl;
 187         struct mlx5_devx_obj *sq;
 188         struct mlx5_devx_obj *rq;
 189         unsigned int i;
 190         int ret = 0;
 191
 192         for (i = 0; i != priv->txqs_n; ++i) {
 193                 txq_ctrl = mlx5_txq_get(dev, i);
 194                 if (!txq_ctrl)
 195                         continue;
 196                 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
 197                         mlx5_txq_release(dev, i);
 198                         continue;
 199                 }
 200                 if (!txq_ctrl->obj) {
 201                         rte_errno = ENOMEM;
 202                         DRV_LOG(ERR, "port %u no txq object found: %d",
 203                                 dev->data->port_id, i);
 204                         mlx5_txq_release(dev, i);
 205                         return -rte_errno;
 206                 }
 207                 sq = txq_ctrl->obj->sq;
 208                 rxq_ctrl = mlx5_rxq_get(dev,
 209                                         txq_ctrl->hairpin_conf.peers[0].queue);
 210                 if (!rxq_ctrl) {
 211                         mlx5_txq_release(dev, i);
 212                         rte_errno = EINVAL;
 213                         DRV_LOG(ERR, "port %u no rxq object found: %d",
 214                                 dev->data->port_id,
 215                                 txq_ctrl->hairpin_conf.peers[0].queue);
 216                         return -rte_errno;
 217                 }
 218                 if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN ||
 219                     rxq_ctrl->hairpin_conf.peers[0].queue != i) {
 220                         rte_errno = ENOMEM;
 221                         DRV_LOG(ERR, "port %u Tx queue %d can't be binded to "
 222                                 "Rx queue %d", dev->data->port_id,
 223                                 i, txq_ctrl->hairpin_conf.peers[0].queue);
 224                         goto error;
 225                 }
 226                 rq = rxq_ctrl->obj->rq;
 227                 if (!rq) {
 228                         rte_errno = ENOMEM;
 229                         DRV_LOG(ERR, "port %u hairpin no matching rxq: %d",
 230                                 dev->data->port_id,
 231                                 txq_ctrl->hairpin_conf.peers[0].queue);
 232                         goto error;
 233                 }
 234                 sq_attr.state = MLX5_SQC_STATE_RDY;
 235                 sq_attr.sq_state = MLX5_SQC_STATE_RST;
 236                 sq_attr.hairpin_peer_rq = rq->id;
 237                 sq_attr.hairpin_peer_vhca = priv->config.hca_attr.vhca_id;
 238                 ret = mlx5_devx_cmd_modify_sq(sq, &sq_attr);
 239                 if (ret)
 240                         goto error;
 241                 rq_attr.state = MLX5_SQC_STATE_RDY;
 242                 rq_attr.rq_state = MLX5_SQC_STATE_RST;
 243                 rq_attr.hairpin_peer_sq = sq->id;
 244                 rq_attr.hairpin_peer_vhca = priv->config.hca_attr.vhca_id;
 245                 ret = mlx5_devx_cmd_modify_rq(rq, &rq_attr);
 246                 if (ret)
 247                         goto error;
 248                 mlx5_txq_release(dev, i);
 249                 mlx5_rxq_release(dev, txq_ctrl->hairpin_conf.peers[0].queue);
 250         }
 251         return 0;
 252 error:
 253         mlx5_txq_release(dev, i);
 254         mlx5_rxq_release(dev, txq_ctrl->hairpin_conf.peers[0].queue);
 255         return -rte_errno;
 256 }
 257
 258 /**
 259  * DPDK callback to start the device.
 260  *
 261  * Simulate device start by attaching all configured flows.
 262  *
 263  * @param dev
 264  *   Pointer to Ethernet device structure.
 265  *
 266  * @return
 267  *   0 on success, a negative errno value otherwise and rte_errno is set.
 268  */
 269 int
 270 mlx5_dev_start(struct rte_eth_dev *dev)
 271 {
 272         struct mlx5_priv *priv = dev->data->dev_private;
 273         int ret;
 274         int fine_inline;
 275
 276         DRV_LOG(DEBUG, "port %u starting device", dev->data->port_id);
 277         fine_inline = rte_mbuf_dynflag_lookup
 278                 (RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, NULL);
 279         if (fine_inline > 0)
 280                 rte_net_mlx5_dynf_inline_mask = 1UL << fine_inline;
 281         else
 282                 rte_net_mlx5_dynf_inline_mask = 0;
 283         if (dev->data->nb_rx_queues > 0) {
 284                 ret = mlx5_dev_configure_rss_reta(dev);
 285                 if (ret) {
 286                         DRV_LOG(ERR, "port %u reta config failed: %s",
 287                                 dev->data->port_id, strerror(rte_errno));
 288                         return -rte_errno;
 289                 }
 290         }
 291         ret = mlx5_txq_start(dev);
 292         if (ret) {
 293                 DRV_LOG(ERR, "port %u Tx queue allocation failed: %s",
 294                         dev->data->port_id, strerror(rte_errno));
 295                 return -rte_errno;
 296         }
 297         ret = mlx5_rxq_start(dev);
 298         if (ret) {
 299                 DRV_LOG(ERR, "port %u Rx queue allocation failed: %s",
 300                         dev->data->port_id, strerror(rte_errno));
 301                 mlx5_txq_stop(dev);
 302                 return -rte_errno;
 303         }
 304         ret = mlx5_hairpin_bind(dev);
 305         if (ret) {
 306                 DRV_LOG(ERR, "port %u hairpin binding failed: %s",
 307                         dev->data->port_id, strerror(rte_errno));
 308                 mlx5_txq_stop(dev);
 309                 return -rte_errno;
 310         }
 311         /* Set started flag here for the following steps like control flow. */
 312         dev->data->dev_started = 1;
 313         ret = mlx5_rx_intr_vec_enable(dev);
 314         if (ret) {
 315                 DRV_LOG(ERR, "port %u Rx interrupt vector creation failed",
 316                         dev->data->port_id);
 317                 goto error;
 318         }
 319         mlx5_os_stats_init(dev);
 320         ret = mlx5_traffic_enable(dev);
 321         if (ret) {
 322                 DRV_LOG(ERR, "port %u failed to set defaults flows",
 323                         dev->data->port_id);
 324                 goto error;
 325         }
 326         /* Set a mask and offset of dynamic metadata flows into Rx queues*/
 327         mlx5_flow_rxq_dynf_metadata_set(dev);
 328         /*
 329          * In non-cached mode, it only needs to start the default mreg copy
 330          * action and no flow created by application exists anymore.
 331          * But it is worth wrapping the interface for further usage.
 332          */
 333         ret = mlx5_flow_start_default(dev);
 334         if (ret) {
 335                 DRV_LOG(DEBUG, "port %u failed to start default actions: %s",
 336                         dev->data->port_id, strerror(rte_errno));
 337                 goto error;
 338         }
 339         rte_wmb();
 340         dev->tx_pkt_burst = mlx5_select_tx_function(dev);
 341         dev->rx_pkt_burst = mlx5_select_rx_function(dev);
 342         /* Enable datapath on secondary process. */
 343         mlx5_mp_req_start_rxtx(dev);
 344         if (priv->sh->intr_handle.fd >= 0) {
 345                 priv->sh->port[priv->dev_port - 1].ih_port_id =
 346                                         (uint32_t)dev->data->port_id;
 347         } else {
 348                 DRV_LOG(INFO, "port %u starts without LSC and RMV interrupts.",
 349                         dev->data->port_id);
 350                 dev->data->dev_conf.intr_conf.lsc = 0;
 351                 dev->data->dev_conf.intr_conf.rmv = 0;
 352         }
 353         if (priv->sh->intr_handle_devx.fd >= 0)
 354                 priv->sh->port[priv->dev_port - 1].devx_ih_port_id =
 355                                         (uint32_t)dev->data->port_id;
 356         return 0;
 357 error:
 358         ret = rte_errno; /* Save rte_errno before cleanup. */
 359         /* Rollback. */
 360         dev->data->dev_started = 0;
 361         mlx5_flow_stop_default(dev);
 362         mlx5_traffic_disable(dev);
 363         mlx5_txq_stop(dev);
 364         mlx5_rxq_stop(dev);
 365         rte_errno = ret; /* Restore rte_errno. */
 366         return -rte_errno;
 367 }
 368
 369 /**
 370  * DPDK callback to stop the device.
 371  *
 372  * Simulate device stop by detaching all configured flows.
 373  *
 374  * @param dev
 375  *   Pointer to Ethernet device structure.
 376  */
 377 void
 378 mlx5_dev_stop(struct rte_eth_dev *dev)
 379 {
 380         struct mlx5_priv *priv = dev->data->dev_private;
 381
 382         dev->data->dev_started = 0;
 383         /* Prevent crashes when queues are still in use. */
 384         dev->rx_pkt_burst = removed_rx_burst;
 385         dev->tx_pkt_burst = removed_tx_burst;
 386         rte_wmb();
 387         /* Disable datapath on secondary process. */
 388         mlx5_mp_req_stop_rxtx(dev);
 389         usleep(1000 * priv->rxqs_n);
 390         DRV_LOG(DEBUG, "port %u stopping device", dev->data->port_id);
 391         mlx5_flow_stop_default(dev);
 392         /* Control flows for default traffic can be removed firstly. */
 393         mlx5_traffic_disable(dev);
 394         /* All RX queue flags will be cleared in the flush interface. */
 395         mlx5_flow_list_flush(dev, &priv->flows, true);
 396         mlx5_rx_intr_vec_disable(dev);
 397         priv->sh->port[priv->dev_port - 1].ih_port_id = RTE_MAX_ETHPORTS;
 398         priv->sh->port[priv->dev_port - 1].devx_ih_port_id = RTE_MAX_ETHPORTS;
 399         mlx5_txq_stop(dev);
 400         mlx5_rxq_stop(dev);
 401 }
 402
 403 /**
 404  * Enable traffic flows configured by control plane
 405  *
 406  * @param dev
 407  *   Pointer to Ethernet device private data.
 408  * @param dev
 409  *   Pointer to Ethernet device structure.
 410  *
 411  * @return
 412  *   0 on success, a negative errno value otherwise and rte_errno is set.
 413  */
 414 int
 415 mlx5_traffic_enable(struct rte_eth_dev *dev)
 416 {
 417         struct mlx5_priv *priv = dev->data->dev_private;
 418         struct rte_flow_item_eth bcast = {
 419                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
 420         };
 421         struct rte_flow_item_eth ipv6_multi_spec = {
 422                 .dst.addr_bytes = "\x33\x33\x00\x00\x00\x00",
 423         };
 424         struct rte_flow_item_eth ipv6_multi_mask = {
 425                 .dst.addr_bytes = "\xff\xff\x00\x00\x00\x00",
 426         };
 427         struct rte_flow_item_eth unicast = {
 428                 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00",
 429         };
 430         struct rte_flow_item_eth unicast_mask = {
 431                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
 432         };
 433         const unsigned int vlan_filter_n = priv->vlan_filter_n;
 434         const struct rte_ether_addr cmp = {
 435                 .addr_bytes = "\x00\x00\x00\x00\x00\x00",
 436         };
 437         unsigned int i;
 438         unsigned int j;
 439         int ret;
 440
 441         /*
 442          * Hairpin txq default flow should be created no matter if it is
 443          * isolation mode. Or else all the packets to be sent will be sent
 444          * out directly without the TX flow actions, e.g. encapsulation.
 445          */
 446         for (i = 0; i != priv->txqs_n; ++i) {
 447                 struct mlx5_txq_ctrl *txq_ctrl = mlx5_txq_get(dev, i);
 448                 if (!txq_ctrl)
 449                         continue;
 450                 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {
 451                         ret = mlx5_ctrl_flow_source_queue(dev, i);
 452                         if (ret) {
 453                                 mlx5_txq_release(dev, i);
 454                                 goto error;
 455                         }
 456                 }
 457                 mlx5_txq_release(dev, i);
 458         }
 459         if (priv->config.dv_esw_en && !priv->config.vf) {
 460                 if (mlx5_flow_create_esw_table_zero_flow(dev))
 461                         priv->fdb_def_rule = 1;
 462                 else
 463                         DRV_LOG(INFO, "port %u FDB default rule cannot be"
 464                                 " configured - only Eswitch group 0 flows are"
 465                                 " supported.", dev->data->port_id);
 466         }
 467         if (priv->isolated)
 468                 return 0;
 469         if (dev->data->promiscuous) {
 470                 struct rte_flow_item_eth promisc = {
 471                         .dst.addr_bytes = "\x00\x00\x00\x00\x00\x00",
 472                         .src.addr_bytes = "\x00\x00\x00\x00\x00\x00",
 473                         .type = 0,
 474                 };
 475
 476                 ret = mlx5_ctrl_flow(dev, &promisc, &promisc);
 477                 if (ret)
 478                         goto error;
 479         }
 480         if (dev->data->all_multicast) {
 481                 struct rte_flow_item_eth multicast = {
 482                         .dst.addr_bytes = "\x01\x00\x00\x00\x00\x00",
 483                         .src.addr_bytes = "\x00\x00\x00\x00\x00\x00",
 484                         .type = 0,
 485                 };
 486
 487                 ret = mlx5_ctrl_flow(dev, &multicast, &multicast);
 488                 if (ret)
 489                         goto error;
 490         } else {
 491                 /* Add broadcast/multicast flows. */
 492                 for (i = 0; i != vlan_filter_n; ++i) {
 493                         uint16_t vlan = priv->vlan_filter[i];
 494
 495                         struct rte_flow_item_vlan vlan_spec = {
 496                                 .tci = rte_cpu_to_be_16(vlan),
 497                         };
 498                         struct rte_flow_item_vlan vlan_mask =
 499                                 rte_flow_item_vlan_mask;
 500
 501                         ret = mlx5_ctrl_flow_vlan(dev, &bcast, &bcast,
 502                                                   &vlan_spec, &vlan_mask);
 503                         if (ret)
 504                                 goto error;
 505                         ret = mlx5_ctrl_flow_vlan(dev, &ipv6_multi_spec,
 506                                                   &ipv6_multi_mask,
 507                                                   &vlan_spec, &vlan_mask);
 508                         if (ret)
 509                                 goto error;
 510                 }
 511                 if (!vlan_filter_n) {
 512                         ret = mlx5_ctrl_flow(dev, &bcast, &bcast);
 513                         if (ret)
 514                                 goto error;
 515                         ret = mlx5_ctrl_flow(dev, &ipv6_multi_spec,
 516                                              &ipv6_multi_mask);
 517                         if (ret)
 518                                 goto error;
 519                 }
 520         }
 521         /* Add MAC address flows. */
 522         for (i = 0; i != MLX5_MAX_MAC_ADDRESSES; ++i) {
 523                 struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
 524
 525                 if (!memcmp(mac, &cmp, sizeof(*mac)))
 526                         continue;
 527                 memcpy(&unicast.dst.addr_bytes,
 528                        mac->addr_bytes,
 529                        RTE_ETHER_ADDR_LEN);
 530                 for (j = 0; j != vlan_filter_n; ++j) {
 531                         uint16_t vlan = priv->vlan_filter[j];
 532
 533                         struct rte_flow_item_vlan vlan_spec = {
 534                                 .tci = rte_cpu_to_be_16(vlan),
 535                         };
 536                         struct rte_flow_item_vlan vlan_mask =
 537                                 rte_flow_item_vlan_mask;
 538
 539                         ret = mlx5_ctrl_flow_vlan(dev, &unicast,
 540                                                   &unicast_mask,
 541                                                   &vlan_spec,
 542                                                   &vlan_mask);
 543                         if (ret)
 544                                 goto error;
 545                 }
 546                 if (!vlan_filter_n) {
 547                         ret = mlx5_ctrl_flow(dev, &unicast, &unicast_mask);
 548                         if (ret)
 549                                 goto error;
 550                 }
 551         }
 552         return 0;
 553 error:
 554         ret = rte_errno; /* Save rte_errno before cleanup. */
 555         mlx5_flow_list_flush(dev, &priv->ctrl_flows, false);
 556         rte_errno = ret; /* Restore rte_errno. */
 557         return -rte_errno;
 558 }
 559
 560
 561 /**
 562  * Disable traffic flows configured by control plane
 563  *
 564  * @param dev
 565  *   Pointer to Ethernet device private data.
 566  */
 567 void
 568 mlx5_traffic_disable(struct rte_eth_dev *dev)
 569 {
 570         struct mlx5_priv *priv = dev->data->dev_private;
 571
 572         mlx5_flow_list_flush(dev, &priv->ctrl_flows, false);
 573 }
 574
 575 /**
 576  * Restart traffic flows configured by control plane
 577  *
 578  * @param dev
 579  *   Pointer to Ethernet device private data.
 580  *
 581  * @return
 582  *   0 on success, a negative errno value otherwise and rte_errno is set.
 583  */
 584 int
 585 mlx5_traffic_restart(struct rte_eth_dev *dev)
 586 {
 587         if (dev->data->dev_started) {
 588                 mlx5_traffic_disable(dev);
 589                 return mlx5_traffic_enable(dev);
 590         }
 591         return 0;
 592 }