1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
9 #include <rte_ethdev_driver.h>
10 #include <rte_interrupts.h>
11 #include <rte_alarm.h>
13 #include <mlx5_malloc.h>
17 #include "mlx5_rxtx.h"
18 #include "mlx5_utils.h"
19 #include "rte_pmd_mlx5.h"
22 * Stop traffic on Tx queues.
25 * Pointer to Ethernet device structure.
28 mlx5_txq_stop(struct rte_eth_dev *dev)
30 struct mlx5_priv *priv = dev->data->dev_private;
33 for (i = 0; i != priv->txqs_n; ++i)
34 mlx5_txq_release(dev, i);
38 * Start traffic on Tx queues.
41 * Pointer to Ethernet device structure.
44 * 0 on success, a negative errno value otherwise and rte_errno is set.
47 mlx5_txq_start(struct rte_eth_dev *dev)
49 struct mlx5_priv *priv = dev->data->dev_private;
53 for (i = 0; i != priv->txqs_n; ++i) {
54 struct mlx5_txq_ctrl *txq_ctrl = mlx5_txq_get(dev, i);
55 struct mlx5_txq_data *txq_data = &txq_ctrl->txq;
56 uint32_t flags = MLX5_MEM_RTE | MLX5_MEM_ZERO;
60 if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD)
61 txq_alloc_elts(txq_ctrl);
62 MLX5_ASSERT(!txq_ctrl->obj);
63 txq_ctrl->obj = mlx5_malloc(flags, sizeof(struct mlx5_txq_obj),
66 DRV_LOG(ERR, "Port %u Tx queue %u cannot allocate "
67 "memory resources.", dev->data->port_id,
72 ret = priv->obj_ops.txq_obj_new(dev, i);
74 mlx5_free(txq_ctrl->obj);
78 if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD) {
79 size_t size = txq_data->cqe_s * sizeof(*txq_data->fcqs);
80 txq_data->fcqs = mlx5_malloc(flags, size,
83 if (!txq_data->fcqs) {
84 DRV_LOG(ERR, "Port %u Tx queue %u cannot "
85 "allocate memory (FCQ).",
86 dev->data->port_id, i);
91 DRV_LOG(DEBUG, "Port %u txq %u updated with %p.",
92 dev->data->port_id, i, (void *)&txq_ctrl->obj);
93 LIST_INSERT_HEAD(&priv->txqsobj, txq_ctrl->obj, next);
97 ret = rte_errno; /* Save rte_errno before cleanup. */
99 mlx5_txq_release(dev, i);
101 rte_errno = ret; /* Restore rte_errno. */
106 * Stop traffic on Rx queues.
109 * Pointer to Ethernet device structure.
112 mlx5_rxq_stop(struct rte_eth_dev *dev)
114 struct mlx5_priv *priv = dev->data->dev_private;
117 for (i = 0; i != priv->rxqs_n; ++i)
118 mlx5_rxq_release(dev, i);
122 * Start traffic on Rx queues.
125 * Pointer to Ethernet device structure.
128 * 0 on success, a negative errno value otherwise and rte_errno is set.
131 mlx5_rxq_start(struct rte_eth_dev *dev)
133 struct mlx5_priv *priv = dev->data->dev_private;
137 /* Allocate/reuse/resize mempool for Multi-Packet RQ. */
138 if (mlx5_mprq_alloc_mp(dev)) {
139 /* Should not release Rx queues but return immediately. */
142 DRV_LOG(DEBUG, "Port %u device_attr.max_qp_wr is %d.",
143 dev->data->port_id, priv->sh->device_attr.max_qp_wr);
144 DRV_LOG(DEBUG, "Port %u device_attr.max_sge is %d.",
145 dev->data->port_id, priv->sh->device_attr.max_sge);
146 for (i = 0; i != priv->rxqs_n; ++i) {
147 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i);
151 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) {
152 /* Pre-register Rx mempools. */
153 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq)) {
154 mlx5_mr_update_mp(dev, &rxq_ctrl->rxq.mr_ctrl,
155 rxq_ctrl->rxq.mprq_mp);
159 for (s = 0; s < rxq_ctrl->rxq.rxseg_n; s++)
161 (dev, &rxq_ctrl->rxq.mr_ctrl,
162 rxq_ctrl->rxq.rxseg[s].mp);
164 ret = rxq_alloc_elts(rxq_ctrl);
168 MLX5_ASSERT(!rxq_ctrl->obj);
169 rxq_ctrl->obj = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
170 sizeof(*rxq_ctrl->obj), 0,
172 if (!rxq_ctrl->obj) {
174 "Port %u Rx queue %u can't allocate resources.",
175 dev->data->port_id, (*priv->rxqs)[i]->idx);
179 ret = priv->obj_ops.rxq_obj_new(dev, i);
181 mlx5_free(rxq_ctrl->obj);
184 DRV_LOG(DEBUG, "Port %u rxq %u updated with %p.",
185 dev->data->port_id, i, (void *)&rxq_ctrl->obj);
186 LIST_INSERT_HEAD(&priv->rxqsobj, rxq_ctrl->obj, next);
190 ret = rte_errno; /* Save rte_errno before cleanup. */
192 mlx5_rxq_release(dev, i);
194 rte_errno = ret; /* Restore rte_errno. */
199 * Binds Tx queues to Rx queues for hairpin.
201 * Binds Tx queues to the target Rx queues.
204 * Pointer to Ethernet device structure.
207 * 0 on success, a negative errno value otherwise and rte_errno is set.
210 mlx5_hairpin_auto_bind(struct rte_eth_dev *dev)
212 struct mlx5_priv *priv = dev->data->dev_private;
213 struct mlx5_devx_modify_sq_attr sq_attr = { 0 };
214 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
215 struct mlx5_txq_ctrl *txq_ctrl;
216 struct mlx5_rxq_ctrl *rxq_ctrl;
217 struct mlx5_devx_obj *sq;
218 struct mlx5_devx_obj *rq;
222 for (i = 0; i != priv->txqs_n; ++i) {
223 txq_ctrl = mlx5_txq_get(dev, i);
226 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
227 mlx5_txq_release(dev, i);
230 if (!txq_ctrl->obj) {
232 DRV_LOG(ERR, "port %u no txq object found: %d",
233 dev->data->port_id, i);
234 mlx5_txq_release(dev, i);
237 sq = txq_ctrl->obj->sq;
238 rxq_ctrl = mlx5_rxq_get(dev,
239 txq_ctrl->hairpin_conf.peers[0].queue);
241 mlx5_txq_release(dev, i);
243 DRV_LOG(ERR, "port %u no rxq object found: %d",
245 txq_ctrl->hairpin_conf.peers[0].queue);
248 if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN ||
249 rxq_ctrl->hairpin_conf.peers[0].queue != i) {
251 DRV_LOG(ERR, "port %u Tx queue %d can't be binded to "
252 "Rx queue %d", dev->data->port_id,
253 i, txq_ctrl->hairpin_conf.peers[0].queue);
256 rq = rxq_ctrl->obj->rq;
259 DRV_LOG(ERR, "port %u hairpin no matching rxq: %d",
261 txq_ctrl->hairpin_conf.peers[0].queue);
264 sq_attr.state = MLX5_SQC_STATE_RDY;
265 sq_attr.sq_state = MLX5_SQC_STATE_RST;
266 sq_attr.hairpin_peer_rq = rq->id;
267 sq_attr.hairpin_peer_vhca = priv->config.hca_attr.vhca_id;
268 ret = mlx5_devx_cmd_modify_sq(sq, &sq_attr);
271 rq_attr.state = MLX5_SQC_STATE_RDY;
272 rq_attr.rq_state = MLX5_SQC_STATE_RST;
273 rq_attr.hairpin_peer_sq = sq->id;
274 rq_attr.hairpin_peer_vhca = priv->config.hca_attr.vhca_id;
275 ret = mlx5_devx_cmd_modify_rq(rq, &rq_attr);
278 mlx5_txq_release(dev, i);
279 mlx5_rxq_release(dev, txq_ctrl->hairpin_conf.peers[0].queue);
283 mlx5_txq_release(dev, i);
284 mlx5_rxq_release(dev, txq_ctrl->hairpin_conf.peers[0].queue);
289 * Fetch the peer queue's SW & HW information.
292 * Pointer to Ethernet device structure.
294 * Index of the queue to fetch the information.
295 * @param current_info
296 * Pointer to the input peer information, not used currently.
298 * Pointer to the structure to store the information, output.
300 * Positive to get the RxQ information, zero to get the TxQ information.
303 * 0 on success, a negative errno value otherwise and rte_errno is set.
306 mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,
307 struct rte_hairpin_peer_info *current_info,
308 struct rte_hairpin_peer_info *peer_info,
311 struct mlx5_priv *priv = dev->data->dev_private;
312 RTE_SET_USED(current_info);
314 if (dev->data->dev_started == 0) {
316 DRV_LOG(ERR, "peer port %u is not started",
321 * Peer port used as egress. In the current design, hairpin Tx queue
322 * will be bound to the peer Rx queue. Indeed, only the information of
323 * peer Rx queue needs to be fetched.
325 if (direction == 0) {
326 struct mlx5_txq_ctrl *txq_ctrl;
328 txq_ctrl = mlx5_txq_get(dev, peer_queue);
329 if (txq_ctrl == NULL) {
331 DRV_LOG(ERR, "Failed to get port %u Tx queue %d",
332 dev->data->port_id, peer_queue);
335 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
337 DRV_LOG(ERR, "port %u queue %d is not a hairpin Txq",
338 dev->data->port_id, peer_queue);
339 mlx5_txq_release(dev, peer_queue);
342 if (txq_ctrl->obj == NULL || txq_ctrl->obj->sq == NULL) {
344 DRV_LOG(ERR, "port %u no Txq object found: %d",
345 dev->data->port_id, peer_queue);
346 mlx5_txq_release(dev, peer_queue);
349 peer_info->qp_id = txq_ctrl->obj->sq->id;
350 peer_info->vhca_id = priv->config.hca_attr.vhca_id;
351 /* 1-to-1 mapping, only the first one is used. */
352 peer_info->peer_q = txq_ctrl->hairpin_conf.peers[0].queue;
353 peer_info->tx_explicit = txq_ctrl->hairpin_conf.tx_explicit;
354 peer_info->manual_bind = txq_ctrl->hairpin_conf.manual_bind;
355 mlx5_txq_release(dev, peer_queue);
356 } else { /* Peer port used as ingress. */
357 struct mlx5_rxq_ctrl *rxq_ctrl;
359 rxq_ctrl = mlx5_rxq_get(dev, peer_queue);
360 if (rxq_ctrl == NULL) {
362 DRV_LOG(ERR, "Failed to get port %u Rx queue %d",
363 dev->data->port_id, peer_queue);
366 if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {
368 DRV_LOG(ERR, "port %u queue %d is not a hairpin Rxq",
369 dev->data->port_id, peer_queue);
370 mlx5_rxq_release(dev, peer_queue);
373 if (rxq_ctrl->obj == NULL || rxq_ctrl->obj->rq == NULL) {
375 DRV_LOG(ERR, "port %u no Rxq object found: %d",
376 dev->data->port_id, peer_queue);
377 mlx5_rxq_release(dev, peer_queue);
380 peer_info->qp_id = rxq_ctrl->obj->rq->id;
381 peer_info->vhca_id = priv->config.hca_attr.vhca_id;
382 peer_info->peer_q = rxq_ctrl->hairpin_conf.peers[0].queue;
383 peer_info->tx_explicit = rxq_ctrl->hairpin_conf.tx_explicit;
384 peer_info->manual_bind = rxq_ctrl->hairpin_conf.manual_bind;
385 mlx5_rxq_release(dev, peer_queue);
391 * Bind the hairpin queue with the peer HW information.
392 * This needs to be called twice both for Tx and Rx queues of a pair.
393 * If the queue is already bound, it is considered successful.
396 * Pointer to Ethernet device structure.
398 * Index of the queue to change the HW configuration to bind.
400 * Pointer to information of the peer queue.
402 * Positive to configure the TxQ, zero to configure the RxQ.
405 * 0 on success, a negative errno value otherwise and rte_errno is set.
408 mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,
409 struct rte_hairpin_peer_info *peer_info,
415 * Consistency checking of the peer queue: opposite direction is used
416 * to get the peer queue info with ethdev port ID, no need to check.
418 if (peer_info->peer_q != cur_queue) {
420 DRV_LOG(ERR, "port %u queue %d and peer queue %d mismatch",
421 dev->data->port_id, cur_queue, peer_info->peer_q);
424 if (direction != 0) {
425 struct mlx5_txq_ctrl *txq_ctrl;
426 struct mlx5_devx_modify_sq_attr sq_attr = { 0 };
428 txq_ctrl = mlx5_txq_get(dev, cur_queue);
429 if (txq_ctrl == NULL) {
431 DRV_LOG(ERR, "Failed to get port %u Tx queue %d",
432 dev->data->port_id, cur_queue);
435 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
437 DRV_LOG(ERR, "port %u queue %d not a hairpin Txq",
438 dev->data->port_id, cur_queue);
439 mlx5_txq_release(dev, cur_queue);
442 if (txq_ctrl->obj == NULL || txq_ctrl->obj->sq == NULL) {
444 DRV_LOG(ERR, "port %u no Txq object found: %d",
445 dev->data->port_id, cur_queue);
446 mlx5_txq_release(dev, cur_queue);
449 if (txq_ctrl->hairpin_status != 0) {
450 DRV_LOG(DEBUG, "port %u Tx queue %d is already bound",
451 dev->data->port_id, cur_queue);
452 mlx5_txq_release(dev, cur_queue);
456 * All queues' of one port consistency checking is done in the
457 * bind() function, and that is optional.
459 if (peer_info->tx_explicit !=
460 txq_ctrl->hairpin_conf.tx_explicit) {
462 DRV_LOG(ERR, "port %u Tx queue %d and peer Tx rule mode"
463 " mismatch", dev->data->port_id, cur_queue);
464 mlx5_txq_release(dev, cur_queue);
467 if (peer_info->manual_bind !=
468 txq_ctrl->hairpin_conf.manual_bind) {
470 DRV_LOG(ERR, "port %u Tx queue %d and peer binding mode"
471 " mismatch", dev->data->port_id, cur_queue);
472 mlx5_txq_release(dev, cur_queue);
475 sq_attr.state = MLX5_SQC_STATE_RDY;
476 sq_attr.sq_state = MLX5_SQC_STATE_RST;
477 sq_attr.hairpin_peer_rq = peer_info->qp_id;
478 sq_attr.hairpin_peer_vhca = peer_info->vhca_id;
479 ret = mlx5_devx_cmd_modify_sq(txq_ctrl->obj->sq, &sq_attr);
481 txq_ctrl->hairpin_status = 1;
482 mlx5_txq_release(dev, cur_queue);
484 struct mlx5_rxq_ctrl *rxq_ctrl;
485 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
487 rxq_ctrl = mlx5_rxq_get(dev, cur_queue);
488 if (rxq_ctrl == NULL) {
490 DRV_LOG(ERR, "Failed to get port %u Rx queue %d",
491 dev->data->port_id, cur_queue);
494 if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {
496 DRV_LOG(ERR, "port %u queue %d not a hairpin Rxq",
497 dev->data->port_id, cur_queue);
498 mlx5_rxq_release(dev, cur_queue);
501 if (rxq_ctrl->obj == NULL || rxq_ctrl->obj->rq == NULL) {
503 DRV_LOG(ERR, "port %u no Rxq object found: %d",
504 dev->data->port_id, cur_queue);
505 mlx5_rxq_release(dev, cur_queue);
508 if (rxq_ctrl->hairpin_status != 0) {
509 DRV_LOG(DEBUG, "port %u Rx queue %d is already bound",
510 dev->data->port_id, cur_queue);
511 mlx5_rxq_release(dev, cur_queue);
514 if (peer_info->tx_explicit !=
515 rxq_ctrl->hairpin_conf.tx_explicit) {
517 DRV_LOG(ERR, "port %u Rx queue %d and peer Tx rule mode"
518 " mismatch", dev->data->port_id, cur_queue);
519 mlx5_rxq_release(dev, cur_queue);
522 if (peer_info->manual_bind !=
523 rxq_ctrl->hairpin_conf.manual_bind) {
525 DRV_LOG(ERR, "port %u Rx queue %d and peer binding mode"
526 " mismatch", dev->data->port_id, cur_queue);
527 mlx5_rxq_release(dev, cur_queue);
530 rq_attr.state = MLX5_SQC_STATE_RDY;
531 rq_attr.rq_state = MLX5_SQC_STATE_RST;
532 rq_attr.hairpin_peer_sq = peer_info->qp_id;
533 rq_attr.hairpin_peer_vhca = peer_info->vhca_id;
534 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);
536 rxq_ctrl->hairpin_status = 1;
537 mlx5_rxq_release(dev, cur_queue);
543 * Unbind the hairpin queue and reset its HW configuration.
544 * This needs to be called twice both for Tx and Rx queues of a pair.
545 * If the queue is already unbound, it is considered successful.
548 * Pointer to Ethernet device structure.
550 * Index of the queue to change the HW configuration to unbind.
552 * Positive to reset the TxQ, zero to reset the RxQ.
555 * 0 on success, a negative errno value otherwise and rte_errno is set.
558 mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,
563 if (direction != 0) {
564 struct mlx5_txq_ctrl *txq_ctrl;
565 struct mlx5_devx_modify_sq_attr sq_attr = { 0 };
567 txq_ctrl = mlx5_txq_get(dev, cur_queue);
568 if (txq_ctrl == NULL) {
570 DRV_LOG(ERR, "Failed to get port %u Tx queue %d",
571 dev->data->port_id, cur_queue);
574 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
576 DRV_LOG(ERR, "port %u queue %d not a hairpin Txq",
577 dev->data->port_id, cur_queue);
578 mlx5_txq_release(dev, cur_queue);
581 /* Already unbound, return success before obj checking. */
582 if (txq_ctrl->hairpin_status == 0) {
583 DRV_LOG(DEBUG, "port %u Tx queue %d is already unbound",
584 dev->data->port_id, cur_queue);
585 mlx5_txq_release(dev, cur_queue);
588 if (!txq_ctrl->obj || !txq_ctrl->obj->sq) {
590 DRV_LOG(ERR, "port %u no Txq object found: %d",
591 dev->data->port_id, cur_queue);
592 mlx5_txq_release(dev, cur_queue);
595 sq_attr.state = MLX5_SQC_STATE_RST;
596 sq_attr.sq_state = MLX5_SQC_STATE_RST;
597 ret = mlx5_devx_cmd_modify_sq(txq_ctrl->obj->sq, &sq_attr);
599 txq_ctrl->hairpin_status = 0;
600 mlx5_txq_release(dev, cur_queue);
602 struct mlx5_rxq_ctrl *rxq_ctrl;
603 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
605 rxq_ctrl = mlx5_rxq_get(dev, cur_queue);
606 if (rxq_ctrl == NULL) {
608 DRV_LOG(ERR, "Failed to get port %u Rx queue %d",
609 dev->data->port_id, cur_queue);
612 if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {
614 DRV_LOG(ERR, "port %u queue %d not a hairpin Rxq",
615 dev->data->port_id, cur_queue);
616 mlx5_rxq_release(dev, cur_queue);
619 if (rxq_ctrl->hairpin_status == 0) {
620 DRV_LOG(DEBUG, "port %u Rx queue %d is already unbound",
621 dev->data->port_id, cur_queue);
622 mlx5_rxq_release(dev, cur_queue);
625 if (rxq_ctrl->obj == NULL || rxq_ctrl->obj->rq == NULL) {
627 DRV_LOG(ERR, "port %u no Rxq object found: %d",
628 dev->data->port_id, cur_queue);
629 mlx5_rxq_release(dev, cur_queue);
632 rq_attr.state = MLX5_SQC_STATE_RST;
633 rq_attr.rq_state = MLX5_SQC_STATE_RST;
634 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);
636 rxq_ctrl->hairpin_status = 0;
637 mlx5_rxq_release(dev, cur_queue);
643 * Bind the hairpin port pairs, from the Tx to the peer Rx.
644 * This function only supports to bind the Tx to one Rx.
647 * Pointer to Ethernet device structure.
649 * Port identifier of the Rx port.
652 * 0 on success, a negative errno value otherwise and rte_errno is set.
655 mlx5_hairpin_bind_single_port(struct rte_eth_dev *dev, uint16_t rx_port)
657 struct mlx5_priv *priv = dev->data->dev_private;
659 struct mlx5_txq_ctrl *txq_ctrl;
661 struct rte_hairpin_peer_info peer = {0xffffff};
662 struct rte_hairpin_peer_info cur;
663 const struct rte_eth_hairpin_conf *conf;
665 uint16_t local_port = priv->dev_data->port_id;
670 if (mlx5_eth_find_next(rx_port, priv->pci_dev) != rx_port) {
672 DRV_LOG(ERR, "Rx port %u does not belong to mlx5", rx_port);
676 * Before binding TxQ to peer RxQ, first round loop will be used for
677 * checking the queues' configuration consistency. This would be a
678 * little time consuming but better than doing the rollback.
680 for (i = 0; i != priv->txqs_n; i++) {
681 txq_ctrl = mlx5_txq_get(dev, i);
682 if (txq_ctrl == NULL)
684 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
685 mlx5_txq_release(dev, i);
689 * All hairpin Tx queues of a single port that connected to the
690 * same peer Rx port should have the same "auto binding" and
691 * "implicit Tx flow" modes.
692 * Peer consistency checking will be done in per queue binding.
694 conf = &txq_ctrl->hairpin_conf;
695 if (conf->peers[0].port == rx_port) {
697 manual = conf->manual_bind;
698 explicit = conf->tx_explicit;
700 if (manual != conf->manual_bind ||
701 explicit != conf->tx_explicit) {
703 DRV_LOG(ERR, "port %u queue %d mode"
704 " mismatch: %u %u, %u %u",
705 local_port, i, manual,
706 conf->manual_bind, explicit,
708 mlx5_txq_release(dev, i);
714 mlx5_txq_release(dev, i);
716 /* Once no queue is configured, success is returned directly. */
719 /* All the hairpin TX queues need to be traversed again. */
720 for (i = 0; i != priv->txqs_n; i++) {
721 txq_ctrl = mlx5_txq_get(dev, i);
722 if (txq_ctrl == NULL)
724 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
725 mlx5_txq_release(dev, i);
728 if (txq_ctrl->hairpin_conf.peers[0].port != rx_port) {
729 mlx5_txq_release(dev, i);
732 rx_queue = txq_ctrl->hairpin_conf.peers[0].queue;
734 * Fetch peer RxQ's information.
735 * No need to pass the information of the current queue.
737 ret = rte_eth_hairpin_queue_peer_update(rx_port, rx_queue,
740 mlx5_txq_release(dev, i);
743 /* Accessing its own device, inside mlx5 PMD. */
744 ret = mlx5_hairpin_queue_peer_bind(dev, i, &peer, 1);
746 mlx5_txq_release(dev, i);
749 /* Pass TxQ's information to peer RxQ and try binding. */
750 cur.peer_q = rx_queue;
751 cur.qp_id = txq_ctrl->obj->sq->id;
752 cur.vhca_id = priv->config.hca_attr.vhca_id;
753 cur.tx_explicit = txq_ctrl->hairpin_conf.tx_explicit;
754 cur.manual_bind = txq_ctrl->hairpin_conf.manual_bind;
756 * In order to access another device in a proper way, RTE level
757 * private function is needed.
759 ret = rte_eth_hairpin_queue_peer_bind(rx_port, rx_queue,
762 mlx5_txq_release(dev, i);
765 mlx5_txq_release(dev, i);
770 * Do roll-back process for the queues already bound.
771 * No need to check the return value of the queue unbind function.
774 /* No validation is needed here. */
775 txq_ctrl = mlx5_txq_get(dev, i);
776 if (txq_ctrl == NULL)
778 rx_queue = txq_ctrl->hairpin_conf.peers[0].queue;
779 rte_eth_hairpin_queue_peer_unbind(rx_port, rx_queue, 0);
780 mlx5_hairpin_queue_peer_unbind(dev, i, 1);
781 mlx5_txq_release(dev, i);
787 * Unbind the hairpin port pair, HW configuration of both devices will be clear
788 * and status will be reset for all the queues used between the them.
789 * This function only supports to unbind the Tx from one Rx.
792 * Pointer to Ethernet device structure.
794 * Port identifier of the Rx port.
797 * 0 on success, a negative errno value otherwise and rte_errno is set.
800 mlx5_hairpin_unbind_single_port(struct rte_eth_dev *dev, uint16_t rx_port)
802 struct mlx5_priv *priv = dev->data->dev_private;
803 struct mlx5_txq_ctrl *txq_ctrl;
806 uint16_t cur_port = priv->dev_data->port_id;
808 if (mlx5_eth_find_next(rx_port, priv->pci_dev) != rx_port) {
810 DRV_LOG(ERR, "Rx port %u does not belong to mlx5", rx_port);
813 for (i = 0; i != priv->txqs_n; i++) {
816 txq_ctrl = mlx5_txq_get(dev, i);
817 if (txq_ctrl == NULL)
819 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
820 mlx5_txq_release(dev, i);
823 if (txq_ctrl->hairpin_conf.peers[0].port != rx_port) {
824 mlx5_txq_release(dev, i);
827 /* Indeed, only the first used queue needs to be checked. */
828 if (txq_ctrl->hairpin_conf.manual_bind == 0) {
829 if (cur_port != rx_port) {
831 DRV_LOG(ERR, "port %u and port %u are in"
832 " auto-bind mode", cur_port, rx_port);
833 mlx5_txq_release(dev, i);
839 rx_queue = txq_ctrl->hairpin_conf.peers[0].queue;
840 mlx5_txq_release(dev, i);
841 ret = rte_eth_hairpin_queue_peer_unbind(rx_port, rx_queue, 0);
843 DRV_LOG(ERR, "port %u Rx queue %d unbind - failure",
847 ret = mlx5_hairpin_queue_peer_unbind(dev, i, 1);
849 DRV_LOG(ERR, "port %u Tx queue %d unbind - failure",
858 * Bind hairpin ports, Rx could be all ports when using RTE_MAX_ETHPORTS.
859 * @see mlx5_hairpin_bind_single_port()
862 mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port)
866 struct mlx5_priv *priv = dev->data->dev_private;
869 * If the Rx port has no hairpin configuration with the current port,
870 * the binding will be skipped in the called function of single port.
871 * Device started status will be checked only before the queue
872 * information updating.
874 if (rx_port == RTE_MAX_ETHPORTS) {
875 MLX5_ETH_FOREACH_DEV(p, priv->pci_dev) {
876 ret = mlx5_hairpin_bind_single_port(dev, p);
882 return mlx5_hairpin_bind_single_port(dev, rx_port);
885 MLX5_ETH_FOREACH_DEV(pp, priv->pci_dev)
887 mlx5_hairpin_unbind_single_port(dev, pp);
892 * Unbind hairpin ports, Rx could be all ports when using RTE_MAX_ETHPORTS.
893 * @see mlx5_hairpin_unbind_single_port()
896 mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port)
900 struct mlx5_priv *priv = dev->data->dev_private;
902 if (rx_port == RTE_MAX_ETHPORTS)
903 MLX5_ETH_FOREACH_DEV(p, priv->pci_dev) {
904 ret = mlx5_hairpin_unbind_single_port(dev, p);
909 ret = mlx5_hairpin_bind_single_port(dev, rx_port);
914 * DPDK callback to get the hairpin peer ports list.
915 * This will return the actual number of peer ports and save the identifiers
916 * into the array (sorted, may be different from that when setting up the
917 * hairpin peer queues).
918 * The peer port ID could be the same as the port ID of the current device.
921 * Pointer to Ethernet device structure.
923 * Pointer to array to save the port identifiers.
925 * The length of the array.
927 * Current port to peer port direction.
928 * positive - current used as Tx to get all peer Rx ports.
929 * zero - current used as Rx to get all peer Tx ports.
932 * 0 or positive value on success, actual number of peer ports.
933 * a negative errno value otherwise and rte_errno is set.
936 mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,
937 size_t len, uint32_t direction)
939 struct mlx5_priv *priv = dev->data->dev_private;
940 struct mlx5_txq_ctrl *txq_ctrl;
941 struct mlx5_rxq_ctrl *rxq_ctrl;
944 uint32_t bits[(RTE_MAX_ETHPORTS + 31) / 32] = {0};
948 for (i = 0; i < priv->txqs_n; i++) {
949 txq_ctrl = mlx5_txq_get(dev, i);
952 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
953 mlx5_txq_release(dev, i);
956 pp = txq_ctrl->hairpin_conf.peers[0].port;
957 if (pp >= RTE_MAX_ETHPORTS) {
959 mlx5_txq_release(dev, i);
960 DRV_LOG(ERR, "port %hu queue %u peer port "
962 priv->dev_data->port_id, i, pp);
965 bits[pp / 32] |= 1 << (pp % 32);
966 mlx5_txq_release(dev, i);
969 for (i = 0; i < priv->rxqs_n; i++) {
970 rxq_ctrl = mlx5_rxq_get(dev, i);
973 if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {
974 mlx5_rxq_release(dev, i);
977 pp = rxq_ctrl->hairpin_conf.peers[0].port;
978 if (pp >= RTE_MAX_ETHPORTS) {
980 mlx5_rxq_release(dev, i);
981 DRV_LOG(ERR, "port %hu queue %u peer port "
983 priv->dev_data->port_id, i, pp);
986 bits[pp / 32] |= 1 << (pp % 32);
987 mlx5_rxq_release(dev, i);
990 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
991 if (bits[i / 32] & (1 << (i % 32))) {
992 if ((size_t)ret >= len) {
996 peer_ports[ret++] = i;
1003 * DPDK callback to start the device.
1005 * Simulate device start by attaching all configured flows.
1008 * Pointer to Ethernet device structure.
1011 * 0 on success, a negative errno value otherwise and rte_errno is set.
1014 mlx5_dev_start(struct rte_eth_dev *dev)
1016 struct mlx5_priv *priv = dev->data->dev_private;
1020 DRV_LOG(DEBUG, "port %u starting device", dev->data->port_id);
1021 fine_inline = rte_mbuf_dynflag_lookup
1022 (RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, NULL);
1023 if (fine_inline >= 0)
1024 rte_net_mlx5_dynf_inline_mask = 1UL << fine_inline;
1026 rte_net_mlx5_dynf_inline_mask = 0;
1027 if (dev->data->nb_rx_queues > 0) {
1028 ret = mlx5_dev_configure_rss_reta(dev);
1030 DRV_LOG(ERR, "port %u reta config failed: %s",
1031 dev->data->port_id, strerror(rte_errno));
1035 ret = mlx5_txpp_start(dev);
1037 DRV_LOG(ERR, "port %u Tx packet pacing init failed: %s",
1038 dev->data->port_id, strerror(rte_errno));
1041 ret = mlx5_txq_start(dev);
1043 DRV_LOG(ERR, "port %u Tx queue allocation failed: %s",
1044 dev->data->port_id, strerror(rte_errno));
1047 ret = mlx5_rxq_start(dev);
1049 DRV_LOG(ERR, "port %u Rx queue allocation failed: %s",
1050 dev->data->port_id, strerror(rte_errno));
1053 ret = mlx5_hairpin_auto_bind(dev);
1055 DRV_LOG(ERR, "port %u hairpin binding failed: %s",
1056 dev->data->port_id, strerror(rte_errno));
1059 /* Set started flag here for the following steps like control flow. */
1060 dev->data->dev_started = 1;
1061 ret = mlx5_rx_intr_vec_enable(dev);
1063 DRV_LOG(ERR, "port %u Rx interrupt vector creation failed",
1064 dev->data->port_id);
1067 mlx5_os_stats_init(dev);
1068 ret = mlx5_traffic_enable(dev);
1070 DRV_LOG(ERR, "port %u failed to set defaults flows",
1071 dev->data->port_id);
1074 /* Set a mask and offset of dynamic metadata flows into Rx queues. */
1075 mlx5_flow_rxq_dynf_metadata_set(dev);
1076 /* Set flags and context to convert Rx timestamps. */
1077 mlx5_rxq_timestamp_set(dev);
1078 /* Set a mask and offset of scheduling on timestamp into Tx queues. */
1079 mlx5_txq_dynf_timestamp_set(dev);
1081 * In non-cached mode, it only needs to start the default mreg copy
1082 * action and no flow created by application exists anymore.
1083 * But it is worth wrapping the interface for further usage.
1085 ret = mlx5_flow_start_default(dev);
1087 DRV_LOG(DEBUG, "port %u failed to start default actions: %s",
1088 dev->data->port_id, strerror(rte_errno));
1092 dev->tx_pkt_burst = mlx5_select_tx_function(dev);
1093 dev->rx_pkt_burst = mlx5_select_rx_function(dev);
1094 /* Enable datapath on secondary process. */
1095 mlx5_mp_os_req_start_rxtx(dev);
1096 if (priv->sh->intr_handle.fd >= 0) {
1097 priv->sh->port[priv->dev_port - 1].ih_port_id =
1098 (uint32_t)dev->data->port_id;
1100 DRV_LOG(INFO, "port %u starts without LSC and RMV interrupts.",
1101 dev->data->port_id);
1102 dev->data->dev_conf.intr_conf.lsc = 0;
1103 dev->data->dev_conf.intr_conf.rmv = 0;
1105 if (priv->sh->intr_handle_devx.fd >= 0)
1106 priv->sh->port[priv->dev_port - 1].devx_ih_port_id =
1107 (uint32_t)dev->data->port_id;
1110 ret = rte_errno; /* Save rte_errno before cleanup. */
1112 dev->data->dev_started = 0;
1113 mlx5_flow_stop_default(dev);
1114 mlx5_traffic_disable(dev);
1117 mlx5_txpp_stop(dev); /* Stop last. */
1118 rte_errno = ret; /* Restore rte_errno. */
1123 * DPDK callback to stop the device.
1125 * Simulate device stop by detaching all configured flows.
1128 * Pointer to Ethernet device structure.
1131 mlx5_dev_stop(struct rte_eth_dev *dev)
1133 struct mlx5_priv *priv = dev->data->dev_private;
1135 dev->data->dev_started = 0;
1136 /* Prevent crashes when queues are still in use. */
1137 dev->rx_pkt_burst = removed_rx_burst;
1138 dev->tx_pkt_burst = removed_tx_burst;
1140 /* Disable datapath on secondary process. */
1141 mlx5_mp_os_req_stop_rxtx(dev);
1142 usleep(1000 * priv->rxqs_n);
1143 DRV_LOG(DEBUG, "port %u stopping device", dev->data->port_id);
1144 mlx5_flow_stop_default(dev);
1145 /* Control flows for default traffic can be removed firstly. */
1146 mlx5_traffic_disable(dev);
1147 /* All RX queue flags will be cleared in the flush interface. */
1148 mlx5_flow_list_flush(dev, &priv->flows, true);
1149 mlx5_rx_intr_vec_disable(dev);
1150 priv->sh->port[priv->dev_port - 1].ih_port_id = RTE_MAX_ETHPORTS;
1151 priv->sh->port[priv->dev_port - 1].devx_ih_port_id = RTE_MAX_ETHPORTS;
1154 mlx5_txpp_stop(dev);
1160 * Enable traffic flows configured by control plane
1163 * Pointer to Ethernet device private data.
1165 * Pointer to Ethernet device structure.
1168 * 0 on success, a negative errno value otherwise and rte_errno is set.
1171 mlx5_traffic_enable(struct rte_eth_dev *dev)
1173 struct mlx5_priv *priv = dev->data->dev_private;
1174 struct rte_flow_item_eth bcast = {
1175 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1177 struct rte_flow_item_eth ipv6_multi_spec = {
1178 .dst.addr_bytes = "\x33\x33\x00\x00\x00\x00",
1180 struct rte_flow_item_eth ipv6_multi_mask = {
1181 .dst.addr_bytes = "\xff\xff\x00\x00\x00\x00",
1183 struct rte_flow_item_eth unicast = {
1184 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00",
1186 struct rte_flow_item_eth unicast_mask = {
1187 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1189 const unsigned int vlan_filter_n = priv->vlan_filter_n;
1190 const struct rte_ether_addr cmp = {
1191 .addr_bytes = "\x00\x00\x00\x00\x00\x00",
1198 * Hairpin txq default flow should be created no matter if it is
1199 * isolation mode. Or else all the packets to be sent will be sent
1200 * out directly without the TX flow actions, e.g. encapsulation.
1202 for (i = 0; i != priv->txqs_n; ++i) {
1203 struct mlx5_txq_ctrl *txq_ctrl = mlx5_txq_get(dev, i);
1206 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {
1207 ret = mlx5_ctrl_flow_source_queue(dev, i);
1209 mlx5_txq_release(dev, i);
1213 mlx5_txq_release(dev, i);
1215 if (priv->config.dv_esw_en && !priv->config.vf) {
1216 if (mlx5_flow_create_esw_table_zero_flow(dev))
1217 priv->fdb_def_rule = 1;
1219 DRV_LOG(INFO, "port %u FDB default rule cannot be"
1220 " configured - only Eswitch group 0 flows are"
1221 " supported.", dev->data->port_id);
1223 if (!priv->config.lacp_by_user && priv->pf_bond >= 0) {
1224 ret = mlx5_flow_lacp_miss(dev);
1226 DRV_LOG(INFO, "port %u LACP rule cannot be created - "
1227 "forward LACP to kernel.", dev->data->port_id);
1229 DRV_LOG(INFO, "LACP traffic will be missed in port %u."
1230 , dev->data->port_id);
1234 if (dev->data->promiscuous) {
1235 struct rte_flow_item_eth promisc = {
1236 .dst.addr_bytes = "\x00\x00\x00\x00\x00\x00",
1237 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00",
1241 ret = mlx5_ctrl_flow(dev, &promisc, &promisc);
1245 if (dev->data->all_multicast) {
1246 struct rte_flow_item_eth multicast = {
1247 .dst.addr_bytes = "\x01\x00\x00\x00\x00\x00",
1248 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00",
1252 ret = mlx5_ctrl_flow(dev, &multicast, &multicast);
1256 /* Add broadcast/multicast flows. */
1257 for (i = 0; i != vlan_filter_n; ++i) {
1258 uint16_t vlan = priv->vlan_filter[i];
1260 struct rte_flow_item_vlan vlan_spec = {
1261 .tci = rte_cpu_to_be_16(vlan),
1263 struct rte_flow_item_vlan vlan_mask =
1264 rte_flow_item_vlan_mask;
1266 ret = mlx5_ctrl_flow_vlan(dev, &bcast, &bcast,
1267 &vlan_spec, &vlan_mask);
1270 ret = mlx5_ctrl_flow_vlan(dev, &ipv6_multi_spec,
1272 &vlan_spec, &vlan_mask);
1276 if (!vlan_filter_n) {
1277 ret = mlx5_ctrl_flow(dev, &bcast, &bcast);
1280 ret = mlx5_ctrl_flow(dev, &ipv6_multi_spec,
1286 /* Add MAC address flows. */
1287 for (i = 0; i != MLX5_MAX_MAC_ADDRESSES; ++i) {
1288 struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
1290 if (!memcmp(mac, &cmp, sizeof(*mac)))
1292 memcpy(&unicast.dst.addr_bytes,
1294 RTE_ETHER_ADDR_LEN);
1295 for (j = 0; j != vlan_filter_n; ++j) {
1296 uint16_t vlan = priv->vlan_filter[j];
1298 struct rte_flow_item_vlan vlan_spec = {
1299 .tci = rte_cpu_to_be_16(vlan),
1301 struct rte_flow_item_vlan vlan_mask =
1302 rte_flow_item_vlan_mask;
1304 ret = mlx5_ctrl_flow_vlan(dev, &unicast,
1311 if (!vlan_filter_n) {
1312 ret = mlx5_ctrl_flow(dev, &unicast, &unicast_mask);
1319 ret = rte_errno; /* Save rte_errno before cleanup. */
1320 mlx5_flow_list_flush(dev, &priv->ctrl_flows, false);
1321 rte_errno = ret; /* Restore rte_errno. */
1327 * Disable traffic flows configured by control plane
1330 * Pointer to Ethernet device private data.
1333 mlx5_traffic_disable(struct rte_eth_dev *dev)
1335 struct mlx5_priv *priv = dev->data->dev_private;
1337 mlx5_flow_list_flush(dev, &priv->ctrl_flows, false);
1341 * Restart traffic flows configured by control plane
1344 * Pointer to Ethernet device private data.
1347 * 0 on success, a negative errno value otherwise and rte_errno is set.
1350 mlx5_traffic_restart(struct rte_eth_dev *dev)
1352 if (dev->data->dev_started) {
1353 mlx5_traffic_disable(dev);
1354 return mlx5_traffic_enable(dev);