1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
9 #include <ethdev_driver.h>
10 #include <rte_interrupts.h>
11 #include <rte_alarm.h>
12 #include <rte_cycles.h>
14 #include <mlx5_malloc.h>
17 #include "mlx5_flow.h"
20 #include "mlx5_utils.h"
21 #include "rte_pmd_mlx5.h"
24 * Stop traffic on Tx queues.
27 * Pointer to Ethernet device structure.
30 mlx5_txq_stop(struct rte_eth_dev *dev)
32 struct mlx5_priv *priv = dev->data->dev_private;
35 for (i = 0; i != priv->txqs_n; ++i)
36 mlx5_txq_release(dev, i);
40 * Start traffic on Tx queues.
43 * Pointer to Ethernet device structure.
46 * 0 on success, a negative errno value otherwise and rte_errno is set.
49 mlx5_txq_start(struct rte_eth_dev *dev)
51 struct mlx5_priv *priv = dev->data->dev_private;
55 for (i = 0; i != priv->txqs_n; ++i) {
56 struct mlx5_txq_ctrl *txq_ctrl = mlx5_txq_get(dev, i);
57 struct mlx5_txq_data *txq_data = &txq_ctrl->txq;
58 uint32_t flags = MLX5_MEM_RTE | MLX5_MEM_ZERO;
62 if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD)
63 txq_alloc_elts(txq_ctrl);
64 MLX5_ASSERT(!txq_ctrl->obj);
65 txq_ctrl->obj = mlx5_malloc(flags, sizeof(struct mlx5_txq_obj),
68 DRV_LOG(ERR, "Port %u Tx queue %u cannot allocate "
69 "memory resources.", dev->data->port_id,
74 ret = priv->obj_ops.txq_obj_new(dev, i);
76 mlx5_free(txq_ctrl->obj);
80 if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD) {
81 size_t size = txq_data->cqe_s * sizeof(*txq_data->fcqs);
83 txq_data->fcqs = mlx5_malloc(flags, size,
86 if (!txq_data->fcqs) {
87 DRV_LOG(ERR, "Port %u Tx queue %u cannot "
88 "allocate memory (FCQ).",
89 dev->data->port_id, i);
94 DRV_LOG(DEBUG, "Port %u txq %u updated with %p.",
95 dev->data->port_id, i, (void *)&txq_ctrl->obj);
96 LIST_INSERT_HEAD(&priv->txqsobj, txq_ctrl->obj, next);
100 ret = rte_errno; /* Save rte_errno before cleanup. */
102 mlx5_txq_release(dev, i);
104 rte_errno = ret; /* Restore rte_errno. */
109 * Translate the chunk address to MR key in order to put in into the cache.
112 mlx5_rxq_mempool_register_cb(struct rte_mempool *mp, void *opaque,
113 struct rte_mempool_memhdr *memhdr,
116 struct mlx5_rxq_data *rxq = opaque;
120 mlx5_rx_addr2mr(rxq, (uintptr_t)memhdr->addr);
124 * Register Rx queue mempools and fill the Rx queue cache.
125 * This function tolerates repeated mempool registration.
127 * @param[in] rxq_ctrl
128 * Rx queue control data.
131 * 0 on success, (-1) on failure and rte_errno is set.
134 mlx5_rxq_mempool_register(struct mlx5_rxq_ctrl *rxq_ctrl)
136 struct mlx5_priv *priv = rxq_ctrl->priv;
137 struct rte_mempool *mp;
141 mlx5_mr_flush_local_cache(&rxq_ctrl->rxq.mr_ctrl);
142 /* MPRQ mempool is registered on creation, just fill the cache. */
143 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq)) {
144 rte_mempool_mem_iter(rxq_ctrl->rxq.mprq_mp,
145 mlx5_rxq_mempool_register_cb,
149 for (s = 0; s < rxq_ctrl->rxq.rxseg_n; s++) {
150 mp = rxq_ctrl->rxq.rxseg[s].mp;
151 ret = mlx5_mr_mempool_register(&priv->sh->cdev->mr_scache,
152 priv->sh->cdev->pd, mp,
154 if (ret < 0 && rte_errno != EEXIST)
156 rte_mempool_mem_iter(mp, mlx5_rxq_mempool_register_cb,
163 * Stop traffic on Rx queues.
166 * Pointer to Ethernet device structure.
169 mlx5_rxq_stop(struct rte_eth_dev *dev)
171 struct mlx5_priv *priv = dev->data->dev_private;
174 for (i = 0; i != priv->rxqs_n; ++i)
175 mlx5_rxq_release(dev, i);
179 * Start traffic on Rx queues.
182 * Pointer to Ethernet device structure.
185 * 0 on success, a negative errno value otherwise and rte_errno is set.
188 mlx5_rxq_start(struct rte_eth_dev *dev)
190 struct mlx5_priv *priv = dev->data->dev_private;
194 /* Allocate/reuse/resize mempool for Multi-Packet RQ. */
195 if (mlx5_mprq_alloc_mp(dev)) {
196 /* Should not release Rx queues but return immediately. */
199 DRV_LOG(DEBUG, "Port %u device_attr.max_qp_wr is %d.",
200 dev->data->port_id, priv->sh->device_attr.max_qp_wr);
201 DRV_LOG(DEBUG, "Port %u device_attr.max_sge is %d.",
202 dev->data->port_id, priv->sh->device_attr.max_sge);
203 for (i = 0; i != priv->rxqs_n; ++i) {
204 struct mlx5_rxq_priv *rxq = mlx5_rxq_ref(dev, i);
205 struct mlx5_rxq_ctrl *rxq_ctrl;
209 rxq_ctrl = rxq->ctrl;
210 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) {
212 * Pre-register the mempools. Regardless of whether
213 * the implicit registration is enabled or not,
214 * Rx mempool destruction is tracked to free MRs.
216 if (mlx5_rxq_mempool_register(rxq_ctrl) < 0)
218 ret = rxq_alloc_elts(rxq_ctrl);
222 MLX5_ASSERT(!rxq_ctrl->obj);
223 rxq_ctrl->obj = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
224 sizeof(*rxq_ctrl->obj), 0,
226 if (!rxq_ctrl->obj) {
228 "Port %u Rx queue %u can't allocate resources.",
229 dev->data->port_id, (*priv->rxqs)[i]->idx);
233 ret = priv->obj_ops.rxq_obj_new(dev, i);
235 mlx5_free(rxq_ctrl->obj);
236 rxq_ctrl->obj = NULL;
239 DRV_LOG(DEBUG, "Port %u rxq %u updated with %p.",
240 dev->data->port_id, i, (void *)&rxq_ctrl->obj);
241 LIST_INSERT_HEAD(&priv->rxqsobj, rxq_ctrl->obj, next);
245 ret = rte_errno; /* Save rte_errno before cleanup. */
247 mlx5_rxq_release(dev, i);
249 rte_errno = ret; /* Restore rte_errno. */
254 * Binds Tx queues to Rx queues for hairpin.
256 * Binds Tx queues to the target Rx queues.
259 * Pointer to Ethernet device structure.
262 * 0 on success, a negative errno value otherwise and rte_errno is set.
265 mlx5_hairpin_auto_bind(struct rte_eth_dev *dev)
267 struct mlx5_priv *priv = dev->data->dev_private;
268 struct mlx5_devx_modify_sq_attr sq_attr = { 0 };
269 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
270 struct mlx5_txq_ctrl *txq_ctrl;
271 struct mlx5_rxq_priv *rxq;
272 struct mlx5_rxq_ctrl *rxq_ctrl;
273 struct mlx5_devx_obj *sq;
274 struct mlx5_devx_obj *rq;
277 bool need_auto = false;
278 uint16_t self_port = dev->data->port_id;
280 for (i = 0; i != priv->txqs_n; ++i) {
281 txq_ctrl = mlx5_txq_get(dev, i);
284 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN ||
285 txq_ctrl->hairpin_conf.peers[0].port != self_port) {
286 mlx5_txq_release(dev, i);
289 if (txq_ctrl->hairpin_conf.manual_bind) {
290 mlx5_txq_release(dev, i);
294 mlx5_txq_release(dev, i);
298 for (i = 0; i != priv->txqs_n; ++i) {
299 txq_ctrl = mlx5_txq_get(dev, i);
302 /* Skip hairpin queues with other peer ports. */
303 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN ||
304 txq_ctrl->hairpin_conf.peers[0].port != self_port) {
305 mlx5_txq_release(dev, i);
308 if (!txq_ctrl->obj) {
310 DRV_LOG(ERR, "port %u no txq object found: %d",
311 dev->data->port_id, i);
312 mlx5_txq_release(dev, i);
315 sq = txq_ctrl->obj->sq;
316 rxq = mlx5_rxq_get(dev, txq_ctrl->hairpin_conf.peers[0].queue);
318 mlx5_txq_release(dev, i);
320 DRV_LOG(ERR, "port %u no rxq object found: %d",
322 txq_ctrl->hairpin_conf.peers[0].queue);
325 rxq_ctrl = rxq->ctrl;
326 if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN ||
327 rxq_ctrl->hairpin_conf.peers[0].queue != i) {
329 DRV_LOG(ERR, "port %u Tx queue %d can't be binded to "
330 "Rx queue %d", dev->data->port_id,
331 i, txq_ctrl->hairpin_conf.peers[0].queue);
334 rq = rxq_ctrl->obj->rq;
337 DRV_LOG(ERR, "port %u hairpin no matching rxq: %d",
339 txq_ctrl->hairpin_conf.peers[0].queue);
342 sq_attr.state = MLX5_SQC_STATE_RDY;
343 sq_attr.sq_state = MLX5_SQC_STATE_RST;
344 sq_attr.hairpin_peer_rq = rq->id;
345 sq_attr.hairpin_peer_vhca = priv->config.hca_attr.vhca_id;
346 ret = mlx5_devx_cmd_modify_sq(sq, &sq_attr);
349 rq_attr.state = MLX5_SQC_STATE_RDY;
350 rq_attr.rq_state = MLX5_SQC_STATE_RST;
351 rq_attr.hairpin_peer_sq = sq->id;
352 rq_attr.hairpin_peer_vhca = priv->config.hca_attr.vhca_id;
353 ret = mlx5_devx_cmd_modify_rq(rq, &rq_attr);
356 /* Qs with auto-bind will be destroyed directly. */
357 rxq_ctrl->hairpin_status = 1;
358 txq_ctrl->hairpin_status = 1;
359 mlx5_txq_release(dev, i);
363 mlx5_txq_release(dev, i);
368 * Fetch the peer queue's SW & HW information.
371 * Pointer to Ethernet device structure.
373 * Index of the queue to fetch the information.
374 * @param current_info
375 * Pointer to the input peer information, not used currently.
377 * Pointer to the structure to store the information, output.
379 * Positive to get the RxQ information, zero to get the TxQ information.
382 * 0 on success, a negative errno value otherwise and rte_errno is set.
385 mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,
386 struct rte_hairpin_peer_info *current_info,
387 struct rte_hairpin_peer_info *peer_info,
390 struct mlx5_priv *priv = dev->data->dev_private;
391 RTE_SET_USED(current_info);
393 if (dev->data->dev_started == 0) {
395 DRV_LOG(ERR, "peer port %u is not started",
400 * Peer port used as egress. In the current design, hairpin Tx queue
401 * will be bound to the peer Rx queue. Indeed, only the information of
402 * peer Rx queue needs to be fetched.
404 if (direction == 0) {
405 struct mlx5_txq_ctrl *txq_ctrl;
407 txq_ctrl = mlx5_txq_get(dev, peer_queue);
408 if (txq_ctrl == NULL) {
410 DRV_LOG(ERR, "Failed to get port %u Tx queue %d",
411 dev->data->port_id, peer_queue);
414 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
416 DRV_LOG(ERR, "port %u queue %d is not a hairpin Txq",
417 dev->data->port_id, peer_queue);
418 mlx5_txq_release(dev, peer_queue);
421 if (txq_ctrl->obj == NULL || txq_ctrl->obj->sq == NULL) {
423 DRV_LOG(ERR, "port %u no Txq object found: %d",
424 dev->data->port_id, peer_queue);
425 mlx5_txq_release(dev, peer_queue);
428 peer_info->qp_id = txq_ctrl->obj->sq->id;
429 peer_info->vhca_id = priv->config.hca_attr.vhca_id;
430 /* 1-to-1 mapping, only the first one is used. */
431 peer_info->peer_q = txq_ctrl->hairpin_conf.peers[0].queue;
432 peer_info->tx_explicit = txq_ctrl->hairpin_conf.tx_explicit;
433 peer_info->manual_bind = txq_ctrl->hairpin_conf.manual_bind;
434 mlx5_txq_release(dev, peer_queue);
435 } else { /* Peer port used as ingress. */
436 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, peer_queue);
437 struct mlx5_rxq_ctrl *rxq_ctrl;
441 DRV_LOG(ERR, "Failed to get port %u Rx queue %d",
442 dev->data->port_id, peer_queue);
445 rxq_ctrl = rxq->ctrl;
446 if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {
448 DRV_LOG(ERR, "port %u queue %d is not a hairpin Rxq",
449 dev->data->port_id, peer_queue);
452 if (rxq_ctrl->obj == NULL || rxq_ctrl->obj->rq == NULL) {
454 DRV_LOG(ERR, "port %u no Rxq object found: %d",
455 dev->data->port_id, peer_queue);
458 peer_info->qp_id = rxq_ctrl->obj->rq->id;
459 peer_info->vhca_id = priv->config.hca_attr.vhca_id;
460 peer_info->peer_q = rxq_ctrl->hairpin_conf.peers[0].queue;
461 peer_info->tx_explicit = rxq_ctrl->hairpin_conf.tx_explicit;
462 peer_info->manual_bind = rxq_ctrl->hairpin_conf.manual_bind;
468 * Bind the hairpin queue with the peer HW information.
469 * This needs to be called twice both for Tx and Rx queues of a pair.
470 * If the queue is already bound, it is considered successful.
473 * Pointer to Ethernet device structure.
475 * Index of the queue to change the HW configuration to bind.
477 * Pointer to information of the peer queue.
479 * Positive to configure the TxQ, zero to configure the RxQ.
482 * 0 on success, a negative errno value otherwise and rte_errno is set.
485 mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,
486 struct rte_hairpin_peer_info *peer_info,
492 * Consistency checking of the peer queue: opposite direction is used
493 * to get the peer queue info with ethdev port ID, no need to check.
495 if (peer_info->peer_q != cur_queue) {
497 DRV_LOG(ERR, "port %u queue %d and peer queue %d mismatch",
498 dev->data->port_id, cur_queue, peer_info->peer_q);
501 if (direction != 0) {
502 struct mlx5_txq_ctrl *txq_ctrl;
503 struct mlx5_devx_modify_sq_attr sq_attr = { 0 };
505 txq_ctrl = mlx5_txq_get(dev, cur_queue);
506 if (txq_ctrl == NULL) {
508 DRV_LOG(ERR, "Failed to get port %u Tx queue %d",
509 dev->data->port_id, cur_queue);
512 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
514 DRV_LOG(ERR, "port %u queue %d not a hairpin Txq",
515 dev->data->port_id, cur_queue);
516 mlx5_txq_release(dev, cur_queue);
519 if (txq_ctrl->obj == NULL || txq_ctrl->obj->sq == NULL) {
521 DRV_LOG(ERR, "port %u no Txq object found: %d",
522 dev->data->port_id, cur_queue);
523 mlx5_txq_release(dev, cur_queue);
526 if (txq_ctrl->hairpin_status != 0) {
527 DRV_LOG(DEBUG, "port %u Tx queue %d is already bound",
528 dev->data->port_id, cur_queue);
529 mlx5_txq_release(dev, cur_queue);
533 * All queues' of one port consistency checking is done in the
534 * bind() function, and that is optional.
536 if (peer_info->tx_explicit !=
537 txq_ctrl->hairpin_conf.tx_explicit) {
539 DRV_LOG(ERR, "port %u Tx queue %d and peer Tx rule mode"
540 " mismatch", dev->data->port_id, cur_queue);
541 mlx5_txq_release(dev, cur_queue);
544 if (peer_info->manual_bind !=
545 txq_ctrl->hairpin_conf.manual_bind) {
547 DRV_LOG(ERR, "port %u Tx queue %d and peer binding mode"
548 " mismatch", dev->data->port_id, cur_queue);
549 mlx5_txq_release(dev, cur_queue);
552 sq_attr.state = MLX5_SQC_STATE_RDY;
553 sq_attr.sq_state = MLX5_SQC_STATE_RST;
554 sq_attr.hairpin_peer_rq = peer_info->qp_id;
555 sq_attr.hairpin_peer_vhca = peer_info->vhca_id;
556 ret = mlx5_devx_cmd_modify_sq(txq_ctrl->obj->sq, &sq_attr);
558 txq_ctrl->hairpin_status = 1;
559 mlx5_txq_release(dev, cur_queue);
561 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, cur_queue);
562 struct mlx5_rxq_ctrl *rxq_ctrl;
563 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
567 DRV_LOG(ERR, "Failed to get port %u Rx queue %d",
568 dev->data->port_id, cur_queue);
571 rxq_ctrl = rxq->ctrl;
572 if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {
574 DRV_LOG(ERR, "port %u queue %d not a hairpin Rxq",
575 dev->data->port_id, cur_queue);
578 if (rxq_ctrl->obj == NULL || rxq_ctrl->obj->rq == NULL) {
580 DRV_LOG(ERR, "port %u no Rxq object found: %d",
581 dev->data->port_id, cur_queue);
584 if (rxq_ctrl->hairpin_status != 0) {
585 DRV_LOG(DEBUG, "port %u Rx queue %d is already bound",
586 dev->data->port_id, cur_queue);
589 if (peer_info->tx_explicit !=
590 rxq_ctrl->hairpin_conf.tx_explicit) {
592 DRV_LOG(ERR, "port %u Rx queue %d and peer Tx rule mode"
593 " mismatch", dev->data->port_id, cur_queue);
596 if (peer_info->manual_bind !=
597 rxq_ctrl->hairpin_conf.manual_bind) {
599 DRV_LOG(ERR, "port %u Rx queue %d and peer binding mode"
600 " mismatch", dev->data->port_id, cur_queue);
603 rq_attr.state = MLX5_SQC_STATE_RDY;
604 rq_attr.rq_state = MLX5_SQC_STATE_RST;
605 rq_attr.hairpin_peer_sq = peer_info->qp_id;
606 rq_attr.hairpin_peer_vhca = peer_info->vhca_id;
607 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);
609 rxq_ctrl->hairpin_status = 1;
615 * Unbind the hairpin queue and reset its HW configuration.
616 * This needs to be called twice both for Tx and Rx queues of a pair.
617 * If the queue is already unbound, it is considered successful.
620 * Pointer to Ethernet device structure.
622 * Index of the queue to change the HW configuration to unbind.
624 * Positive to reset the TxQ, zero to reset the RxQ.
627 * 0 on success, a negative errno value otherwise and rte_errno is set.
630 mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,
635 if (direction != 0) {
636 struct mlx5_txq_ctrl *txq_ctrl;
637 struct mlx5_devx_modify_sq_attr sq_attr = { 0 };
639 txq_ctrl = mlx5_txq_get(dev, cur_queue);
640 if (txq_ctrl == NULL) {
642 DRV_LOG(ERR, "Failed to get port %u Tx queue %d",
643 dev->data->port_id, cur_queue);
646 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
648 DRV_LOG(ERR, "port %u queue %d not a hairpin Txq",
649 dev->data->port_id, cur_queue);
650 mlx5_txq_release(dev, cur_queue);
653 /* Already unbound, return success before obj checking. */
654 if (txq_ctrl->hairpin_status == 0) {
655 DRV_LOG(DEBUG, "port %u Tx queue %d is already unbound",
656 dev->data->port_id, cur_queue);
657 mlx5_txq_release(dev, cur_queue);
660 if (!txq_ctrl->obj || !txq_ctrl->obj->sq) {
662 DRV_LOG(ERR, "port %u no Txq object found: %d",
663 dev->data->port_id, cur_queue);
664 mlx5_txq_release(dev, cur_queue);
667 sq_attr.state = MLX5_SQC_STATE_RST;
668 sq_attr.sq_state = MLX5_SQC_STATE_RST;
669 ret = mlx5_devx_cmd_modify_sq(txq_ctrl->obj->sq, &sq_attr);
671 txq_ctrl->hairpin_status = 0;
672 mlx5_txq_release(dev, cur_queue);
674 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, cur_queue);
675 struct mlx5_rxq_ctrl *rxq_ctrl;
676 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
680 DRV_LOG(ERR, "Failed to get port %u Rx queue %d",
681 dev->data->port_id, cur_queue);
684 rxq_ctrl = rxq->ctrl;
685 if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {
687 DRV_LOG(ERR, "port %u queue %d not a hairpin Rxq",
688 dev->data->port_id, cur_queue);
691 if (rxq_ctrl->hairpin_status == 0) {
692 DRV_LOG(DEBUG, "port %u Rx queue %d is already unbound",
693 dev->data->port_id, cur_queue);
696 if (rxq_ctrl->obj == NULL || rxq_ctrl->obj->rq == NULL) {
698 DRV_LOG(ERR, "port %u no Rxq object found: %d",
699 dev->data->port_id, cur_queue);
702 rq_attr.state = MLX5_SQC_STATE_RST;
703 rq_attr.rq_state = MLX5_SQC_STATE_RST;
704 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);
706 rxq_ctrl->hairpin_status = 0;
712 * Bind the hairpin port pairs, from the Tx to the peer Rx.
713 * This function only supports to bind the Tx to one Rx.
716 * Pointer to Ethernet device structure.
718 * Port identifier of the Rx port.
721 * 0 on success, a negative errno value otherwise and rte_errno is set.
724 mlx5_hairpin_bind_single_port(struct rte_eth_dev *dev, uint16_t rx_port)
726 struct mlx5_priv *priv = dev->data->dev_private;
728 struct mlx5_txq_ctrl *txq_ctrl;
730 struct rte_hairpin_peer_info peer = {0xffffff};
731 struct rte_hairpin_peer_info cur;
732 const struct rte_eth_hairpin_conf *conf;
734 uint16_t local_port = priv->dev_data->port_id;
739 if (mlx5_eth_find_next(rx_port, dev->device) != rx_port) {
741 DRV_LOG(ERR, "Rx port %u does not belong to mlx5", rx_port);
745 * Before binding TxQ to peer RxQ, first round loop will be used for
746 * checking the queues' configuration consistency. This would be a
747 * little time consuming but better than doing the rollback.
749 for (i = 0; i != priv->txqs_n; i++) {
750 txq_ctrl = mlx5_txq_get(dev, i);
751 if (txq_ctrl == NULL)
753 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
754 mlx5_txq_release(dev, i);
758 * All hairpin Tx queues of a single port that connected to the
759 * same peer Rx port should have the same "auto binding" and
760 * "implicit Tx flow" modes.
761 * Peer consistency checking will be done in per queue binding.
763 conf = &txq_ctrl->hairpin_conf;
764 if (conf->peers[0].port == rx_port) {
766 manual = conf->manual_bind;
767 explicit = conf->tx_explicit;
769 if (manual != conf->manual_bind ||
770 explicit != conf->tx_explicit) {
772 DRV_LOG(ERR, "port %u queue %d mode"
773 " mismatch: %u %u, %u %u",
774 local_port, i, manual,
775 conf->manual_bind, explicit,
777 mlx5_txq_release(dev, i);
783 mlx5_txq_release(dev, i);
785 /* Once no queue is configured, success is returned directly. */
788 /* All the hairpin TX queues need to be traversed again. */
789 for (i = 0; i != priv->txqs_n; i++) {
790 txq_ctrl = mlx5_txq_get(dev, i);
791 if (txq_ctrl == NULL)
793 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
794 mlx5_txq_release(dev, i);
797 if (txq_ctrl->hairpin_conf.peers[0].port != rx_port) {
798 mlx5_txq_release(dev, i);
801 rx_queue = txq_ctrl->hairpin_conf.peers[0].queue;
803 * Fetch peer RxQ's information.
804 * No need to pass the information of the current queue.
806 ret = rte_eth_hairpin_queue_peer_update(rx_port, rx_queue,
809 mlx5_txq_release(dev, i);
812 /* Accessing its own device, inside mlx5 PMD. */
813 ret = mlx5_hairpin_queue_peer_bind(dev, i, &peer, 1);
815 mlx5_txq_release(dev, i);
818 /* Pass TxQ's information to peer RxQ and try binding. */
819 cur.peer_q = rx_queue;
820 cur.qp_id = txq_ctrl->obj->sq->id;
821 cur.vhca_id = priv->config.hca_attr.vhca_id;
822 cur.tx_explicit = txq_ctrl->hairpin_conf.tx_explicit;
823 cur.manual_bind = txq_ctrl->hairpin_conf.manual_bind;
825 * In order to access another device in a proper way, RTE level
826 * private function is needed.
828 ret = rte_eth_hairpin_queue_peer_bind(rx_port, rx_queue,
831 mlx5_txq_release(dev, i);
834 mlx5_txq_release(dev, i);
839 * Do roll-back process for the queues already bound.
840 * No need to check the return value of the queue unbind function.
843 /* No validation is needed here. */
844 txq_ctrl = mlx5_txq_get(dev, i);
845 if (txq_ctrl == NULL)
847 rx_queue = txq_ctrl->hairpin_conf.peers[0].queue;
848 rte_eth_hairpin_queue_peer_unbind(rx_port, rx_queue, 0);
849 mlx5_hairpin_queue_peer_unbind(dev, i, 1);
850 mlx5_txq_release(dev, i);
856 * Unbind the hairpin port pair, HW configuration of both devices will be clear
857 * and status will be reset for all the queues used between the them.
858 * This function only supports to unbind the Tx from one Rx.
861 * Pointer to Ethernet device structure.
863 * Port identifier of the Rx port.
866 * 0 on success, a negative errno value otherwise and rte_errno is set.
869 mlx5_hairpin_unbind_single_port(struct rte_eth_dev *dev, uint16_t rx_port)
871 struct mlx5_priv *priv = dev->data->dev_private;
872 struct mlx5_txq_ctrl *txq_ctrl;
875 uint16_t cur_port = priv->dev_data->port_id;
877 if (mlx5_eth_find_next(rx_port, dev->device) != rx_port) {
879 DRV_LOG(ERR, "Rx port %u does not belong to mlx5", rx_port);
882 for (i = 0; i != priv->txqs_n; i++) {
885 txq_ctrl = mlx5_txq_get(dev, i);
886 if (txq_ctrl == NULL)
888 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
889 mlx5_txq_release(dev, i);
892 if (txq_ctrl->hairpin_conf.peers[0].port != rx_port) {
893 mlx5_txq_release(dev, i);
896 /* Indeed, only the first used queue needs to be checked. */
897 if (txq_ctrl->hairpin_conf.manual_bind == 0) {
898 if (cur_port != rx_port) {
900 DRV_LOG(ERR, "port %u and port %u are in"
901 " auto-bind mode", cur_port, rx_port);
902 mlx5_txq_release(dev, i);
908 rx_queue = txq_ctrl->hairpin_conf.peers[0].queue;
909 mlx5_txq_release(dev, i);
910 ret = rte_eth_hairpin_queue_peer_unbind(rx_port, rx_queue, 0);
912 DRV_LOG(ERR, "port %u Rx queue %d unbind - failure",
916 ret = mlx5_hairpin_queue_peer_unbind(dev, i, 1);
918 DRV_LOG(ERR, "port %u Tx queue %d unbind - failure",
927 * Bind hairpin ports, Rx could be all ports when using RTE_MAX_ETHPORTS.
928 * @see mlx5_hairpin_bind_single_port()
931 mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port)
937 * If the Rx port has no hairpin configuration with the current port,
938 * the binding will be skipped in the called function of single port.
939 * Device started status will be checked only before the queue
940 * information updating.
942 if (rx_port == RTE_MAX_ETHPORTS) {
943 MLX5_ETH_FOREACH_DEV(p, dev->device) {
944 ret = mlx5_hairpin_bind_single_port(dev, p);
950 return mlx5_hairpin_bind_single_port(dev, rx_port);
953 MLX5_ETH_FOREACH_DEV(pp, dev->device)
955 mlx5_hairpin_unbind_single_port(dev, pp);
960 * Unbind hairpin ports, Rx could be all ports when using RTE_MAX_ETHPORTS.
961 * @see mlx5_hairpin_unbind_single_port()
964 mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port)
969 if (rx_port == RTE_MAX_ETHPORTS)
970 MLX5_ETH_FOREACH_DEV(p, dev->device) {
971 ret = mlx5_hairpin_unbind_single_port(dev, p);
976 ret = mlx5_hairpin_unbind_single_port(dev, rx_port);
981 * DPDK callback to get the hairpin peer ports list.
982 * This will return the actual number of peer ports and save the identifiers
983 * into the array (sorted, may be different from that when setting up the
984 * hairpin peer queues).
985 * The peer port ID could be the same as the port ID of the current device.
988 * Pointer to Ethernet device structure.
990 * Pointer to array to save the port identifiers.
992 * The length of the array.
994 * Current port to peer port direction.
995 * positive - current used as Tx to get all peer Rx ports.
996 * zero - current used as Rx to get all peer Tx ports.
999 * 0 or positive value on success, actual number of peer ports.
1000 * a negative errno value otherwise and rte_errno is set.
1003 mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,
1004 size_t len, uint32_t direction)
1006 struct mlx5_priv *priv = dev->data->dev_private;
1007 struct mlx5_txq_ctrl *txq_ctrl;
1010 uint32_t bits[(RTE_MAX_ETHPORTS + 31) / 32] = {0};
1014 for (i = 0; i < priv->txqs_n; i++) {
1015 txq_ctrl = mlx5_txq_get(dev, i);
1018 if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
1019 mlx5_txq_release(dev, i);
1022 pp = txq_ctrl->hairpin_conf.peers[0].port;
1023 if (pp >= RTE_MAX_ETHPORTS) {
1025 mlx5_txq_release(dev, i);
1026 DRV_LOG(ERR, "port %hu queue %u peer port "
1028 priv->dev_data->port_id, i, pp);
1031 bits[pp / 32] |= 1 << (pp % 32);
1032 mlx5_txq_release(dev, i);
1035 for (i = 0; i < priv->rxqs_n; i++) {
1036 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i);
1037 struct mlx5_rxq_ctrl *rxq_ctrl;
1041 rxq_ctrl = rxq->ctrl;
1042 if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN)
1044 pp = rxq_ctrl->hairpin_conf.peers[0].port;
1045 if (pp >= RTE_MAX_ETHPORTS) {
1047 DRV_LOG(ERR, "port %hu queue %u peer port "
1049 priv->dev_data->port_id, i, pp);
1052 bits[pp / 32] |= 1 << (pp % 32);
1055 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
1056 if (bits[i / 32] & (1 << (i % 32))) {
1057 if ((size_t)ret >= len) {
1061 peer_ports[ret++] = i;
1068 * DPDK callback to start the device.
1070 * Simulate device start by attaching all configured flows.
1073 * Pointer to Ethernet device structure.
1076 * 0 on success, a negative errno value otherwise and rte_errno is set.
1079 mlx5_dev_start(struct rte_eth_dev *dev)
1081 struct mlx5_priv *priv = dev->data->dev_private;
1085 DRV_LOG(DEBUG, "port %u starting device", dev->data->port_id);
1086 fine_inline = rte_mbuf_dynflag_lookup
1087 (RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, NULL);
1088 if (fine_inline >= 0)
1089 rte_net_mlx5_dynf_inline_mask = 1UL << fine_inline;
1091 rte_net_mlx5_dynf_inline_mask = 0;
1092 if (dev->data->nb_rx_queues > 0) {
1093 ret = mlx5_dev_configure_rss_reta(dev);
1095 DRV_LOG(ERR, "port %u reta config failed: %s",
1096 dev->data->port_id, strerror(rte_errno));
1100 ret = mlx5_txpp_start(dev);
1102 DRV_LOG(ERR, "port %u Tx packet pacing init failed: %s",
1103 dev->data->port_id, strerror(rte_errno));
1106 if ((priv->sh->devx && priv->config.dv_flow_en &&
1107 priv->config.dest_tir) && priv->obj_ops.lb_dummy_queue_create) {
1108 ret = priv->obj_ops.lb_dummy_queue_create(dev);
1112 ret = mlx5_txq_start(dev);
1114 DRV_LOG(ERR, "port %u Tx queue allocation failed: %s",
1115 dev->data->port_id, strerror(rte_errno));
1118 ret = mlx5_rxq_start(dev);
1120 DRV_LOG(ERR, "port %u Rx queue allocation failed: %s",
1121 dev->data->port_id, strerror(rte_errno));
1125 * Such step will be skipped if there is no hairpin TX queue configured
1126 * with RX peer queue from the same device.
1128 ret = mlx5_hairpin_auto_bind(dev);
1130 DRV_LOG(ERR, "port %u hairpin auto binding failed: %s",
1131 dev->data->port_id, strerror(rte_errno));
1134 /* Set started flag here for the following steps like control flow. */
1135 dev->data->dev_started = 1;
1136 ret = mlx5_rx_intr_vec_enable(dev);
1138 DRV_LOG(ERR, "port %u Rx interrupt vector creation failed",
1139 dev->data->port_id);
1142 mlx5_os_stats_init(dev);
1143 ret = mlx5_traffic_enable(dev);
1145 DRV_LOG(ERR, "port %u failed to set defaults flows",
1146 dev->data->port_id);
1149 /* Set a mask and offset of dynamic metadata flows into Rx queues. */
1150 mlx5_flow_rxq_dynf_metadata_set(dev);
1151 /* Set flags and context to convert Rx timestamps. */
1152 mlx5_rxq_timestamp_set(dev);
1153 /* Set a mask and offset of scheduling on timestamp into Tx queues. */
1154 mlx5_txq_dynf_timestamp_set(dev);
1155 /* Attach indirection table objects detached on port stop. */
1156 ret = mlx5_action_handle_attach(dev);
1159 "port %u failed to attach indirect actions: %s",
1160 dev->data->port_id, rte_strerror(rte_errno));
1164 * In non-cached mode, it only needs to start the default mreg copy
1165 * action and no flow created by application exists anymore.
1166 * But it is worth wrapping the interface for further usage.
1168 ret = mlx5_flow_start_default(dev);
1170 DRV_LOG(DEBUG, "port %u failed to start default actions: %s",
1171 dev->data->port_id, strerror(rte_errno));
1174 if (mlx5_dev_ctx_shared_mempool_subscribe(dev) != 0) {
1175 DRV_LOG(ERR, "port %u failed to subscribe for mempool life cycle: %s",
1176 dev->data->port_id, rte_strerror(rte_errno));
1180 dev->tx_pkt_burst = mlx5_select_tx_function(dev);
1181 dev->rx_pkt_burst = mlx5_select_rx_function(dev);
1182 /* Enable datapath on secondary process. */
1183 mlx5_mp_os_req_start_rxtx(dev);
1184 if (rte_intr_fd_get(priv->sh->intr_handle) >= 0) {
1185 priv->sh->port[priv->dev_port - 1].ih_port_id =
1186 (uint32_t)dev->data->port_id;
1188 DRV_LOG(INFO, "port %u starts without LSC and RMV interrupts.",
1189 dev->data->port_id);
1190 dev->data->dev_conf.intr_conf.lsc = 0;
1191 dev->data->dev_conf.intr_conf.rmv = 0;
1193 if (rte_intr_fd_get(priv->sh->intr_handle_devx) >= 0)
1194 priv->sh->port[priv->dev_port - 1].devx_ih_port_id =
1195 (uint32_t)dev->data->port_id;
1198 ret = rte_errno; /* Save rte_errno before cleanup. */
1200 dev->data->dev_started = 0;
1201 mlx5_flow_stop_default(dev);
1202 mlx5_traffic_disable(dev);
1205 if (priv->obj_ops.lb_dummy_queue_release)
1206 priv->obj_ops.lb_dummy_queue_release(dev);
1207 mlx5_txpp_stop(dev); /* Stop last. */
1208 rte_errno = ret; /* Restore rte_errno. */
1213 * DPDK callback to stop the device.
1215 * Simulate device stop by detaching all configured flows.
1218 * Pointer to Ethernet device structure.
1221 mlx5_dev_stop(struct rte_eth_dev *dev)
1223 struct mlx5_priv *priv = dev->data->dev_private;
1225 dev->data->dev_started = 0;
1226 /* Prevent crashes when queues are still in use. */
1227 dev->rx_pkt_burst = removed_rx_burst;
1228 dev->tx_pkt_burst = removed_tx_burst;
1230 /* Disable datapath on secondary process. */
1231 mlx5_mp_os_req_stop_rxtx(dev);
1232 rte_delay_us_sleep(1000 * priv->rxqs_n);
1233 DRV_LOG(DEBUG, "port %u stopping device", dev->data->port_id);
1234 mlx5_flow_stop_default(dev);
1235 /* Control flows for default traffic can be removed firstly. */
1236 mlx5_traffic_disable(dev);
1237 /* All RX queue flags will be cleared in the flush interface. */
1238 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1239 mlx5_flow_meter_rxq_flush(dev);
1240 mlx5_action_handle_detach(dev);
1241 mlx5_rx_intr_vec_disable(dev);
1242 priv->sh->port[priv->dev_port - 1].ih_port_id = RTE_MAX_ETHPORTS;
1243 priv->sh->port[priv->dev_port - 1].devx_ih_port_id = RTE_MAX_ETHPORTS;
1246 if (priv->obj_ops.lb_dummy_queue_release)
1247 priv->obj_ops.lb_dummy_queue_release(dev);
1248 mlx5_txpp_stop(dev);
1254 * Enable traffic flows configured by control plane
1257 * Pointer to Ethernet device private data.
1259 * Pointer to Ethernet device structure.
1262 * 0 on success, a negative errno value otherwise and rte_errno is set.
1265 mlx5_traffic_enable(struct rte_eth_dev *dev)
1267 struct mlx5_priv *priv = dev->data->dev_private;
1268 struct rte_flow_item_eth bcast = {
1269 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1271 struct rte_flow_item_eth ipv6_multi_spec = {
1272 .dst.addr_bytes = "\x33\x33\x00\x00\x00\x00",
1274 struct rte_flow_item_eth ipv6_multi_mask = {
1275 .dst.addr_bytes = "\xff\xff\x00\x00\x00\x00",
1277 struct rte_flow_item_eth unicast = {
1278 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00",
1280 struct rte_flow_item_eth unicast_mask = {
1281 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1283 const unsigned int vlan_filter_n = priv->vlan_filter_n;
1284 const struct rte_ether_addr cmp = {
1285 .addr_bytes = "\x00\x00\x00\x00\x00\x00",
1292 * Hairpin txq default flow should be created no matter if it is
1293 * isolation mode. Or else all the packets to be sent will be sent
1294 * out directly without the TX flow actions, e.g. encapsulation.
1296 for (i = 0; i != priv->txqs_n; ++i) {
1297 struct mlx5_txq_ctrl *txq_ctrl = mlx5_txq_get(dev, i);
1300 /* Only Tx implicit mode requires the default Tx flow. */
1301 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN &&
1302 txq_ctrl->hairpin_conf.tx_explicit == 0 &&
1303 txq_ctrl->hairpin_conf.peers[0].port ==
1304 priv->dev_data->port_id) {
1305 ret = mlx5_ctrl_flow_source_queue(dev, i);
1307 mlx5_txq_release(dev, i);
1311 if ((priv->representor || priv->master) &&
1312 priv->config.dv_esw_en) {
1313 if (mlx5_flow_create_devx_sq_miss_flow(dev, i) == 0) {
1315 "Port %u Tx queue %u SQ create representor devx default miss rule failed.",
1316 dev->data->port_id, i);
1320 mlx5_txq_release(dev, i);
1322 if ((priv->master || priv->representor) && priv->config.dv_esw_en) {
1323 if (mlx5_flow_create_esw_table_zero_flow(dev))
1324 priv->fdb_def_rule = 1;
1326 DRV_LOG(INFO, "port %u FDB default rule cannot be"
1327 " configured - only Eswitch group 0 flows are"
1328 " supported.", dev->data->port_id);
1330 if (!priv->config.lacp_by_user && priv->pf_bond >= 0) {
1331 ret = mlx5_flow_lacp_miss(dev);
1333 DRV_LOG(INFO, "port %u LACP rule cannot be created - "
1334 "forward LACP to kernel.", dev->data->port_id);
1336 DRV_LOG(INFO, "LACP traffic will be missed in port %u."
1337 , dev->data->port_id);
1341 if (dev->data->promiscuous) {
1342 struct rte_flow_item_eth promisc = {
1343 .dst.addr_bytes = "\x00\x00\x00\x00\x00\x00",
1344 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00",
1348 ret = mlx5_ctrl_flow(dev, &promisc, &promisc);
1352 if (dev->data->all_multicast) {
1353 struct rte_flow_item_eth multicast = {
1354 .dst.addr_bytes = "\x01\x00\x00\x00\x00\x00",
1355 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00",
1359 ret = mlx5_ctrl_flow(dev, &multicast, &multicast);
1363 /* Add broadcast/multicast flows. */
1364 for (i = 0; i != vlan_filter_n; ++i) {
1365 uint16_t vlan = priv->vlan_filter[i];
1367 struct rte_flow_item_vlan vlan_spec = {
1368 .tci = rte_cpu_to_be_16(vlan),
1370 struct rte_flow_item_vlan vlan_mask =
1371 rte_flow_item_vlan_mask;
1373 ret = mlx5_ctrl_flow_vlan(dev, &bcast, &bcast,
1374 &vlan_spec, &vlan_mask);
1377 ret = mlx5_ctrl_flow_vlan(dev, &ipv6_multi_spec,
1379 &vlan_spec, &vlan_mask);
1383 if (!vlan_filter_n) {
1384 ret = mlx5_ctrl_flow(dev, &bcast, &bcast);
1387 ret = mlx5_ctrl_flow(dev, &ipv6_multi_spec,
1390 /* Do not fail on IPv6 broadcast creation failure. */
1392 "IPv6 broadcast is not supported");
1397 /* Add MAC address flows. */
1398 for (i = 0; i != MLX5_MAX_MAC_ADDRESSES; ++i) {
1399 struct rte_ether_addr *mac = &dev->data->mac_addrs[i];
1401 if (!memcmp(mac, &cmp, sizeof(*mac)))
1403 memcpy(&unicast.dst.addr_bytes,
1405 RTE_ETHER_ADDR_LEN);
1406 for (j = 0; j != vlan_filter_n; ++j) {
1407 uint16_t vlan = priv->vlan_filter[j];
1409 struct rte_flow_item_vlan vlan_spec = {
1410 .tci = rte_cpu_to_be_16(vlan),
1412 struct rte_flow_item_vlan vlan_mask =
1413 rte_flow_item_vlan_mask;
1415 ret = mlx5_ctrl_flow_vlan(dev, &unicast,
1422 if (!vlan_filter_n) {
1423 ret = mlx5_ctrl_flow(dev, &unicast, &unicast_mask);
1430 ret = rte_errno; /* Save rte_errno before cleanup. */
1431 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_CTL, false);
1432 rte_errno = ret; /* Restore rte_errno. */
1438 * Disable traffic flows configured by control plane
1441 * Pointer to Ethernet device private data.
1444 mlx5_traffic_disable(struct rte_eth_dev *dev)
1446 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_CTL, false);
1450 * Restart traffic flows configured by control plane
1453 * Pointer to Ethernet device private data.
1456 * 0 on success, a negative errno value otherwise and rte_errno is set.
1459 mlx5_traffic_restart(struct rte_eth_dev *dev)
1461 if (dev->data->dev_started) {
1462 mlx5_traffic_disable(dev);
1463 return mlx5_traffic_enable(dev);