1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2021 6WIND S.A.
3 * Copyright 2021 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_TX_H_
7 #define RTE_PMD_MLX5_TX_H_
10 #include <sys/queue.h>
13 #include <rte_mempool.h>
14 #include <rte_common.h>
15 #include <rte_spinlock.h>
17 #include <mlx5_common_mr.h>
20 #include "mlx5_autoconf.h"
23 /* TX burst subroutines return codes. */
24 enum mlx5_txcmp_code {
25 MLX5_TXCMP_CODE_EXIT = 0,
26 MLX5_TXCMP_CODE_ERROR,
27 MLX5_TXCMP_CODE_SINGLE,
28 MLX5_TXCMP_CODE_MULTI,
34 * These defines are used to configure Tx burst routine option set supported
35 * at compile time. The not specified options are optimized out due to if
36 * conditions can be explicitly calculated at compile time.
37 * The offloads with bigger runtime check (require more CPU cycles toskip)
38 * overhead should have the bigger index - this is needed to select the better
39 * matching routine function if no exact match and some offloads are not
42 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
43 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
44 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
45 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
46 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
47 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
48 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
49 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
50 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
51 #define MLX5_TXOFF_CONFIG_TXPP (1u << 10) /* Scheduling on timestamp.*/
53 /* The most common offloads groups. */
54 #define MLX5_TXOFF_CONFIG_NONE 0
55 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
56 MLX5_TXOFF_CONFIG_TSO | \
57 MLX5_TXOFF_CONFIG_SWP | \
58 MLX5_TXOFF_CONFIG_CSUM | \
59 MLX5_TXOFF_CONFIG_INLINE | \
60 MLX5_TXOFF_CONFIG_VLAN | \
61 MLX5_TXOFF_CONFIG_METADATA)
63 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
65 #define MLX5_TXOFF_PRE_DECL(func) \
66 uint16_t mlx5_tx_burst_##func(void *txq, \
67 struct rte_mbuf **pkts, \
70 #define MLX5_TXOFF_DECL(func, olx) \
71 uint16_t mlx5_tx_burst_##func(void *txq, \
72 struct rte_mbuf **pkts, \
75 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
76 pkts, pkts_n, (olx)); \
79 /* Mbuf dynamic flag offset for inline. */
80 extern uint64_t rte_net_mlx5_dynf_inline_mask;
81 #define PKT_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask
83 extern uint32_t mlx5_ptype_table[] __rte_cache_aligned;
84 extern uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
85 extern uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
87 struct mlx5_txq_stats {
88 #ifdef MLX5_PMD_SOFT_COUNTERS
89 uint64_t opackets; /**< Total of successfully sent packets. */
90 uint64_t obytes; /**< Total of successfully sent bytes. */
92 uint64_t oerrors; /**< Total number of failed transmitted packets. */
95 /* TX queue send local data. */
97 struct mlx5_txq_local {
98 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
99 struct rte_mbuf *mbuf; /* first mbuf to process. */
100 uint16_t pkts_copy; /* packets copied to elts. */
101 uint16_t pkts_sent; /* packets sent. */
102 uint16_t pkts_loop; /* packets sent on loop entry. */
103 uint16_t elts_free; /* available elts remain. */
104 uint16_t wqe_free; /* available wqe remain. */
105 uint16_t mbuf_off; /* data offset in current mbuf. */
106 uint16_t mbuf_nseg; /* number of remaining mbuf. */
107 uint16_t mbuf_free; /* number of inline mbufs to free. */
110 /* TX queue descriptor. */
112 struct mlx5_txq_data {
113 uint16_t elts_head; /* Current counter in (*elts)[]. */
114 uint16_t elts_tail; /* Counter of first element awaiting completion. */
115 uint16_t elts_comp; /* elts index since last completion request. */
116 uint16_t elts_s; /* Number of mbuf elements. */
117 uint16_t elts_m; /* Mask for mbuf elements indices. */
118 /* Fields related to elts mbuf storage. */
119 uint16_t wqe_ci; /* Consumer index for work queue. */
120 uint16_t wqe_pi; /* Producer index for work queue. */
121 uint16_t wqe_s; /* Number of WQ elements. */
122 uint16_t wqe_m; /* Mask Number for WQ elements. */
123 uint16_t wqe_comp; /* WQE index since last completion request. */
124 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
125 /* WQ related fields. */
126 uint16_t cq_ci; /* Consumer index for completion queue. */
127 uint16_t cq_pi; /* Production index for completion queue. */
128 uint16_t cqe_s; /* Number of CQ elements. */
129 uint16_t cqe_m; /* Mask for CQ indices. */
130 /* CQ related fields. */
131 uint16_t elts_n:4; /* elts[] length (in log2). */
132 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
133 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
134 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
135 uint16_t tunnel_en:1;
136 /* When set TX offload for tunneled packets are supported. */
137 uint16_t swp_en:1; /* Whether SW parser is enabled. */
138 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
139 uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */
140 uint16_t db_heu:1; /* Doorbell heuristic write barrier. */
141 uint16_t fast_free:1; /* mbuf fast free on Tx is enabled. */
142 uint16_t inlen_send; /* Ordinary send data inline size. */
143 uint16_t inlen_empw; /* eMPW max packet size to inline. */
144 uint16_t inlen_mode; /* Minimal data length to inline. */
145 uint32_t qp_num_8s; /* QP number shifted by 8. */
146 uint64_t offloads; /* Offloads for Tx Queue. */
147 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
148 struct mlx5_wqe *wqes; /* Work queue. */
149 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
150 #ifdef RTE_LIBRTE_MLX5_DEBUG
151 uint32_t *fcqs; /* Free completion queue (debug extended). */
153 uint16_t *fcqs; /* Free completion queue. */
155 volatile struct mlx5_cqe *cqes; /* Completion queue. */
156 volatile uint32_t *qp_db; /* Work queue doorbell. */
157 volatile uint32_t *cq_db; /* Completion queue doorbell. */
158 uint16_t port_id; /* Port ID of device. */
159 uint16_t idx; /* Queue index. */
160 uint64_t ts_mask; /* Timestamp flag dynamic mask. */
161 int32_t ts_offset; /* Timestamp field dynamic offset. */
162 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
163 struct mlx5_txq_stats stats; /* TX queue counters. */
165 rte_spinlock_t *uar_lock;
166 /* UAR access lock required for 32bit implementations */
168 struct rte_mbuf *elts[0];
169 /* Storage for queued packets, must be the last field. */
170 } __rte_cache_aligned;
173 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
174 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Tx queue. */
177 /* TX queue control descriptor. */
178 struct mlx5_txq_ctrl {
179 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
180 uint32_t refcnt; /* Reference counter. */
181 unsigned int socket; /* CPU socket ID for allocations. */
182 enum mlx5_txq_type type; /* The txq ctrl type. */
183 unsigned int max_inline_data; /* Max inline data. */
184 unsigned int max_tso_header; /* Max TSO header size. */
185 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */
186 struct mlx5_priv *priv; /* Back pointer to private data. */
187 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
188 void *bf_reg; /* BlueFlame register from Verbs. */
189 uint16_t dump_file_n; /* Number of dump files. */
190 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
191 uint32_t hairpin_status; /* Hairpin binding status. */
192 struct mlx5_txq_data txq; /* Data path structure. */
193 /* Must be the last field in the structure, contains elts[]. */
198 int mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id);
199 int mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id);
200 int mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id);
201 int mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id);
202 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
203 unsigned int socket, const struct rte_eth_txconf *conf);
204 int mlx5_tx_hairpin_queue_setup
205 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
206 const struct rte_eth_hairpin_conf *hairpin_conf);
207 void mlx5_tx_queue_release(void *dpdk_txq);
208 void txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl);
209 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
210 void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev);
211 int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
212 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
213 uint16_t desc, unsigned int socket,
214 const struct rte_eth_txconf *conf);
215 struct mlx5_txq_ctrl *mlx5_txq_hairpin_new
216 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
217 const struct rte_eth_hairpin_conf *hairpin_conf);
218 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
219 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
220 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
221 int mlx5_txq_verify(struct rte_eth_dev *dev);
222 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
223 void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);
224 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
225 void mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev);
229 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
231 void mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq,
232 unsigned int olx __rte_unused);
233 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
234 void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
235 struct rte_eth_txq_info *qinfo);
236 int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
237 struct rte_eth_burst_mode *mode);
241 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
242 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
243 struct rte_mempool *mp);
247 MLX5_TXOFF_PRE_DECL(full_empw);
248 MLX5_TXOFF_PRE_DECL(none_empw);
249 MLX5_TXOFF_PRE_DECL(md_empw);
250 MLX5_TXOFF_PRE_DECL(mt_empw);
251 MLX5_TXOFF_PRE_DECL(mtsc_empw);
252 MLX5_TXOFF_PRE_DECL(mti_empw);
253 MLX5_TXOFF_PRE_DECL(mtv_empw);
254 MLX5_TXOFF_PRE_DECL(mtiv_empw);
255 MLX5_TXOFF_PRE_DECL(sc_empw);
256 MLX5_TXOFF_PRE_DECL(sci_empw);
257 MLX5_TXOFF_PRE_DECL(scv_empw);
258 MLX5_TXOFF_PRE_DECL(sciv_empw);
259 MLX5_TXOFF_PRE_DECL(i_empw);
260 MLX5_TXOFF_PRE_DECL(v_empw);
261 MLX5_TXOFF_PRE_DECL(iv_empw);
263 /* mlx5_tx_nompw.c */
265 MLX5_TXOFF_PRE_DECL(full);
266 MLX5_TXOFF_PRE_DECL(none);
267 MLX5_TXOFF_PRE_DECL(md);
268 MLX5_TXOFF_PRE_DECL(mt);
269 MLX5_TXOFF_PRE_DECL(mtsc);
270 MLX5_TXOFF_PRE_DECL(mti);
271 MLX5_TXOFF_PRE_DECL(mtv);
272 MLX5_TXOFF_PRE_DECL(mtiv);
273 MLX5_TXOFF_PRE_DECL(sc);
274 MLX5_TXOFF_PRE_DECL(sci);
275 MLX5_TXOFF_PRE_DECL(scv);
276 MLX5_TXOFF_PRE_DECL(sciv);
277 MLX5_TXOFF_PRE_DECL(i);
278 MLX5_TXOFF_PRE_DECL(v);
279 MLX5_TXOFF_PRE_DECL(iv);
283 MLX5_TXOFF_PRE_DECL(full_ts_nompw);
284 MLX5_TXOFF_PRE_DECL(full_ts_nompwi);
285 MLX5_TXOFF_PRE_DECL(full_ts);
286 MLX5_TXOFF_PRE_DECL(full_ts_noi);
287 MLX5_TXOFF_PRE_DECL(none_ts);
288 MLX5_TXOFF_PRE_DECL(mdi_ts);
289 MLX5_TXOFF_PRE_DECL(mti_ts);
290 MLX5_TXOFF_PRE_DECL(mtiv_ts);
294 MLX5_TXOFF_PRE_DECL(none_mpw);
295 MLX5_TXOFF_PRE_DECL(mci_mpw);
296 MLX5_TXOFF_PRE_DECL(mc_mpw);
297 MLX5_TXOFF_PRE_DECL(i_mpw);
299 static __rte_always_inline uint64_t *
300 mlx5_tx_bfreg(struct mlx5_txq_data *txq)
302 return MLX5_PROC_PRIV(txq->port_id)->uar_table[txq->idx];
306 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
307 * 64bit architectures.
310 * value to write in CPU endian format.
312 * Address to write to.
314 * Address of the lock to use for that UAR access.
316 static __rte_always_inline void
317 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
318 rte_spinlock_t *lock __rte_unused)
321 *(uint64_t *)addr = val;
322 #else /* !RTE_ARCH_64 */
323 rte_spinlock_lock(lock);
324 *(uint32_t *)addr = val;
326 *((uint32_t *)addr + 1) = val >> 32;
327 rte_spinlock_unlock(lock);
332 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
333 * 64bit architectures while guaranteeing the order of execution with the
334 * code being executed.
337 * value to write in CPU endian format.
339 * Address to write to.
341 * Address of the lock to use for that UAR access.
343 static __rte_always_inline void
344 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
347 __mlx5_uar_write64_relaxed(val, addr, lock);
350 /* Assist macros, used instead of directly calling the functions they wrap. */
352 #define mlx5_uar_write64_relaxed(val, dst, lock) \
353 __mlx5_uar_write64_relaxed(val, dst, NULL)
354 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
356 #define mlx5_uar_write64_relaxed(val, dst, lock) \
357 __mlx5_uar_write64_relaxed(val, dst, lock)
358 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
362 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
365 * Pointer to Tx queue structure.
370 * Searched LKey on success, UINT32_MAX on no match.
372 static __rte_always_inline uint32_t
373 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
375 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
376 uintptr_t addr = (uintptr_t)mb->buf_addr;
379 /* Check generation bit to see if there's any change on existing MRs. */
380 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
381 mlx5_mr_flush_local_cache(mr_ctrl);
382 /* Linear search on MR cache array. */
383 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
384 MLX5_MR_CACHE_N, addr);
385 if (likely(lkey != UINT32_MAX))
387 /* Take slower bottom-half on miss. */
388 return mlx5_tx_mb2mr_bh(txq, mb);
392 * Ring TX queue doorbell and flush the update if requested.
395 * Pointer to TX queue structure.
397 * Pointer to the last WQE posted in the NIC.
399 * Request for write memory barrier after BlueFlame update.
401 static __rte_always_inline void
402 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
405 uint64_t *dst = mlx5_tx_bfreg(txq);
406 volatile uint64_t *src = ((volatile uint64_t *)wqe);
409 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
410 /* Ensure ordering between DB record and BF copy. */
412 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
418 * Ring TX queue doorbell and flush the update by write memory barrier.
421 * Pointer to TX queue structure.
423 * Pointer to the last WQE posted in the NIC.
425 static __rte_always_inline void
426 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
428 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
432 * Convert timestamp from mbuf format to linear counter
433 * of Clock Queue completions (24 bits).
436 * Pointer to the device shared context to fetch Tx
437 * packet pacing timestamp and parameters.
439 * Timestamp from mbuf to convert.
441 * positive or zero value - completion ID to wait.
442 * negative value - conversion error.
444 static __rte_always_inline int32_t
445 mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts)
452 * Read atomically two uint64_t fields and compare lsb bits.
453 * It there is no match - the timestamp was updated in
454 * the service thread, data should be re-read.
456 rte_compiler_barrier();
457 ci = __atomic_load_n(&sh->txpp.ts.ci_ts, __ATOMIC_RELAXED);
458 ts = __atomic_load_n(&sh->txpp.ts.ts, __ATOMIC_RELAXED);
459 rte_compiler_barrier();
460 if (!((ts ^ ci) << (64 - MLX5_CQ_INDEX_WIDTH)))
463 /* Perform the skew correction, positive value to send earlier. */
464 mts -= sh->txpp.skew;
466 if (unlikely(mts >= UINT64_MAX / 2)) {
467 /* We have negative integer, mts is in the past. */
468 __atomic_fetch_add(&sh->txpp.err_ts_past,
469 1, __ATOMIC_RELAXED);
472 tick = sh->txpp.tick;
474 /* Convert delta to completions, round up. */
475 mts = (mts + tick - 1) / tick;
476 if (unlikely(mts >= (1 << MLX5_CQ_INDEX_WIDTH) / 2 - 1)) {
477 /* We have mts is too distant future. */
478 __atomic_fetch_add(&sh->txpp.err_ts_future,
479 1, __ATOMIC_RELAXED);
482 mts <<= 64 - MLX5_CQ_INDEX_WIDTH;
484 ci >>= 64 - MLX5_CQ_INDEX_WIDTH;
489 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
490 * Flags must be preliminary initialized to zero.
493 * Pointer to burst routine local context.
495 * Pointer to store Software Parser flags.
497 * Configured Tx offloads mask. It is fully defined at
498 * compile time and may be used for optimization.
501 * Software Parser offsets packed in dword.
502 * Software Parser flags are set by pointer.
504 static __rte_always_inline uint32_t
505 txq_mbuf_to_swp(struct mlx5_txq_local *__rte_restrict loc,
510 unsigned int idx, off;
513 if (!MLX5_TXOFF_CONFIG(SWP))
515 ol = loc->mbuf->ol_flags;
516 tunnel = ol & PKT_TX_TUNNEL_MASK;
518 * Check whether Software Parser is required.
519 * Only customized tunnels may ask for.
521 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
524 * The index should have:
525 * bit[0:1] = PKT_TX_L4_MASK
526 * bit[4] = PKT_TX_IPV6
527 * bit[8] = PKT_TX_OUTER_IPV6
528 * bit[9] = PKT_TX_OUTER_UDP
530 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
531 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
532 *swp_flags = mlx5_swp_types_table[idx];
534 * Set offsets for SW parser. Since ConnectX-5, SW parser just
535 * complements HW parser. SW parser starts to engage only if HW parser
536 * can't reach a header. For the older devices, HW parser will not kick
537 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
538 * should be set regardless of HW offload.
540 off = loc->mbuf->outer_l2_len;
541 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
542 off += sizeof(struct rte_vlan_hdr);
543 set = (off >> 1) << 8; /* Outer L3 offset. */
544 off += loc->mbuf->outer_l3_len;
545 if (tunnel == PKT_TX_TUNNEL_UDP)
546 set |= off >> 1; /* Outer L4 offset. */
547 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
548 const uint64_t csum = ol & PKT_TX_L4_MASK;
549 off += loc->mbuf->l2_len;
550 set |= (off >> 1) << 24; /* Inner L3 offset. */
551 if (csum == PKT_TX_TCP_CKSUM ||
552 csum == PKT_TX_UDP_CKSUM ||
553 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
554 off += loc->mbuf->l3_len;
555 set |= (off >> 1) << 16; /* Inner L4 offset. */
558 set = rte_cpu_to_le_32(set);
563 * Convert the Checksum offloads to Verbs.
566 * Pointer to the mbuf.
569 * Converted checksum flags.
571 static __rte_always_inline uint8_t
572 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
575 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
576 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
577 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
580 * The index should have:
581 * bit[0] = PKT_TX_TCP_SEG
582 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
583 * bit[4] = PKT_TX_IP_CKSUM
584 * bit[8] = PKT_TX_OUTER_IP_CKSUM
587 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
588 return mlx5_cksum_table[idx];
592 * Free the mbufs from the linear array of pointers.
595 * Pointer to Tx queue structure.
597 * Pointer to array of packets to be free.
599 * Number of packets to be freed.
601 * Configured Tx offloads mask. It is fully defined at
602 * compile time and may be used for optimization.
604 static __rte_always_inline void
605 mlx5_tx_free_mbuf(struct mlx5_txq_data *__rte_restrict txq,
606 struct rte_mbuf **__rte_restrict pkts,
608 unsigned int olx __rte_unused)
610 struct rte_mempool *pool = NULL;
611 struct rte_mbuf **p_free = NULL;
612 struct rte_mbuf *mbuf;
613 unsigned int n_free = 0;
616 * The implemented algorithm eliminates
617 * copying pointers to temporary array
618 * for rte_mempool_put_bulk() calls.
623 * Free mbufs directly to the pool in bulk
624 * if fast free offload is engaged
626 if (!MLX5_TXOFF_CONFIG(MULTI) && txq->fast_free) {
629 rte_mempool_put_bulk(pool, (void *)pkts, pkts_n);
635 * Decrement mbuf reference counter, detach
636 * indirect and external buffers if needed.
638 mbuf = rte_pktmbuf_prefree_seg(*pkts);
639 if (likely(mbuf != NULL)) {
640 MLX5_ASSERT(mbuf == *pkts);
641 if (likely(n_free != 0)) {
642 if (unlikely(pool != mbuf->pool))
643 /* From different pool. */
646 /* Start new scan array. */
653 if (unlikely(pkts_n == 0)) {
659 * This happens if mbuf is still referenced.
660 * We can't put it back to the pool, skip.
664 if (unlikely(n_free != 0))
665 /* There is some array to free.*/
667 if (unlikely(pkts_n == 0))
668 /* Last mbuf, nothing to free. */
674 * This loop is implemented to avoid multiple
675 * inlining of rte_mempool_put_bulk().
681 * Free the array of pre-freed mbufs
682 * belonging to the same memory pool.
684 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
685 if (unlikely(mbuf != NULL)) {
686 /* There is the request to start new scan. */
691 if (likely(pkts_n != 0))
694 * This is the last mbuf to be freed.
695 * Do one more loop iteration to complete.
696 * This is rare case of the last unique mbuf.
701 if (likely(pkts_n == 0))
710 * No inline version to free buffers for optimal call
711 * on the tx_burst completion.
713 static __rte_noinline void
714 __mlx5_tx_free_mbuf(struct mlx5_txq_data *__rte_restrict txq,
715 struct rte_mbuf **__rte_restrict pkts,
717 unsigned int olx __rte_unused)
719 mlx5_tx_free_mbuf(txq, pkts, pkts_n, olx);
723 * Free the mbuf from the elts ring buffer till new tail.
726 * Pointer to Tx queue structure.
728 * Index in elts to free up to, becomes new elts tail.
730 * Configured Tx offloads mask. It is fully defined at
731 * compile time and may be used for optimization.
733 static __rte_always_inline void
734 mlx5_tx_free_elts(struct mlx5_txq_data *__rte_restrict txq,
736 unsigned int olx __rte_unused)
738 uint16_t n_elts = tail - txq->elts_tail;
741 MLX5_ASSERT(n_elts <= txq->elts_s);
743 * Implement a loop to support ring buffer wraparound
744 * with single inlining of mlx5_tx_free_mbuf().
749 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
750 part = RTE_MIN(part, n_elts);
752 MLX5_ASSERT(part <= txq->elts_s);
753 mlx5_tx_free_mbuf(txq,
754 &txq->elts[txq->elts_tail & txq->elts_m],
756 txq->elts_tail += part;
762 * Store the mbuf being sent into elts ring buffer.
763 * On Tx completion these mbufs will be freed.
766 * Pointer to Tx queue structure.
768 * Pointer to array of packets to be stored.
770 * Number of packets to be stored.
772 * Configured Tx offloads mask. It is fully defined at
773 * compile time and may be used for optimization.
775 static __rte_always_inline void
776 mlx5_tx_copy_elts(struct mlx5_txq_data *__rte_restrict txq,
777 struct rte_mbuf **__rte_restrict pkts,
779 unsigned int olx __rte_unused)
782 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
786 part = txq->elts_s - (txq->elts_head & txq->elts_m);
788 MLX5_ASSERT(part <= txq->elts_s);
789 /* This code is a good candidate for vectorizing with SIMD. */
790 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
792 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
793 txq->elts_head += pkts_n;
794 if (unlikely(part < pkts_n))
795 /* The copy is wrapping around the elts array. */
796 rte_memcpy((void *)elts, (void *)(pkts + part),
797 (pkts_n - part) * sizeof(struct rte_mbuf *));
801 * Check if the completion request flag should be set in the last WQE.
802 * Both pushed mbufs and WQEs are monitored and the completion request
803 * flag is set if any of thresholds is reached.
806 * Pointer to TX queue structure.
808 * Pointer to burst routine local context.
810 * Configured Tx offloads mask. It is fully defined at
811 * compile time and may be used for optimization.
813 static __rte_always_inline void
814 mlx5_tx_request_completion(struct mlx5_txq_data *__rte_restrict txq,
815 struct mlx5_txq_local *__rte_restrict loc,
818 uint16_t head = txq->elts_head;
821 part = MLX5_TXOFF_CONFIG(INLINE) ?
822 0 : loc->pkts_sent - loc->pkts_copy;
824 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
825 (MLX5_TXOFF_CONFIG(INLINE) &&
826 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
827 volatile struct mlx5_wqe *last = loc->wqe_last;
830 txq->elts_comp = head;
831 if (MLX5_TXOFF_CONFIG(INLINE))
832 txq->wqe_comp = txq->wqe_ci;
833 /* Request unconditional completion on last WQE. */
834 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
835 MLX5_COMP_MODE_OFFSET);
836 /* Save elts_head in dedicated free on completion queue. */
837 #ifdef RTE_LIBRTE_MLX5_DEBUG
838 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |
839 (last->cseg.opcode >> 8) << 16;
841 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;
843 /* A CQE slot must always be available. */
844 MLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);
849 * Build the Control Segment with specified opcode:
851 * - MLX5_OPCODE_ENHANCED_MPSW
855 * Pointer to TX queue structure.
857 * Pointer to burst routine local context.
859 * Pointer to WQE to fill with built Control Segment.
861 * Supposed length of WQE in segments.
863 * SQ WQE opcode to put into Control Segment.
865 * Configured Tx offloads mask. It is fully defined at
866 * compile time and may be used for optimization.
868 static __rte_always_inline void
869 mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,
870 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
871 struct mlx5_wqe *__rte_restrict wqe,
874 unsigned int olx __rte_unused)
876 struct mlx5_wqe_cseg *__rte_restrict cs = &wqe->cseg;
878 /* For legacy MPW replace the EMPW by TSO with modifier. */
879 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
880 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
881 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
882 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
883 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
884 MLX5_COMP_MODE_OFFSET);
885 cs->misc = RTE_BE32(0);
889 * Build the Synchronize Queue Segment with specified completion index.
892 * Pointer to TX queue structure.
894 * Pointer to burst routine local context.
896 * Pointer to WQE to fill with built Control Segment.
898 * Completion index in Clock Queue to wait.
900 * Configured Tx offloads mask. It is fully defined at
901 * compile time and may be used for optimization.
903 static __rte_always_inline void
904 mlx5_tx_wseg_init(struct mlx5_txq_data *restrict txq,
905 struct mlx5_txq_local *restrict loc __rte_unused,
906 struct mlx5_wqe *restrict wqe,
908 unsigned int olx __rte_unused)
910 struct mlx5_wqe_qseg *qs;
912 qs = RTE_PTR_ADD(wqe, MLX5_WSEG_SIZE);
913 qs->max_index = rte_cpu_to_be_32(wci);
914 qs->qpn_cqn = rte_cpu_to_be_32(txq->sh->txpp.clock_queue.cq_obj.cq->id);
915 qs->reserved0 = RTE_BE32(0);
916 qs->reserved1 = RTE_BE32(0);
920 * Build the Ethernet Segment without inlined data.
921 * Supports Software Parser, Checksums and VLAN insertion Tx offload features.
924 * Pointer to TX queue structure.
926 * Pointer to burst routine local context.
928 * Pointer to WQE to fill with built Ethernet Segment.
930 * Configured Tx offloads mask. It is fully defined at
931 * compile time and may be used for optimization.
933 static __rte_always_inline void
934 mlx5_tx_eseg_none(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
935 struct mlx5_txq_local *__rte_restrict loc,
936 struct mlx5_wqe *__rte_restrict wqe,
939 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
943 * Calculate and set check sum flags first, dword field
944 * in segment may be shared with Software Parser flags.
946 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
947 es->flags = rte_cpu_to_le_32(csum);
949 * Calculate and set Software Parser offsets and flags.
950 * These flags a set for custom UDP and IP tunnel packets.
952 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
953 /* Fill metadata field if needed. */
954 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
955 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
956 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
957 /* Engage VLAN tag insertion feature if requested. */
958 if (MLX5_TXOFF_CONFIG(VLAN) &&
959 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
961 * We should get here only if device support
962 * this feature correctly.
964 MLX5_ASSERT(txq->vlan_en);
965 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
966 loc->mbuf->vlan_tci);
968 es->inline_hdr = RTE_BE32(0);
973 * Build the Ethernet Segment with minimal inlined data
974 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
975 * used to fill the gap in single WQEBB WQEs.
976 * Supports Software Parser, Checksums and VLAN
977 * insertion Tx offload features.
980 * Pointer to TX queue structure.
982 * Pointer to burst routine local context.
984 * Pointer to WQE to fill with built Ethernet Segment.
986 * Length of VLAN tag insertion if any.
988 * Configured Tx offloads mask. It is fully defined at
989 * compile time and may be used for optimization.
991 static __rte_always_inline void
992 mlx5_tx_eseg_dmin(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
993 struct mlx5_txq_local *__rte_restrict loc,
994 struct mlx5_wqe *__rte_restrict wqe,
998 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
1000 uint8_t *psrc, *pdst;
1003 * Calculate and set check sum flags first, dword field
1004 * in segment may be shared with Software Parser flags.
1006 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
1007 es->flags = rte_cpu_to_le_32(csum);
1009 * Calculate and set Software Parser offsets and flags.
1010 * These flags a set for custom UDP and IP tunnel packets.
1012 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
1013 /* Fill metadata field if needed. */
1014 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
1015 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
1016 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
1017 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
1018 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
1019 es->inline_data = *(unaligned_uint16_t *)psrc;
1020 psrc += sizeof(uint16_t);
1021 pdst = (uint8_t *)(es + 1);
1022 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
1023 /* Implement VLAN tag insertion as part inline data. */
1024 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
1025 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
1026 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
1027 /* Insert VLAN ethertype + VLAN tag. */
1028 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
1029 ((RTE_ETHER_TYPE_VLAN << 16) |
1030 loc->mbuf->vlan_tci);
1031 pdst += sizeof(struct rte_vlan_hdr);
1032 /* Copy the rest two bytes from packet data. */
1033 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
1034 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
1036 /* Fill the gap in the title WQEBB with inline data. */
1037 rte_mov16(pdst, psrc);
1042 * Build the Ethernet Segment with entire packet data inlining. Checks the
1043 * boundary of WQEBB and ring buffer wrapping, supports Software Parser,
1044 * Checksums and VLAN insertion Tx offload features.
1047 * Pointer to TX queue structure.
1049 * Pointer to burst routine local context.
1051 * Pointer to WQE to fill with built Ethernet Segment.
1053 * Length of VLAN tag insertion if any.
1055 * Length of data to inline (VLAN included, if any).
1057 * TSO flag, set mss field from the packet.
1059 * Configured Tx offloads mask. It is fully defined at
1060 * compile time and may be used for optimization.
1063 * Pointer to the next Data Segment (aligned and wrapped around).
1065 static __rte_always_inline struct mlx5_wqe_dseg *
1066 mlx5_tx_eseg_data(struct mlx5_txq_data *__rte_restrict txq,
1067 struct mlx5_txq_local *__rte_restrict loc,
1068 struct mlx5_wqe *__rte_restrict wqe,
1074 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
1076 uint8_t *psrc, *pdst;
1080 * Calculate and set check sum flags first, dword field
1081 * in segment may be shared with Software Parser flags.
1083 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
1086 csum |= loc->mbuf->tso_segsz;
1087 es->flags = rte_cpu_to_be_32(csum);
1089 es->flags = rte_cpu_to_le_32(csum);
1092 * Calculate and set Software Parser offsets and flags.
1093 * These flags a set for custom UDP and IP tunnel packets.
1095 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
1096 /* Fill metadata field if needed. */
1097 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
1098 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
1099 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
1100 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
1101 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
1102 es->inline_data = *(unaligned_uint16_t *)psrc;
1103 psrc += sizeof(uint16_t);
1104 pdst = (uint8_t *)(es + 1);
1105 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
1106 /* Implement VLAN tag insertion as part inline data. */
1107 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
1108 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
1109 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
1110 /* Insert VLAN ethertype + VLAN tag. */
1111 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
1112 ((RTE_ETHER_TYPE_VLAN << 16) |
1113 loc->mbuf->vlan_tci);
1114 pdst += sizeof(struct rte_vlan_hdr);
1115 /* Copy the rest two bytes from packet data. */
1116 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
1117 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
1118 psrc += sizeof(uint16_t);
1120 /* Fill the gap in the title WQEBB with inline data. */
1121 rte_mov16(pdst, psrc);
1122 psrc += sizeof(rte_v128u32_t);
1124 pdst = (uint8_t *)(es + 2);
1125 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
1126 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
1127 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
1129 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
1130 return (struct mlx5_wqe_dseg *)pdst;
1133 * The WQEBB space availability is checked by caller.
1134 * Here we should be aware of WQE ring buffer wraparound only.
1136 part = (uint8_t *)txq->wqes_end - pdst;
1137 part = RTE_MIN(part, inlen);
1139 rte_memcpy(pdst, psrc, part);
1141 if (likely(!inlen)) {
1143 * If return value is not used by the caller
1144 * the code below will be optimized out.
1147 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
1148 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
1149 pdst = (uint8_t *)txq->wqes;
1150 return (struct mlx5_wqe_dseg *)pdst;
1152 pdst = (uint8_t *)txq->wqes;
1159 * Copy data from chain of mbuf to the specified linear buffer.
1160 * Checksums and VLAN insertion Tx offload features. If data
1161 * from some mbuf copied completely this mbuf is freed. Local
1162 * structure is used to keep the byte stream state.
1165 * Pointer to the destination linear buffer.
1167 * Pointer to burst routine local context.
1169 * Length of data to be copied.
1171 * Length of data to be copied ignoring no inline hint.
1173 * Configured Tx offloads mask. It is fully defined at
1174 * compile time and may be used for optimization.
1177 * Number of actual copied data bytes. This is always greater than or
1178 * equal to must parameter and might be lesser than len in no inline
1179 * hint flag is encountered.
1181 static __rte_always_inline unsigned int
1182 mlx5_tx_mseg_memcpy(uint8_t *pdst,
1183 struct mlx5_txq_local *__rte_restrict loc,
1186 unsigned int olx __rte_unused)
1188 struct rte_mbuf *mbuf;
1189 unsigned int part, dlen, copy = 0;
1193 MLX5_ASSERT(must <= len);
1195 /* Allow zero length packets, must check first. */
1196 dlen = rte_pktmbuf_data_len(loc->mbuf);
1197 if (dlen <= loc->mbuf_off) {
1198 /* Exhausted packet, just free. */
1200 loc->mbuf = mbuf->next;
1201 rte_pktmbuf_free_seg(mbuf);
1203 MLX5_ASSERT(loc->mbuf_nseg > 1);
1204 MLX5_ASSERT(loc->mbuf);
1206 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
1211 * We already copied the minimal
1212 * requested amount of data.
1217 if (diff <= rte_pktmbuf_data_len(loc->mbuf)) {
1219 * Copy only the minimal required
1220 * part of the data buffer.
1227 dlen -= loc->mbuf_off;
1228 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
1230 part = RTE_MIN(len, dlen);
1231 rte_memcpy(pdst, psrc, part);
1233 loc->mbuf_off += part;
1236 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
1238 /* Exhausted packet, just free. */
1240 loc->mbuf = mbuf->next;
1241 rte_pktmbuf_free_seg(mbuf);
1243 MLX5_ASSERT(loc->mbuf_nseg >= 1);
1253 * Build the Ethernet Segment with inlined data from multi-segment packet.
1254 * Checks the boundary of WQEBB and ring buffer wrapping, supports Software
1255 * Parser, Checksums and VLAN insertion Tx offload features.
1258 * Pointer to TX queue structure.
1260 * Pointer to burst routine local context.
1262 * Pointer to WQE to fill with built Ethernet Segment.
1264 * Length of VLAN tag insertion if any.
1266 * Length of data to inline (VLAN included, if any).
1268 * TSO flag, set mss field from the packet.
1270 * Configured Tx offloads mask. It is fully defined at
1271 * compile time and may be used for optimization.
1274 * Pointer to the next Data Segment (aligned and possible NOT wrapped
1275 * around - caller should do wrapping check on its own).
1277 static __rte_always_inline struct mlx5_wqe_dseg *
1278 mlx5_tx_eseg_mdat(struct mlx5_txq_data *__rte_restrict txq,
1279 struct mlx5_txq_local *__rte_restrict loc,
1280 struct mlx5_wqe *__rte_restrict wqe,
1286 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
1289 unsigned int part, tlen = 0;
1292 * Calculate and set check sum flags first, uint32_t field
1293 * in segment may be shared with Software Parser flags.
1295 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
1298 csum |= loc->mbuf->tso_segsz;
1299 es->flags = rte_cpu_to_be_32(csum);
1301 es->flags = rte_cpu_to_le_32(csum);
1304 * Calculate and set Software Parser offsets and flags.
1305 * These flags a set for custom UDP and IP tunnel packets.
1307 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
1308 /* Fill metadata field if needed. */
1309 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
1310 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
1311 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
1312 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
1313 pdst = (uint8_t *)&es->inline_data;
1314 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
1315 /* Implement VLAN tag insertion as part inline data. */
1316 mlx5_tx_mseg_memcpy(pdst, loc,
1317 2 * RTE_ETHER_ADDR_LEN,
1318 2 * RTE_ETHER_ADDR_LEN, olx);
1319 pdst += 2 * RTE_ETHER_ADDR_LEN;
1320 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
1321 ((RTE_ETHER_TYPE_VLAN << 16) |
1322 loc->mbuf->vlan_tci);
1323 pdst += sizeof(struct rte_vlan_hdr);
1324 tlen += 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
1326 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
1328 * The WQEBB space availability is checked by caller.
1329 * Here we should be aware of WQE ring buffer wraparound only.
1331 part = (uint8_t *)txq->wqes_end - pdst;
1332 part = RTE_MIN(part, inlen - tlen);
1338 * Copying may be interrupted inside the routine
1339 * if run into no inline hint flag.
1341 copy = tso ? inlen : txq->inlen_mode;
1342 copy = tlen >= copy ? 0 : (copy - tlen);
1343 copy = mlx5_tx_mseg_memcpy(pdst, loc, part, copy, olx);
1345 if (likely(inlen <= tlen) || copy < part) {
1346 es->inline_hdr_sz = rte_cpu_to_be_16(tlen);
1348 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
1349 return (struct mlx5_wqe_dseg *)pdst;
1351 pdst = (uint8_t *)txq->wqes;
1352 part = inlen - tlen;
1357 * Build the Data Segment of pointer type.
1360 * Pointer to TX queue structure.
1362 * Pointer to burst routine local context.
1364 * Pointer to WQE to fill with built Data Segment.
1366 * Data buffer to point.
1368 * Data buffer length.
1370 * Configured Tx offloads mask. It is fully defined at
1371 * compile time and may be used for optimization.
1373 static __rte_always_inline void
1374 mlx5_tx_dseg_ptr(struct mlx5_txq_data *__rte_restrict txq,
1375 struct mlx5_txq_local *__rte_restrict loc,
1376 struct mlx5_wqe_dseg *__rte_restrict dseg,
1379 unsigned int olx __rte_unused)
1383 dseg->bcount = rte_cpu_to_be_32(len);
1384 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
1385 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
1389 * Build the Data Segment of pointer type or inline if data length is less than
1390 * buffer in minimal Data Segment size.
1393 * Pointer to TX queue structure.
1395 * Pointer to burst routine local context.
1397 * Pointer to WQE to fill with built Data Segment.
1399 * Data buffer to point.
1401 * Data buffer length.
1403 * Configured Tx offloads mask. It is fully defined at
1404 * compile time and may be used for optimization.
1406 static __rte_always_inline void
1407 mlx5_tx_dseg_iptr(struct mlx5_txq_data *__rte_restrict txq,
1408 struct mlx5_txq_local *__rte_restrict loc,
1409 struct mlx5_wqe_dseg *__rte_restrict dseg,
1412 unsigned int olx __rte_unused)
1418 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
1419 dseg->bcount = rte_cpu_to_be_32(len);
1420 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
1421 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
1425 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
1426 /* Unrolled implementation of generic rte_memcpy. */
1427 dst = (uintptr_t)&dseg->inline_data[0];
1428 src = (uintptr_t)buf;
1430 #ifdef RTE_ARCH_STRICT_ALIGN
1431 MLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
1432 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
1433 dst += sizeof(uint32_t);
1434 src += sizeof(uint32_t);
1435 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
1436 dst += sizeof(uint32_t);
1437 src += sizeof(uint32_t);
1439 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
1440 dst += sizeof(uint64_t);
1441 src += sizeof(uint64_t);
1445 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
1446 dst += sizeof(uint32_t);
1447 src += sizeof(uint32_t);
1450 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
1451 dst += sizeof(uint16_t);
1452 src += sizeof(uint16_t);
1455 *(uint8_t *)dst = *(uint8_t *)src;
1459 * Build the Data Segment of inlined data from single
1460 * segment packet, no VLAN insertion.
1463 * Pointer to TX queue structure.
1465 * Pointer to burst routine local context.
1467 * Pointer to WQE to fill with built Data Segment.
1469 * Data buffer to point.
1471 * Data buffer length.
1473 * Configured Tx offloads mask. It is fully defined at
1474 * compile time and may be used for optimization.
1477 * Pointer to the next Data Segment after inlined data.
1478 * Ring buffer wraparound check is needed. We do not do it here because it
1479 * may not be needed for the last packet in the eMPW session.
1481 static __rte_always_inline struct mlx5_wqe_dseg *
1482 mlx5_tx_dseg_empw(struct mlx5_txq_data *__rte_restrict txq,
1483 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
1484 struct mlx5_wqe_dseg *__rte_restrict dseg,
1487 unsigned int olx __rte_unused)
1492 if (!MLX5_TXOFF_CONFIG(MPW)) {
1493 /* Store the descriptor byte counter for eMPW sessions. */
1494 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
1495 pdst = &dseg->inline_data[0];
1497 /* The entire legacy MPW session counter is stored on close. */
1498 pdst = (uint8_t *)dseg;
1501 * The WQEBB space availability is checked by caller.
1502 * Here we should be aware of WQE ring buffer wraparound only.
1504 part = (uint8_t *)txq->wqes_end - pdst;
1505 part = RTE_MIN(part, len);
1507 rte_memcpy(pdst, buf, part);
1511 if (!MLX5_TXOFF_CONFIG(MPW))
1512 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
1513 /* Note: no final wraparound check here. */
1514 return (struct mlx5_wqe_dseg *)pdst;
1516 pdst = (uint8_t *)txq->wqes;
1523 * Build the Data Segment of inlined data from single
1524 * segment packet with VLAN insertion.
1527 * Pointer to TX queue structure.
1529 * Pointer to burst routine local context.
1531 * Pointer to the dseg fill with built Data Segment.
1533 * Data buffer to point.
1535 * Data buffer length.
1537 * Configured Tx offloads mask. It is fully defined at
1538 * compile time and may be used for optimization.
1541 * Pointer to the next Data Segment after inlined data.
1542 * Ring buffer wraparound check is needed.
1544 static __rte_always_inline struct mlx5_wqe_dseg *
1545 mlx5_tx_dseg_vlan(struct mlx5_txq_data *__rte_restrict txq,
1546 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
1547 struct mlx5_wqe_dseg *__rte_restrict dseg,
1550 unsigned int olx __rte_unused)
1556 MLX5_ASSERT(len > MLX5_ESEG_MIN_INLINE_SIZE);
1557 if (!MLX5_TXOFF_CONFIG(MPW)) {
1558 /* Store the descriptor byte counter for eMPW sessions. */
1559 dseg->bcount = rte_cpu_to_be_32
1560 ((len + sizeof(struct rte_vlan_hdr)) |
1561 MLX5_ETH_WQE_DATA_INLINE);
1562 pdst = &dseg->inline_data[0];
1564 /* The entire legacy MPW session counter is stored on close. */
1565 pdst = (uint8_t *)dseg;
1567 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
1568 buf += MLX5_DSEG_MIN_INLINE_SIZE;
1569 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
1570 len -= MLX5_DSEG_MIN_INLINE_SIZE;
1571 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
1572 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
1573 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
1574 pdst = (uint8_t *)txq->wqes;
1575 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
1576 loc->mbuf->vlan_tci);
1577 pdst += sizeof(struct rte_vlan_hdr);
1579 * The WQEBB space availability is checked by caller.
1580 * Here we should be aware of WQE ring buffer wraparound only.
1582 part = (uint8_t *)txq->wqes_end - pdst;
1583 part = RTE_MIN(part, len);
1585 rte_memcpy(pdst, buf, part);
1589 if (!MLX5_TXOFF_CONFIG(MPW))
1590 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
1591 /* Note: no final wraparound check here. */
1592 return (struct mlx5_wqe_dseg *)pdst;
1594 pdst = (uint8_t *)txq->wqes;
1601 * Build the Ethernet Segment with optionally inlined data with
1602 * VLAN insertion and following Data Segments (if any) from
1603 * multi-segment packet. Used by ordinary send and TSO.
1606 * Pointer to TX queue structure.
1608 * Pointer to burst routine local context.
1610 * Pointer to WQE to fill with built Ethernet/Data Segments.
1612 * Length of VLAN header to insert, 0 means no VLAN insertion.
1614 * Data length to inline. For TSO this parameter specifies exact value,
1615 * for ordinary send routine can be aligned by caller to provide better WQE
1616 * space saving and data buffer start address alignment.
1617 * This length includes VLAN header being inserted.
1619 * Zero means ordinary send, inlined data can be extended,
1620 * otherwise this is TSO, inlined data length is fixed.
1622 * Configured Tx offloads mask. It is fully defined at
1623 * compile time and may be used for optimization.
1626 * Actual size of built WQE in segments.
1628 static __rte_always_inline unsigned int
1629 mlx5_tx_mseg_build(struct mlx5_txq_data *__rte_restrict txq,
1630 struct mlx5_txq_local *__rte_restrict loc,
1631 struct mlx5_wqe *__rte_restrict wqe,
1635 unsigned int olx __rte_unused)
1637 struct mlx5_wqe_dseg *__rte_restrict dseg;
1640 MLX5_ASSERT((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
1641 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
1644 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
1645 if (!loc->mbuf_nseg)
1648 * There are still some mbuf remaining, not inlined.
1649 * The first mbuf may be partially inlined and we
1650 * must process the possible non-zero data offset.
1652 if (loc->mbuf_off) {
1657 * Exhausted packets must be dropped before.
1658 * Non-zero offset means there are some data
1659 * remained in the packet.
1661 MLX5_ASSERT(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
1662 MLX5_ASSERT(rte_pktmbuf_data_len(loc->mbuf));
1663 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
1665 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
1667 * Build the pointer/minimal Data Segment.
1668 * Do ring buffer wrapping check in advance.
1670 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
1671 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
1672 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
1673 /* Store the mbuf to be freed on completion. */
1674 MLX5_ASSERT(loc->elts_free);
1675 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
1678 if (--loc->mbuf_nseg == 0)
1680 loc->mbuf = loc->mbuf->next;
1684 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
1685 struct rte_mbuf *mbuf;
1687 /* Zero length segment found, just skip. */
1689 loc->mbuf = loc->mbuf->next;
1690 rte_pktmbuf_free_seg(mbuf);
1691 if (--loc->mbuf_nseg == 0)
1694 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
1695 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
1698 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
1699 rte_pktmbuf_data_len(loc->mbuf), olx);
1700 MLX5_ASSERT(loc->elts_free);
1701 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
1704 if (--loc->mbuf_nseg == 0)
1706 loc->mbuf = loc->mbuf->next;
1711 /* Calculate actual segments used from the dseg pointer. */
1712 if ((uintptr_t)wqe < (uintptr_t)dseg)
1713 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
1715 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
1716 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
1721 * The routine checks timestamp flag in the current packet,
1722 * and push WAIT WQE into the queue if scheduling is required.
1725 * Pointer to TX queue structure.
1727 * Pointer to burst routine local context.
1729 * Configured Tx offloads mask. It is fully defined at
1730 * compile time and may be used for optimization.
1733 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
1734 * MLX5_TXCMP_CODE_SINGLE - continue processing with the packet.
1735 * MLX5_TXCMP_CODE_MULTI - the WAIT inserted, continue processing.
1736 * Local context variables partially updated.
1738 static __rte_always_inline enum mlx5_txcmp_code
1739 mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
1740 struct mlx5_txq_local *restrict loc,
1743 if (MLX5_TXOFF_CONFIG(TXPP) &&
1744 loc->mbuf->ol_flags & txq->ts_mask) {
1745 struct mlx5_wqe *wqe;
1750 * Estimate the required space quickly and roughly.
1751 * We would like to ensure the packet can be pushed
1752 * to the queue and we won't get the orphan WAIT WQE.
1754 if (loc->wqe_free <= MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE ||
1755 loc->elts_free < NB_SEGS(loc->mbuf))
1756 return MLX5_TXCMP_CODE_EXIT;
1757 /* Convert the timestamp into completion to wait. */
1758 ts = *RTE_MBUF_DYNFIELD(loc->mbuf, txq->ts_offset, uint64_t *);
1759 wci = mlx5_txpp_convert_tx_ts(txq->sh, ts);
1760 if (unlikely(wci < 0))
1761 return MLX5_TXCMP_CODE_SINGLE;
1762 /* Build the WAIT WQE with specified completion. */
1763 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
1764 mlx5_tx_cseg_init(txq, loc, wqe, 2, MLX5_OPCODE_WAIT, olx);
1765 mlx5_tx_wseg_init(txq, loc, wqe, wci, olx);
1768 return MLX5_TXCMP_CODE_MULTI;
1770 return MLX5_TXCMP_CODE_SINGLE;
1774 * Tx one packet function for multi-segment TSO. Supports all
1775 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
1776 * sends one packet per WQE.
1778 * This routine is responsible for storing processed mbuf
1779 * into elts ring buffer and update elts_head.
1782 * Pointer to TX queue structure.
1784 * Pointer to burst routine local context.
1786 * Configured Tx offloads mask. It is fully defined at
1787 * compile time and may be used for optimization.
1790 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
1791 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
1792 * Local context variables partially updated.
1794 static __rte_always_inline enum mlx5_txcmp_code
1795 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
1796 struct mlx5_txq_local *__rte_restrict loc,
1799 struct mlx5_wqe *__rte_restrict wqe;
1800 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
1802 if (MLX5_TXOFF_CONFIG(TXPP)) {
1803 enum mlx5_txcmp_code wret;
1805 /* Generate WAIT for scheduling if requested. */
1806 wret = mlx5_tx_schedule_send(txq, loc, olx);
1807 if (wret == MLX5_TXCMP_CODE_EXIT)
1808 return MLX5_TXCMP_CODE_EXIT;
1809 if (wret == MLX5_TXCMP_CODE_ERROR)
1810 return MLX5_TXCMP_CODE_ERROR;
1813 * Calculate data length to be inlined to estimate
1814 * the required space in WQE ring buffer.
1816 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
1817 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
1818 vlan = sizeof(struct rte_vlan_hdr);
1819 inlen = loc->mbuf->l2_len + vlan +
1820 loc->mbuf->l3_len + loc->mbuf->l4_len;
1821 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
1822 return MLX5_TXCMP_CODE_ERROR;
1823 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
1824 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
1825 /* Packet must contain all TSO headers. */
1826 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
1827 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
1828 inlen > (dlen + vlan)))
1829 return MLX5_TXCMP_CODE_ERROR;
1830 MLX5_ASSERT(inlen >= txq->inlen_mode);
1832 * Check whether there are enough free WQEBBs:
1834 * - Ethernet Segment
1835 * - First Segment of inlined Ethernet data
1836 * - ... data continued ...
1837 * - Data Segments of pointer/min inline type
1839 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
1840 MLX5_ESEG_MIN_INLINE_SIZE +
1842 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
1843 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
1844 return MLX5_TXCMP_CODE_EXIT;
1845 /* Check for maximal WQE size. */
1846 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
1847 return MLX5_TXCMP_CODE_ERROR;
1848 #ifdef MLX5_PMD_SOFT_COUNTERS
1849 /* Update sent data bytes/packets counters. */
1850 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
1851 loc->mbuf->tso_segsz;
1853 * One will be added for mbuf itself at the end of the mlx5_tx_burst
1854 * from loc->pkts_sent field.
1857 txq->stats.opackets += ntcp;
1858 txq->stats.obytes += dlen + vlan + ntcp * inlen;
1860 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
1861 loc->wqe_last = wqe;
1862 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
1863 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
1864 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
1865 txq->wqe_ci += (ds + 3) / 4;
1866 loc->wqe_free -= (ds + 3) / 4;
1867 return MLX5_TXCMP_CODE_MULTI;
1871 * Tx one packet function for multi-segment SEND. Supports all types of Tx
1872 * offloads, uses MLX5_OPCODE_SEND to build WQEs, sends one packet per WQE,
1873 * without any data inlining in Ethernet Segment.
1875 * This routine is responsible for storing processed mbuf
1876 * into elts ring buffer and update elts_head.
1879 * Pointer to TX queue structure.
1881 * Pointer to burst routine local context.
1883 * Configured Tx offloads mask. It is fully defined at
1884 * compile time and may be used for optimization.
1887 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
1888 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
1889 * Local context variables partially updated.
1891 static __rte_always_inline enum mlx5_txcmp_code
1892 mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
1893 struct mlx5_txq_local *__rte_restrict loc,
1896 struct mlx5_wqe_dseg *__rte_restrict dseg;
1897 struct mlx5_wqe *__rte_restrict wqe;
1898 unsigned int ds, nseg;
1900 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
1901 if (MLX5_TXOFF_CONFIG(TXPP)) {
1902 enum mlx5_txcmp_code wret;
1904 /* Generate WAIT for scheduling if requested. */
1905 wret = mlx5_tx_schedule_send(txq, loc, olx);
1906 if (wret == MLX5_TXCMP_CODE_EXIT)
1907 return MLX5_TXCMP_CODE_EXIT;
1908 if (wret == MLX5_TXCMP_CODE_ERROR)
1909 return MLX5_TXCMP_CODE_ERROR;
1912 * No inline at all, it means the CPU cycles saving is prioritized at
1913 * configuration, we should not copy any packet data to WQE.
1915 nseg = NB_SEGS(loc->mbuf);
1917 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
1918 return MLX5_TXCMP_CODE_EXIT;
1919 /* Check for maximal WQE size. */
1920 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
1921 return MLX5_TXCMP_CODE_ERROR;
1923 * Some Tx offloads may cause an error if packet is not long enough,
1924 * check against assumed minimal length.
1926 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
1927 return MLX5_TXCMP_CODE_ERROR;
1928 #ifdef MLX5_PMD_SOFT_COUNTERS
1929 /* Update sent data bytes counter. */
1930 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
1931 if (MLX5_TXOFF_CONFIG(VLAN) &&
1932 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
1933 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
1936 * SEND WQE, one WQEBB:
1937 * - Control Segment, SEND opcode
1938 * - Ethernet Segment, optional VLAN, no inline
1939 * - Data Segments, pointer only type
1941 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
1942 loc->wqe_last = wqe;
1943 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
1944 mlx5_tx_eseg_none(txq, loc, wqe, olx);
1945 dseg = &wqe->dseg[0];
1947 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
1948 struct rte_mbuf *mbuf;
1951 * Zero length segment found, have to correct total
1952 * size of WQE in segments.
1953 * It is supposed to be rare occasion, so in normal
1954 * case (no zero length segments) we avoid extra
1955 * writing to the Control Segment.
1958 wqe->cseg.sq_ds -= RTE_BE32(1);
1960 loc->mbuf = mbuf->next;
1961 rte_pktmbuf_free_seg(mbuf);
1967 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
1968 rte_pktmbuf_data_len(loc->mbuf), olx);
1969 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
1974 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
1975 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
1976 loc->mbuf = loc->mbuf->next;
1979 txq->wqe_ci += (ds + 3) / 4;
1980 loc->wqe_free -= (ds + 3) / 4;
1981 return MLX5_TXCMP_CODE_MULTI;
1985 * Tx one packet function for multi-segment SEND. Supports all
1986 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
1987 * sends one packet per WQE, with data inlining in
1988 * Ethernet Segment and minimal Data Segments.
1990 * This routine is responsible for storing processed mbuf
1991 * into elts ring buffer and update elts_head.
1994 * Pointer to TX queue structure.
1996 * Pointer to burst routine local context.
1998 * Configured Tx offloads mask. It is fully defined at
1999 * compile time and may be used for optimization.
2002 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
2003 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
2004 * Local context variables partially updated.
2006 static __rte_always_inline enum mlx5_txcmp_code
2007 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
2008 struct mlx5_txq_local *__rte_restrict loc,
2011 struct mlx5_wqe *__rte_restrict wqe;
2012 unsigned int ds, inlen, dlen, vlan = 0;
2014 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
2015 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
2016 if (MLX5_TXOFF_CONFIG(TXPP)) {
2017 enum mlx5_txcmp_code wret;
2019 /* Generate WAIT for scheduling if requested. */
2020 wret = mlx5_tx_schedule_send(txq, loc, olx);
2021 if (wret == MLX5_TXCMP_CODE_EXIT)
2022 return MLX5_TXCMP_CODE_EXIT;
2023 if (wret == MLX5_TXCMP_CODE_ERROR)
2024 return MLX5_TXCMP_CODE_ERROR;
2027 * First calculate data length to be inlined
2028 * to estimate the required space for WQE.
2030 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
2031 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
2032 vlan = sizeof(struct rte_vlan_hdr);
2033 inlen = dlen + vlan;
2034 /* Check against minimal length. */
2035 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
2036 return MLX5_TXCMP_CODE_ERROR;
2037 MLX5_ASSERT(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
2038 if (inlen > txq->inlen_send ||
2039 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
2040 struct rte_mbuf *mbuf;
2045 nxlen = rte_pktmbuf_data_len(mbuf);
2047 * Packet length exceeds the allowed inline data length,
2048 * check whether the minimal inlining is required.
2050 if (txq->inlen_mode) {
2051 MLX5_ASSERT(txq->inlen_mode >=
2052 MLX5_ESEG_MIN_INLINE_SIZE);
2053 MLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);
2054 inlen = txq->inlen_mode;
2055 } else if (vlan && !txq->vlan_en) {
2057 * VLAN insertion is requested and hardware does not
2058 * support the offload, will do with software inline.
2060 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
2061 } else if (mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||
2062 nxlen > txq->inlen_send) {
2063 return mlx5_tx_packet_multi_send(txq, loc, olx);
2068 * Now we know the minimal amount of data is requested
2069 * to inline. Check whether we should inline the buffers
2070 * from the chain beginning to eliminate some mbufs.
2072 if (unlikely(nxlen <= txq->inlen_send)) {
2073 /* We can inline first mbuf at least. */
2074 if (nxlen < inlen) {
2077 /* Scan mbufs till inlen filled. */
2082 nxlen = rte_pktmbuf_data_len(mbuf);
2084 } while (unlikely(nxlen < inlen));
2085 if (unlikely(nxlen > txq->inlen_send)) {
2086 /* We cannot inline entire mbuf. */
2087 smlen = inlen - smlen;
2088 start = rte_pktmbuf_mtod_offset
2089 (mbuf, uintptr_t, smlen);
2097 /* There should be not end of packet. */
2099 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
2100 } while (unlikely(nxlen < txq->inlen_send));
2102 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
2104 * Check whether we can do inline to align start
2105 * address of data buffer to cacheline.
2108 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
2109 if (unlikely(start)) {
2111 if (start <= txq->inlen_send)
2116 * Check whether there are enough free WQEBBs:
2118 * - Ethernet Segment
2119 * - First Segment of inlined Ethernet data
2120 * - ... data continued ...
2121 * - Data Segments of pointer/min inline type
2123 * Estimate the number of Data Segments conservatively,
2124 * supposing no any mbufs is being freed during inlining.
2126 MLX5_ASSERT(inlen <= txq->inlen_send);
2127 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
2128 MLX5_ESEG_MIN_INLINE_SIZE +
2130 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
2131 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
2132 return MLX5_TXCMP_CODE_EXIT;
2133 /* Check for maximal WQE size. */
2134 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
2135 return MLX5_TXCMP_CODE_ERROR;
2136 #ifdef MLX5_PMD_SOFT_COUNTERS
2137 /* Update sent data bytes/packets counters. */
2138 txq->stats.obytes += dlen + vlan;
2140 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
2141 loc->wqe_last = wqe;
2142 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
2143 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
2144 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2145 txq->wqe_ci += (ds + 3) / 4;
2146 loc->wqe_free -= (ds + 3) / 4;
2147 return MLX5_TXCMP_CODE_MULTI;
2151 * Tx burst function for multi-segment packets. Supports all
2152 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
2153 * sends one packet per WQE. Function stops sending if it
2154 * encounters the single-segment packet.
2156 * This routine is responsible for storing processed mbuf
2157 * into elts ring buffer and update elts_head.
2160 * Pointer to TX queue structure.
2162 * Packets to transmit.
2164 * Number of packets in array.
2166 * Pointer to burst routine local context.
2168 * Configured Tx offloads mask. It is fully defined at
2169 * compile time and may be used for optimization.
2172 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
2173 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
2174 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
2175 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
2176 * Local context variables updated.
2178 static __rte_always_inline enum mlx5_txcmp_code
2179 mlx5_tx_burst_mseg(struct mlx5_txq_data *__rte_restrict txq,
2180 struct rte_mbuf **__rte_restrict pkts,
2181 unsigned int pkts_n,
2182 struct mlx5_txq_local *__rte_restrict loc,
2185 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
2186 MLX5_ASSERT(pkts_n > loc->pkts_sent);
2187 pkts += loc->pkts_sent + 1;
2188 pkts_n -= loc->pkts_sent;
2190 enum mlx5_txcmp_code ret;
2192 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
2194 * Estimate the number of free elts quickly but conservatively.
2195 * Some segment may be fully inlined and freed,
2196 * ignore this here - precise estimation is costly.
2198 if (loc->elts_free < NB_SEGS(loc->mbuf))
2199 return MLX5_TXCMP_CODE_EXIT;
2200 if (MLX5_TXOFF_CONFIG(TSO) &&
2201 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
2202 /* Proceed with multi-segment TSO. */
2203 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
2204 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
2205 /* Proceed with multi-segment SEND with inlining. */
2206 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
2208 /* Proceed with multi-segment SEND w/o inlining. */
2209 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
2211 if (ret == MLX5_TXCMP_CODE_EXIT)
2212 return MLX5_TXCMP_CODE_EXIT;
2213 if (ret == MLX5_TXCMP_CODE_ERROR)
2214 return MLX5_TXCMP_CODE_ERROR;
2215 /* WQE is built, go to the next packet. */
2218 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
2219 return MLX5_TXCMP_CODE_EXIT;
2220 loc->mbuf = *pkts++;
2222 rte_prefetch0(*pkts);
2223 if (likely(NB_SEGS(loc->mbuf) > 1))
2225 /* Here ends the series of multi-segment packets. */
2226 if (MLX5_TXOFF_CONFIG(TSO) &&
2227 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
2228 return MLX5_TXCMP_CODE_TSO;
2229 return MLX5_TXCMP_CODE_SINGLE;
2235 * Tx burst function for single-segment packets with TSO.
2236 * Supports all types of Tx offloads, except multi-packets.
2237 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
2238 * Function stops sending if it encounters the multi-segment
2239 * packet or packet without TSO requested.
2241 * The routine is responsible for storing processed mbuf into elts ring buffer
2242 * and update elts_head if inline offloads is requested due to possible early
2243 * freeing of the inlined mbufs (can not store pkts array in elts as a batch).
2246 * Pointer to TX queue structure.
2248 * Packets to transmit.
2250 * Number of packets in array.
2252 * Pointer to burst routine local context.
2254 * Configured Tx offloads mask. It is fully defined at
2255 * compile time and may be used for optimization.
2258 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
2259 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
2260 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
2261 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
2262 * Local context variables updated.
2264 static __rte_always_inline enum mlx5_txcmp_code
2265 mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
2266 struct rte_mbuf **__rte_restrict pkts,
2267 unsigned int pkts_n,
2268 struct mlx5_txq_local *__rte_restrict loc,
2271 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
2272 MLX5_ASSERT(pkts_n > loc->pkts_sent);
2273 pkts += loc->pkts_sent + 1;
2274 pkts_n -= loc->pkts_sent;
2276 struct mlx5_wqe_dseg *__rte_restrict dseg;
2277 struct mlx5_wqe *__rte_restrict wqe;
2278 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
2281 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
2282 if (MLX5_TXOFF_CONFIG(TXPP)) {
2283 enum mlx5_txcmp_code wret;
2285 /* Generate WAIT for scheduling if requested. */
2286 wret = mlx5_tx_schedule_send(txq, loc, olx);
2287 if (wret == MLX5_TXCMP_CODE_EXIT)
2288 return MLX5_TXCMP_CODE_EXIT;
2289 if (wret == MLX5_TXCMP_CODE_ERROR)
2290 return MLX5_TXCMP_CODE_ERROR;
2292 dlen = rte_pktmbuf_data_len(loc->mbuf);
2293 if (MLX5_TXOFF_CONFIG(VLAN) &&
2294 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2295 vlan = sizeof(struct rte_vlan_hdr);
2298 * First calculate the WQE size to check
2299 * whether we have enough space in ring buffer.
2301 hlen = loc->mbuf->l2_len + vlan +
2302 loc->mbuf->l3_len + loc->mbuf->l4_len;
2303 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
2304 return MLX5_TXCMP_CODE_ERROR;
2305 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
2306 hlen += loc->mbuf->outer_l2_len +
2307 loc->mbuf->outer_l3_len;
2308 /* Segment must contain all TSO headers. */
2309 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
2310 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
2311 hlen > (dlen + vlan)))
2312 return MLX5_TXCMP_CODE_ERROR;
2314 * Check whether there are enough free WQEBBs:
2316 * - Ethernet Segment
2317 * - First Segment of inlined Ethernet data
2318 * - ... data continued ...
2319 * - Finishing Data Segment of pointer type
2321 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
2322 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
2323 if (loc->wqe_free < ((ds + 3) / 4))
2324 return MLX5_TXCMP_CODE_EXIT;
2325 #ifdef MLX5_PMD_SOFT_COUNTERS
2326 /* Update sent data bytes/packets counters. */
2327 ntcp = (dlen + vlan - hlen +
2328 loc->mbuf->tso_segsz - 1) /
2329 loc->mbuf->tso_segsz;
2331 * One will be added for mbuf itself at the end
2332 * of the mlx5_tx_burst from loc->pkts_sent field.
2335 txq->stats.opackets += ntcp;
2336 txq->stats.obytes += dlen + vlan + ntcp * hlen;
2339 * Build the TSO WQE:
2341 * - Ethernet Segment with hlen bytes inlined
2342 * - Data Segment of pointer type
2344 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
2345 loc->wqe_last = wqe;
2346 mlx5_tx_cseg_init(txq, loc, wqe, ds,
2347 MLX5_OPCODE_TSO, olx);
2348 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
2349 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
2350 dlen -= hlen - vlan;
2351 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
2353 * WQE is built, update the loop parameters
2354 * and go to the next packet.
2356 txq->wqe_ci += (ds + 3) / 4;
2357 loc->wqe_free -= (ds + 3) / 4;
2358 if (MLX5_TXOFF_CONFIG(INLINE))
2359 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2363 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
2364 return MLX5_TXCMP_CODE_EXIT;
2365 loc->mbuf = *pkts++;
2367 rte_prefetch0(*pkts);
2368 if (MLX5_TXOFF_CONFIG(MULTI) &&
2369 unlikely(NB_SEGS(loc->mbuf) > 1))
2370 return MLX5_TXCMP_CODE_MULTI;
2371 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
2372 return MLX5_TXCMP_CODE_SINGLE;
2373 /* Continue with the next TSO packet. */
2379 * Analyze the packet and select the best method to send.
2382 * Pointer to TX queue structure.
2384 * Pointer to burst routine local context.
2386 * Configured Tx offloads mask. It is fully defined at
2387 * compile time and may be used for optimization.
2389 * The predefined flag whether do complete check for
2390 * multi-segment packets and TSO.
2393 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
2394 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
2395 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
2396 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
2398 static __rte_always_inline enum mlx5_txcmp_code
2399 mlx5_tx_able_to_empw(struct mlx5_txq_data *__rte_restrict txq,
2400 struct mlx5_txq_local *__rte_restrict loc,
2404 /* Check for multi-segment packet. */
2406 MLX5_TXOFF_CONFIG(MULTI) &&
2407 unlikely(NB_SEGS(loc->mbuf) > 1))
2408 return MLX5_TXCMP_CODE_MULTI;
2409 /* Check for TSO packet. */
2411 MLX5_TXOFF_CONFIG(TSO) &&
2412 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
2413 return MLX5_TXCMP_CODE_TSO;
2414 /* Check if eMPW is enabled at all. */
2415 if (!MLX5_TXOFF_CONFIG(EMPW))
2416 return MLX5_TXCMP_CODE_SINGLE;
2417 /* Check if eMPW can be engaged. */
2418 if (MLX5_TXOFF_CONFIG(VLAN) &&
2419 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
2420 (!MLX5_TXOFF_CONFIG(INLINE) ||
2421 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
2422 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
2424 * eMPW does not support VLAN insertion offload, we have to
2425 * inline the entire packet but packet is too long for inlining.
2427 return MLX5_TXCMP_CODE_SINGLE;
2429 return MLX5_TXCMP_CODE_EMPW;
2433 * Check the next packet attributes to match with the eMPW batch ones.
2434 * In addition, for legacy MPW the packet length is checked either.
2437 * Pointer to TX queue structure.
2439 * Pointer to Ethernet Segment of eMPW batch.
2441 * Pointer to burst routine local context.
2443 * Length of previous packet in MPW descriptor.
2445 * Configured Tx offloads mask. It is fully defined at
2446 * compile time and may be used for optimization.
2449 * true - packet match with eMPW batch attributes.
2450 * false - no match, eMPW should be restarted.
2452 static __rte_always_inline bool
2453 mlx5_tx_match_empw(struct mlx5_txq_data *__rte_restrict txq,
2454 struct mlx5_wqe_eseg *__rte_restrict es,
2455 struct mlx5_txq_local *__rte_restrict loc,
2459 uint8_t swp_flags = 0;
2461 /* Compare the checksum flags, if any. */
2462 if (MLX5_TXOFF_CONFIG(CSUM) &&
2463 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
2465 /* Compare the Software Parser offsets and flags. */
2466 if (MLX5_TXOFF_CONFIG(SWP) &&
2467 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
2468 es->swp_flags != swp_flags))
2470 /* Fill metadata field if needed. */
2471 if (MLX5_TXOFF_CONFIG(METADATA) &&
2472 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2473 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
2475 /* Legacy MPW can send packets with the same length only. */
2476 if (MLX5_TXOFF_CONFIG(MPW) &&
2477 dlen != rte_pktmbuf_data_len(loc->mbuf))
2479 /* There must be no VLAN packets in eMPW loop. */
2480 if (MLX5_TXOFF_CONFIG(VLAN))
2481 MLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
2482 /* Check if the scheduling is requested. */
2483 if (MLX5_TXOFF_CONFIG(TXPP) &&
2484 loc->mbuf->ol_flags & txq->ts_mask)
2490 * Update send loop variables and WQE for eMPW loop without data inlining.
2491 * Number of Data Segments is equal to the number of sent packets.
2494 * Pointer to TX queue structure.
2496 * Pointer to burst routine local context.
2498 * Number of packets/Data Segments/Packets.
2500 * Accumulated statistics, bytes sent.
2502 * Configured Tx offloads mask. It is fully defined at
2503 * compile time and may be used for optimization.
2506 * true - packet match with eMPW batch attributes.
2507 * false - no match, eMPW should be restarted.
2509 static __rte_always_inline void
2510 mlx5_tx_sdone_empw(struct mlx5_txq_data *__rte_restrict txq,
2511 struct mlx5_txq_local *__rte_restrict loc,
2514 unsigned int olx __rte_unused)
2516 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
2517 #ifdef MLX5_PMD_SOFT_COUNTERS
2518 /* Update sent data bytes counter. */
2519 txq->stats.obytes += slen;
2523 loc->elts_free -= ds;
2524 loc->pkts_sent += ds;
2526 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2527 txq->wqe_ci += (ds + 3) / 4;
2528 loc->wqe_free -= (ds + 3) / 4;
2532 * Update send loop variables and WQE for eMPW loop with data inlining.
2533 * Gets the size of pushed descriptors and data to the WQE.
2536 * Pointer to TX queue structure.
2538 * Pointer to burst routine local context.
2540 * Total size of descriptor/data in bytes.
2542 * Accumulated statistics, data bytes sent.
2544 * The base WQE for the eMPW/MPW descriptor.
2546 * Configured Tx offloads mask. It is fully defined at
2547 * compile time and may be used for optimization.
2550 * true - packet match with eMPW batch attributes.
2551 * false - no match, eMPW should be restarted.
2553 static __rte_always_inline void
2554 mlx5_tx_idone_empw(struct mlx5_txq_data *__rte_restrict txq,
2555 struct mlx5_txq_local *__rte_restrict loc,
2558 struct mlx5_wqe *__rte_restrict wqem,
2559 unsigned int olx __rte_unused)
2561 struct mlx5_wqe_dseg *dseg = &wqem->dseg[0];
2563 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
2564 #ifdef MLX5_PMD_SOFT_COUNTERS
2565 /* Update sent data bytes counter. */
2566 txq->stats.obytes += slen;
2570 if (MLX5_TXOFF_CONFIG(MPW) && dseg->bcount == RTE_BE32(0)) {
2572 * If the legacy MPW session contains the inline packets
2573 * we should set the only inline data segment length
2574 * and align the total length to the segment size.
2576 MLX5_ASSERT(len > sizeof(dseg->bcount));
2577 dseg->bcount = rte_cpu_to_be_32((len - sizeof(dseg->bcount)) |
2578 MLX5_ETH_WQE_DATA_INLINE);
2579 len = (len + MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE + 2;
2582 * The session is not legacy MPW or contains the
2583 * data buffer pointer segments.
2585 MLX5_ASSERT((len % MLX5_WSEG_SIZE) == 0);
2586 len = len / MLX5_WSEG_SIZE + 2;
2588 wqem->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
2589 txq->wqe_ci += (len + 3) / 4;
2590 loc->wqe_free -= (len + 3) / 4;
2591 loc->wqe_last = wqem;
2595 * The set of Tx burst functions for single-segment packets without TSO
2596 * and with Multi-Packet Writing feature support.
2597 * Supports all types of Tx offloads, except multi-packets and TSO.
2599 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends as many packet
2600 * per WQE as it can. If eMPW is not configured or packet can not be sent with
2601 * eMPW (VLAN insertion) the ordinary SEND opcode is used and only one packet
2604 * Functions stop sending if it encounters the multi-segment packet or packet
2605 * with TSO requested.
2607 * The routines are responsible for storing processed mbuf into elts ring buffer
2608 * and update elts_head if inlining offload is requested. Otherwise the copying
2609 * mbufs to elts can be postponed and completed at the end of burst routine.
2612 * Pointer to TX queue structure.
2614 * Packets to transmit.
2616 * Number of packets in array.
2618 * Pointer to burst routine local context.
2620 * Configured Tx offloads mask. It is fully defined at
2621 * compile time and may be used for optimization.
2624 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
2625 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
2626 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
2627 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
2628 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
2629 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
2631 * Local context variables updated.
2634 * The routine sends packets with MLX5_OPCODE_EMPW
2635 * without inlining, this is dedicated optimized branch.
2636 * No VLAN insertion is supported.
2638 static __rte_always_inline enum mlx5_txcmp_code
2639 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
2640 struct rte_mbuf **__rte_restrict pkts,
2641 unsigned int pkts_n,
2642 struct mlx5_txq_local *__rte_restrict loc,
2646 * Subroutine is the part of mlx5_tx_burst_single() and sends
2647 * single-segment packet with eMPW opcode without data inlining.
2649 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
2650 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
2651 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
2652 MLX5_ASSERT(pkts_n > loc->pkts_sent);
2653 pkts += loc->pkts_sent + 1;
2654 pkts_n -= loc->pkts_sent;
2656 struct mlx5_wqe_dseg *__rte_restrict dseg;
2657 struct mlx5_wqe_eseg *__rte_restrict eseg;
2658 enum mlx5_txcmp_code ret;
2659 unsigned int part, loop;
2660 unsigned int slen = 0;
2663 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
2664 if (MLX5_TXOFF_CONFIG(TXPP)) {
2665 enum mlx5_txcmp_code wret;
2667 /* Generate WAIT for scheduling if requested. */
2668 wret = mlx5_tx_schedule_send(txq, loc, olx);
2669 if (wret == MLX5_TXCMP_CODE_EXIT)
2670 return MLX5_TXCMP_CODE_EXIT;
2671 if (wret == MLX5_TXCMP_CODE_ERROR)
2672 return MLX5_TXCMP_CODE_ERROR;
2674 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
2675 MLX5_MPW_MAX_PACKETS :
2676 MLX5_EMPW_MAX_PACKETS);
2677 if (unlikely(loc->elts_free < part)) {
2678 /* We have no enough elts to save all mbufs. */
2679 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
2680 return MLX5_TXCMP_CODE_EXIT;
2681 /* But we still able to send at least minimal eMPW. */
2682 part = loc->elts_free;
2684 /* Check whether we have enough WQEs */
2685 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
2686 if (unlikely(loc->wqe_free <
2687 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
2688 return MLX5_TXCMP_CODE_EXIT;
2689 part = (loc->wqe_free * 4) - 2;
2691 if (likely(part > 1))
2692 rte_prefetch0(*pkts);
2693 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
2695 * Build eMPW title WQEBB:
2696 * - Control Segment, eMPW opcode
2697 * - Ethernet Segment, no inline
2699 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
2700 MLX5_OPCODE_ENHANCED_MPSW, olx);
2701 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
2702 olx & ~MLX5_TXOFF_CONFIG_VLAN);
2703 eseg = &loc->wqe_last->eseg;
2704 dseg = &loc->wqe_last->dseg[0];
2706 /* Store the packet length for legacy MPW. */
2707 if (MLX5_TXOFF_CONFIG(MPW))
2708 eseg->mss = rte_cpu_to_be_16
2709 (rte_pktmbuf_data_len(loc->mbuf));
2711 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
2712 #ifdef MLX5_PMD_SOFT_COUNTERS
2713 /* Update sent data bytes counter. */
2718 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
2720 if (unlikely(--loop == 0))
2722 loc->mbuf = *pkts++;
2723 if (likely(loop > 1))
2724 rte_prefetch0(*pkts);
2725 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
2727 * Unroll the completion code to avoid
2728 * returning variable value - it results in
2729 * unoptimized sequent checking in caller.
2731 if (ret == MLX5_TXCMP_CODE_MULTI) {
2733 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
2734 if (unlikely(!loc->elts_free ||
2736 return MLX5_TXCMP_CODE_EXIT;
2737 return MLX5_TXCMP_CODE_MULTI;
2739 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
2740 if (ret == MLX5_TXCMP_CODE_TSO) {
2742 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
2743 if (unlikely(!loc->elts_free ||
2745 return MLX5_TXCMP_CODE_EXIT;
2746 return MLX5_TXCMP_CODE_TSO;
2748 if (ret == MLX5_TXCMP_CODE_SINGLE) {
2750 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
2751 if (unlikely(!loc->elts_free ||
2753 return MLX5_TXCMP_CODE_EXIT;
2754 return MLX5_TXCMP_CODE_SINGLE;
2756 if (ret != MLX5_TXCMP_CODE_EMPW) {
2759 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
2760 return MLX5_TXCMP_CODE_ERROR;
2763 * Check whether packet parameters coincide
2764 * within assumed eMPW batch:
2765 * - check sum settings
2767 * - software parser settings
2768 * - packets length (legacy MPW only)
2769 * - scheduling is not required
2771 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
2774 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
2775 if (unlikely(!loc->elts_free ||
2777 return MLX5_TXCMP_CODE_EXIT;
2781 /* Packet attributes match, continue the same eMPW. */
2783 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2784 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2786 /* eMPW is built successfully, update loop parameters. */
2788 MLX5_ASSERT(pkts_n >= part);
2789 #ifdef MLX5_PMD_SOFT_COUNTERS
2790 /* Update sent data bytes counter. */
2791 txq->stats.obytes += slen;
2793 loc->elts_free -= part;
2794 loc->pkts_sent += part;
2795 txq->wqe_ci += (2 + part + 3) / 4;
2796 loc->wqe_free -= (2 + part + 3) / 4;
2798 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
2799 return MLX5_TXCMP_CODE_EXIT;
2800 loc->mbuf = *pkts++;
2801 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
2802 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
2804 /* Continue sending eMPW batches. */
2810 * The routine sends packets with MLX5_OPCODE_EMPW
2811 * with inlining, optionally supports VLAN insertion.
2813 static __rte_always_inline enum mlx5_txcmp_code
2814 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
2815 struct rte_mbuf **__rte_restrict pkts,
2816 unsigned int pkts_n,
2817 struct mlx5_txq_local *__rte_restrict loc,
2821 * Subroutine is the part of mlx5_tx_burst_single() and sends
2822 * single-segment packet with eMPW opcode with data inlining.
2824 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
2825 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
2826 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
2827 MLX5_ASSERT(pkts_n > loc->pkts_sent);
2828 pkts += loc->pkts_sent + 1;
2829 pkts_n -= loc->pkts_sent;
2831 struct mlx5_wqe_dseg *__rte_restrict dseg;
2832 struct mlx5_wqe *__rte_restrict wqem;
2833 enum mlx5_txcmp_code ret;
2834 unsigned int room, part, nlim;
2835 unsigned int slen = 0;
2837 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
2838 if (MLX5_TXOFF_CONFIG(TXPP)) {
2839 enum mlx5_txcmp_code wret;
2841 /* Generate WAIT for scheduling if requested. */
2842 wret = mlx5_tx_schedule_send(txq, loc, olx);
2843 if (wret == MLX5_TXCMP_CODE_EXIT)
2844 return MLX5_TXCMP_CODE_EXIT;
2845 if (wret == MLX5_TXCMP_CODE_ERROR)
2846 return MLX5_TXCMP_CODE_ERROR;
2849 * Limits the amount of packets in one WQE
2850 * to improve CQE latency generation.
2852 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
2853 MLX5_MPW_INLINE_MAX_PACKETS :
2854 MLX5_EMPW_MAX_PACKETS);
2855 /* Check whether we have minimal amount WQEs */
2856 if (unlikely(loc->wqe_free <
2857 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
2858 return MLX5_TXCMP_CODE_EXIT;
2859 if (likely(pkts_n > 1))
2860 rte_prefetch0(*pkts);
2861 wqem = txq->wqes + (txq->wqe_ci & txq->wqe_m);
2863 * Build eMPW title WQEBB:
2864 * - Control Segment, eMPW opcode, zero DS
2865 * - Ethernet Segment, no inline
2867 mlx5_tx_cseg_init(txq, loc, wqem, 0,
2868 MLX5_OPCODE_ENHANCED_MPSW, olx);
2869 mlx5_tx_eseg_none(txq, loc, wqem,
2870 olx & ~MLX5_TXOFF_CONFIG_VLAN);
2871 dseg = &wqem->dseg[0];
2872 /* Store the packet length for legacy MPW. */
2873 if (MLX5_TXOFF_CONFIG(MPW))
2874 wqem->eseg.mss = rte_cpu_to_be_16
2875 (rte_pktmbuf_data_len(loc->mbuf));
2876 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
2877 loc->wqe_free) * MLX5_WQE_SIZE -
2878 MLX5_WQE_CSEG_SIZE -
2880 /* Limit the room for legacy MPW sessions for performance. */
2881 if (MLX5_TXOFF_CONFIG(MPW))
2882 room = RTE_MIN(room,
2883 RTE_MAX(txq->inlen_empw +
2884 sizeof(dseg->bcount) +
2885 (MLX5_TXOFF_CONFIG(VLAN) ?
2886 sizeof(struct rte_vlan_hdr) : 0),
2887 MLX5_MPW_INLINE_MAX_PACKETS *
2888 MLX5_WQE_DSEG_SIZE));
2889 /* Build WQE till we have space, packets and resources. */
2892 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
2893 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2896 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
2897 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0);
2898 MLX5_ASSERT((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
2900 * Some Tx offloads may cause an error if packet is not
2901 * long enough, check against assumed minimal length.
2903 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
2905 if (unlikely(!part))
2906 return MLX5_TXCMP_CODE_ERROR;
2908 * We have some successfully built
2909 * packet Data Segments to send.
2911 mlx5_tx_idone_empw(txq, loc, part,
2913 return MLX5_TXCMP_CODE_ERROR;
2915 /* Inline or not inline - that's the Question. */
2916 if (dlen > txq->inlen_empw ||
2917 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE)
2919 if (MLX5_TXOFF_CONFIG(MPW)) {
2920 if (dlen > txq->inlen_send)
2924 /* Open new inline MPW session. */
2925 tlen += sizeof(dseg->bcount);
2926 dseg->bcount = RTE_BE32(0);
2928 (dseg, sizeof(dseg->bcount));
2931 * No pointer and inline descriptor
2932 * intermix for legacy MPW sessions.
2934 if (wqem->dseg[0].bcount)
2938 tlen = sizeof(dseg->bcount) + dlen;
2940 /* Inline entire packet, optional VLAN insertion. */
2941 if (MLX5_TXOFF_CONFIG(VLAN) &&
2942 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2944 * The packet length must be checked in
2945 * mlx5_tx_able_to_empw() and packet
2946 * fits into inline length guaranteed.
2949 sizeof(struct rte_vlan_hdr)) <=
2951 tlen += sizeof(struct rte_vlan_hdr);
2954 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
2956 #ifdef MLX5_PMD_SOFT_COUNTERS
2957 /* Update sent data bytes counter. */
2958 slen += sizeof(struct rte_vlan_hdr);
2963 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
2966 if (!MLX5_TXOFF_CONFIG(MPW))
2967 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
2968 MLX5_ASSERT(room >= tlen);
2971 * Packet data are completely inline,
2972 * we can try to free the packet.
2974 if (likely(loc->pkts_sent == loc->mbuf_free)) {
2976 * All the packets from the burst beginning
2977 * are inline, we can free mbufs directly
2978 * from the origin array on tx_burst exit().
2984 * In order no to call rte_pktmbuf_free_seg() here,
2985 * in the most inner loop (that might be very
2986 * expensive) we just save the mbuf in elts.
2988 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2993 * No pointer and inline descriptor
2994 * intermix for legacy MPW sessions.
2996 if (MLX5_TXOFF_CONFIG(MPW) &&
2998 wqem->dseg[0].bcount == RTE_BE32(0))
3001 * Not inlinable VLAN packets are
3002 * proceeded outside of this routine.
3004 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
3005 if (MLX5_TXOFF_CONFIG(VLAN))
3006 MLX5_ASSERT(!(loc->mbuf->ol_flags &
3008 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3009 /* We have to store mbuf in elts.*/
3010 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3012 room -= MLX5_WQE_DSEG_SIZE;
3013 /* Ring buffer wraparound is checked at the loop end.*/
3016 #ifdef MLX5_PMD_SOFT_COUNTERS
3017 /* Update sent data bytes counter. */
3022 if (unlikely(!pkts_n || !loc->elts_free)) {
3024 * We have no resources/packets to
3025 * continue build descriptors.
3028 mlx5_tx_idone_empw(txq, loc, part,
3030 return MLX5_TXCMP_CODE_EXIT;
3032 loc->mbuf = *pkts++;
3033 if (likely(pkts_n > 1))
3034 rte_prefetch0(*pkts);
3035 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3037 * Unroll the completion code to avoid
3038 * returning variable value - it results in
3039 * unoptimized sequent checking in caller.
3041 if (ret == MLX5_TXCMP_CODE_MULTI) {
3043 mlx5_tx_idone_empw(txq, loc, part,
3045 if (unlikely(!loc->elts_free ||
3047 return MLX5_TXCMP_CODE_EXIT;
3048 return MLX5_TXCMP_CODE_MULTI;
3050 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3051 if (ret == MLX5_TXCMP_CODE_TSO) {
3053 mlx5_tx_idone_empw(txq, loc, part,
3055 if (unlikely(!loc->elts_free ||
3057 return MLX5_TXCMP_CODE_EXIT;
3058 return MLX5_TXCMP_CODE_TSO;
3060 if (ret == MLX5_TXCMP_CODE_SINGLE) {
3062 mlx5_tx_idone_empw(txq, loc, part,
3064 if (unlikely(!loc->elts_free ||
3066 return MLX5_TXCMP_CODE_EXIT;
3067 return MLX5_TXCMP_CODE_SINGLE;
3069 if (ret != MLX5_TXCMP_CODE_EMPW) {
3072 mlx5_tx_idone_empw(txq, loc, part,
3074 return MLX5_TXCMP_CODE_ERROR;
3076 /* Check if we have minimal room left. */
3078 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
3081 * Check whether packet parameters coincide
3082 * within assumed eMPW batch:
3083 * - check sum settings
3085 * - software parser settings
3086 * - packets length (legacy MPW only)
3087 * - scheduling is not required
3089 if (!mlx5_tx_match_empw(txq, &wqem->eseg,
3092 /* Packet attributes match, continue the same eMPW. */
3093 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3094 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3097 * We get here to close an existing eMPW
3098 * session and start the new one.
3100 MLX5_ASSERT(pkts_n);
3102 if (unlikely(!part))
3103 return MLX5_TXCMP_CODE_EXIT;
3104 mlx5_tx_idone_empw(txq, loc, part, slen, wqem, olx);
3105 if (unlikely(!loc->elts_free ||
3107 return MLX5_TXCMP_CODE_EXIT;
3108 /* Continue the loop with new eMPW session. */
3114 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
3115 * Data inlining and VLAN insertion are supported.
3117 static __rte_always_inline enum mlx5_txcmp_code
3118 mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
3119 struct rte_mbuf **__rte_restrict pkts,
3120 unsigned int pkts_n,
3121 struct mlx5_txq_local *__rte_restrict loc,
3125 * Subroutine is the part of mlx5_tx_burst_single()
3126 * and sends single-segment packet with SEND opcode.
3128 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3129 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3130 pkts += loc->pkts_sent + 1;
3131 pkts_n -= loc->pkts_sent;
3133 struct mlx5_wqe *__rte_restrict wqe;
3134 enum mlx5_txcmp_code ret;
3136 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3137 if (MLX5_TXOFF_CONFIG(TXPP)) {
3138 enum mlx5_txcmp_code wret;
3140 /* Generate WAIT for scheduling if requested. */
3141 wret = mlx5_tx_schedule_send(txq, loc, olx);
3142 if (wret == MLX5_TXCMP_CODE_EXIT)
3143 return MLX5_TXCMP_CODE_EXIT;
3144 if (wret == MLX5_TXCMP_CODE_ERROR)
3145 return MLX5_TXCMP_CODE_ERROR;
3147 if (MLX5_TXOFF_CONFIG(INLINE)) {
3148 unsigned int inlen, vlan = 0;
3150 inlen = rte_pktmbuf_data_len(loc->mbuf);
3151 if (MLX5_TXOFF_CONFIG(VLAN) &&
3152 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3153 vlan = sizeof(struct rte_vlan_hdr);
3157 * If inlining is enabled at configuration time
3158 * the limit must be not less than minimal size.
3159 * Otherwise we would do extra check for data
3160 * size to avoid crashes due to length overflow.
3162 MLX5_ASSERT(txq->inlen_send >=
3163 MLX5_ESEG_MIN_INLINE_SIZE);
3164 if (inlen <= txq->inlen_send) {
3165 unsigned int seg_n, wqe_n;
3167 rte_prefetch0(rte_pktmbuf_mtod
3168 (loc->mbuf, uint8_t *));
3169 /* Check against minimal length. */
3170 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3171 return MLX5_TXCMP_CODE_ERROR;
3172 if (loc->mbuf->ol_flags &
3173 PKT_TX_DYNF_NOINLINE) {
3175 * The hint flag not to inline packet
3176 * data is set. Check whether we can
3179 if ((!MLX5_TXOFF_CONFIG(EMPW) &&
3181 (MLX5_TXOFF_CONFIG(MPW) &&
3183 if (inlen <= txq->inlen_send)
3186 * The hardware requires the
3187 * minimal inline data header.
3189 goto single_min_inline;
3191 if (MLX5_TXOFF_CONFIG(VLAN) &&
3192 vlan && !txq->vlan_en) {
3194 * We must insert VLAN tag
3195 * by software means.
3197 goto single_part_inline;
3199 goto single_no_inline;
3203 * Completely inlined packet data WQE:
3204 * - Control Segment, SEND opcode
3205 * - Ethernet Segment, no VLAN insertion
3206 * - Data inlined, VLAN optionally inserted
3207 * - Alignment to MLX5_WSEG_SIZE
3208 * Have to estimate amount of WQEBBs
3210 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
3211 MLX5_ESEG_MIN_INLINE_SIZE +
3212 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3213 /* Check if there are enough WQEBBs. */
3214 wqe_n = (seg_n + 3) / 4;
3215 if (wqe_n > loc->wqe_free)
3216 return MLX5_TXCMP_CODE_EXIT;
3217 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3218 loc->wqe_last = wqe;
3219 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
3220 MLX5_OPCODE_SEND, olx);
3221 mlx5_tx_eseg_data(txq, loc, wqe,
3222 vlan, inlen, 0, olx);
3223 txq->wqe_ci += wqe_n;
3224 loc->wqe_free -= wqe_n;
3226 * Packet data are completely inlined,
3227 * free the packet immediately.
3229 rte_pktmbuf_free_seg(loc->mbuf);
3230 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
3231 MLX5_TXOFF_CONFIG(MPW)) &&
3234 * If minimal inlining is requested the eMPW
3235 * feature should be disabled due to data is
3236 * inlined into Ethernet Segment, which can
3237 * not contain inlined data for eMPW due to
3238 * segment shared for all packets.
3240 struct mlx5_wqe_dseg *__rte_restrict dseg;
3245 * The inline-mode settings require
3246 * to inline the specified amount of
3247 * data bytes to the Ethernet Segment.
3248 * We should check the free space in
3249 * WQE ring buffer to inline partially.
3252 MLX5_ASSERT(txq->inlen_send >= txq->inlen_mode);
3253 MLX5_ASSERT(inlen > txq->inlen_mode);
3254 MLX5_ASSERT(txq->inlen_mode >=
3255 MLX5_ESEG_MIN_INLINE_SIZE);
3257 * Check whether there are enough free WQEBBs:
3259 * - Ethernet Segment
3260 * - First Segment of inlined Ethernet data
3261 * - ... data continued ...
3262 * - Finishing Data Segment of pointer type
3264 ds = (MLX5_WQE_CSEG_SIZE +
3265 MLX5_WQE_ESEG_SIZE +
3266 MLX5_WQE_DSEG_SIZE +
3268 MLX5_ESEG_MIN_INLINE_SIZE +
3269 MLX5_WQE_DSEG_SIZE +
3270 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3271 if (loc->wqe_free < ((ds + 3) / 4))
3272 return MLX5_TXCMP_CODE_EXIT;
3274 * Build the ordinary SEND WQE:
3276 * - Ethernet Segment, inline inlen_mode bytes
3277 * - Data Segment of pointer type
3279 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3280 loc->wqe_last = wqe;
3281 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3282 MLX5_OPCODE_SEND, olx);
3283 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
3286 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
3287 txq->inlen_mode - vlan;
3288 inlen -= txq->inlen_mode;
3289 mlx5_tx_dseg_ptr(txq, loc, dseg,
3292 * WQE is built, update the loop parameters
3293 * and got to the next packet.
3295 txq->wqe_ci += (ds + 3) / 4;
3296 loc->wqe_free -= (ds + 3) / 4;
3297 /* We have to store mbuf in elts.*/
3298 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3299 txq->elts[txq->elts_head++ & txq->elts_m] =
3307 * Partially inlined packet data WQE, we have
3308 * some space in title WQEBB, we can fill it
3309 * with some packet data. It takes one WQEBB,
3310 * it is available, no extra space check:
3311 * - Control Segment, SEND opcode
3312 * - Ethernet Segment, no VLAN insertion
3313 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
3314 * - Data Segment, pointer type
3316 * We also get here if VLAN insertion is not
3317 * supported by HW, the inline is enabled.
3320 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3321 loc->wqe_last = wqe;
3322 mlx5_tx_cseg_init(txq, loc, wqe, 4,
3323 MLX5_OPCODE_SEND, olx);
3324 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
3325 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
3326 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
3328 * The length check is performed above, by
3329 * comparing with txq->inlen_send. We should
3330 * not get overflow here.
3332 MLX5_ASSERT(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
3333 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
3334 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
3338 /* We have to store mbuf in elts.*/
3339 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3340 txq->elts[txq->elts_head++ & txq->elts_m] =
3344 #ifdef MLX5_PMD_SOFT_COUNTERS
3345 /* Update sent data bytes counter. */
3346 txq->stats.obytes += vlan +
3347 rte_pktmbuf_data_len(loc->mbuf);
3351 * No inline at all, it means the CPU cycles saving
3352 * is prioritized at configuration, we should not
3353 * copy any packet data to WQE.
3355 * SEND WQE, one WQEBB:
3356 * - Control Segment, SEND opcode
3357 * - Ethernet Segment, optional VLAN, no inline
3358 * - Data Segment, pointer type
3361 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3362 loc->wqe_last = wqe;
3363 mlx5_tx_cseg_init(txq, loc, wqe, 3,
3364 MLX5_OPCODE_SEND, olx);
3365 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3367 (txq, loc, &wqe->dseg[0],
3368 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3369 rte_pktmbuf_data_len(loc->mbuf), olx);
3373 * We should not store mbuf pointer in elts
3374 * if no inlining is configured, this is done
3375 * by calling routine in a batch copy.
3377 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
3379 #ifdef MLX5_PMD_SOFT_COUNTERS
3380 /* Update sent data bytes counter. */
3381 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
3382 if (MLX5_TXOFF_CONFIG(VLAN) &&
3383 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3384 txq->stats.obytes +=
3385 sizeof(struct rte_vlan_hdr);
3390 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3391 return MLX5_TXCMP_CODE_EXIT;
3392 loc->mbuf = *pkts++;
3394 rte_prefetch0(*pkts);
3395 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3396 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
3402 static __rte_always_inline enum mlx5_txcmp_code
3403 mlx5_tx_burst_single(struct mlx5_txq_data *__rte_restrict txq,
3404 struct rte_mbuf **__rte_restrict pkts,
3405 unsigned int pkts_n,
3406 struct mlx5_txq_local *__rte_restrict loc,
3409 enum mlx5_txcmp_code ret;
3411 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
3412 if (ret == MLX5_TXCMP_CODE_SINGLE)
3414 MLX5_ASSERT(ret == MLX5_TXCMP_CODE_EMPW);
3416 /* Optimize for inline/no inline eMPW send. */
3417 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
3418 mlx5_tx_burst_empw_inline
3419 (txq, pkts, pkts_n, loc, olx) :
3420 mlx5_tx_burst_empw_simple
3421 (txq, pkts, pkts_n, loc, olx);
3422 if (ret != MLX5_TXCMP_CODE_SINGLE)
3424 /* The resources to send one packet should remain. */
3425 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3427 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
3428 MLX5_ASSERT(ret != MLX5_TXCMP_CODE_SINGLE);
3429 if (ret != MLX5_TXCMP_CODE_EMPW)
3431 /* The resources to send one packet should remain. */
3432 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3437 * DPDK Tx callback template. This is configured template used to generate
3438 * routines optimized for specified offload setup.
3439 * One of this generated functions is chosen at SQ configuration time.
3442 * Generic pointer to TX queue structure.
3444 * Packets to transmit.
3446 * Number of packets in array.
3448 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
3449 * values. Should be static to take compile time static configuration
3453 * Number of packets successfully transmitted (<= pkts_n).
3455 static __rte_always_inline uint16_t
3456 mlx5_tx_burst_tmpl(struct mlx5_txq_data *__rte_restrict txq,
3457 struct rte_mbuf **__rte_restrict pkts,
3461 struct mlx5_txq_local loc;
3462 enum mlx5_txcmp_code ret;
3465 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
3466 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
3467 if (unlikely(!pkts_n))
3469 if (MLX5_TXOFF_CONFIG(INLINE))
3473 loc.wqe_last = NULL;
3476 loc.pkts_loop = loc.pkts_sent;
3478 * Check if there are some CQEs, if any:
3479 * - process an encountered errors
3480 * - process the completed WQEs
3481 * - free related mbufs
3482 * - doorbell the NIC about processed CQEs
3484 rte_prefetch0(*(pkts + loc.pkts_sent));
3485 mlx5_tx_handle_completion(txq, olx);
3487 * Calculate the number of available resources - elts and WQEs.
3488 * There are two possible different scenarios:
3489 * - no data inlining into WQEs, one WQEBB may contains up to
3490 * four packets, in this case elts become scarce resource
3491 * - data inlining into WQEs, one packet may require multiple
3492 * WQEBBs, the WQEs become the limiting factor.
3494 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
3495 loc.elts_free = txq->elts_s -
3496 (uint16_t)(txq->elts_head - txq->elts_tail);
3497 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
3498 loc.wqe_free = txq->wqe_s -
3499 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
3500 if (unlikely(!loc.elts_free || !loc.wqe_free))
3504 * Fetch the packet from array. Usually this is the first
3505 * packet in series of multi/single segment packets.
3507 loc.mbuf = *(pkts + loc.pkts_sent);
3508 /* Dedicated branch for multi-segment packets. */
3509 if (MLX5_TXOFF_CONFIG(MULTI) &&
3510 unlikely(NB_SEGS(loc.mbuf) > 1)) {
3512 * Multi-segment packet encountered.
3513 * Hardware is able to process it only
3514 * with SEND/TSO opcodes, one packet
3515 * per WQE, do it in dedicated routine.
3518 MLX5_ASSERT(loc.pkts_sent >= loc.pkts_copy);
3519 part = loc.pkts_sent - loc.pkts_copy;
3520 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
3522 * There are some single-segment mbufs not
3523 * stored in elts. The mbufs must be in the
3524 * same order as WQEs, so we must copy the
3525 * mbufs to elts here, before the coming
3526 * multi-segment packet mbufs is appended.
3528 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
3530 loc.pkts_copy = loc.pkts_sent;
3532 MLX5_ASSERT(pkts_n > loc.pkts_sent);
3533 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
3534 if (!MLX5_TXOFF_CONFIG(INLINE))
3535 loc.pkts_copy = loc.pkts_sent;
3537 * These returned code checks are supposed
3538 * to be optimized out due to routine inlining.
3540 if (ret == MLX5_TXCMP_CODE_EXIT) {
3542 * The routine returns this code when
3543 * all packets are sent or there is no
3544 * enough resources to complete request.
3548 if (ret == MLX5_TXCMP_CODE_ERROR) {
3550 * The routine returns this code when some error
3551 * in the incoming packets format occurred.
3553 txq->stats.oerrors++;
3556 if (ret == MLX5_TXCMP_CODE_SINGLE) {
3558 * The single-segment packet was encountered
3559 * in the array, try to send it with the
3560 * best optimized way, possible engaging eMPW.
3562 goto enter_send_single;
3564 if (MLX5_TXOFF_CONFIG(TSO) &&
3565 ret == MLX5_TXCMP_CODE_TSO) {
3567 * The single-segment TSO packet was
3568 * encountered in the array.
3570 goto enter_send_tso;
3572 /* We must not get here. Something is going wrong. */
3574 txq->stats.oerrors++;
3577 /* Dedicated branch for single-segment TSO packets. */
3578 if (MLX5_TXOFF_CONFIG(TSO) &&
3579 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3581 * TSO might require special way for inlining
3582 * (dedicated parameters) and is sent with
3583 * MLX5_OPCODE_TSO opcode only, provide this
3584 * in dedicated branch.
3587 MLX5_ASSERT(NB_SEGS(loc.mbuf) == 1);
3588 MLX5_ASSERT(pkts_n > loc.pkts_sent);
3589 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
3591 * These returned code checks are supposed
3592 * to be optimized out due to routine inlining.
3594 if (ret == MLX5_TXCMP_CODE_EXIT)
3596 if (ret == MLX5_TXCMP_CODE_ERROR) {
3597 txq->stats.oerrors++;
3600 if (ret == MLX5_TXCMP_CODE_SINGLE)
3601 goto enter_send_single;
3602 if (MLX5_TXOFF_CONFIG(MULTI) &&
3603 ret == MLX5_TXCMP_CODE_MULTI) {
3605 * The multi-segment packet was
3606 * encountered in the array.
3608 goto enter_send_multi;
3610 /* We must not get here. Something is going wrong. */
3612 txq->stats.oerrors++;
3616 * The dedicated branch for the single-segment packets
3617 * without TSO. Often these ones can be sent using
3618 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
3619 * The routine builds the WQEs till it encounters
3620 * the TSO or multi-segment packet (in case if these
3621 * offloads are requested at SQ configuration time).
3624 MLX5_ASSERT(pkts_n > loc.pkts_sent);
3625 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
3627 * These returned code checks are supposed
3628 * to be optimized out due to routine inlining.
3630 if (ret == MLX5_TXCMP_CODE_EXIT)
3632 if (ret == MLX5_TXCMP_CODE_ERROR) {
3633 txq->stats.oerrors++;
3636 if (MLX5_TXOFF_CONFIG(MULTI) &&
3637 ret == MLX5_TXCMP_CODE_MULTI) {
3639 * The multi-segment packet was
3640 * encountered in the array.
3642 goto enter_send_multi;
3644 if (MLX5_TXOFF_CONFIG(TSO) &&
3645 ret == MLX5_TXCMP_CODE_TSO) {
3647 * The single-segment TSO packet was
3648 * encountered in the array.
3650 goto enter_send_tso;
3652 /* We must not get here. Something is going wrong. */
3654 txq->stats.oerrors++;
3658 * Main Tx loop is completed, do the rest:
3659 * - set completion request if thresholds are reached
3660 * - doorbell the hardware
3661 * - copy the rest of mbufs to elts (if any)
3663 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE) ||
3664 loc.pkts_sent >= loc.pkts_copy);
3665 /* Take a shortcut if nothing is sent. */
3666 if (unlikely(loc.pkts_sent == loc.pkts_loop))
3668 /* Request CQE generation if limits are reached. */
3669 mlx5_tx_request_completion(txq, &loc, olx);
3671 * Ring QP doorbell immediately after WQE building completion
3672 * to improve latencies. The pure software related data treatment
3673 * can be completed after doorbell. Tx CQEs for this SQ are
3674 * processed in this thread only by the polling.
3676 * The rdma core library can map doorbell register in two ways,
3677 * depending on the environment variable "MLX5_SHUT_UP_BF":
3679 * - as regular cached memory, the variable is either missing or
3680 * set to zero. This type of mapping may cause the significant
3681 * doorbell register writing latency and requires explicit memory
3682 * write barrier to mitigate this issue and prevent write combining.
3684 * - as non-cached memory, the variable is present and set to not "0"
3685 * value. This type of mapping may cause performance impact under
3686 * heavy loading conditions but the explicit write memory barrier is
3687 * not required and it may improve core performance.
3689 * - the legacy behaviour (prior 19.08 release) was to use some
3690 * heuristics to decide whether write memory barrier should
3691 * be performed. This behavior is supported with specifying
3692 * tx_db_nc=2, write barrier is skipped if application provides
3693 * the full recommended burst of packets, it supposes the next
3694 * packets are coming and the write barrier will be issued on
3695 * the next burst (after descriptor writing, at least).
3697 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
3698 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
3699 /* Not all of the mbufs may be stored into elts yet. */
3700 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
3701 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
3703 * There are some single-segment mbufs not stored in elts.
3704 * It can be only if the last packet was single-segment.
3705 * The copying is gathered into one place due to it is
3706 * a good opportunity to optimize that with SIMD.
3707 * Unfortunately if inlining is enabled the gaps in pointer
3708 * array may happen due to early freeing of the inlined mbufs.
3710 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
3711 loc.pkts_copy = loc.pkts_sent;
3713 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
3714 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
3715 if (pkts_n > loc.pkts_sent) {
3717 * If burst size is large there might be no enough CQE
3718 * fetched from completion queue and no enough resources
3719 * freed to send all the packets.
3724 #ifdef MLX5_PMD_SOFT_COUNTERS
3725 /* Increment sent packets counter. */
3726 txq->stats.opackets += loc.pkts_sent;
3728 if (MLX5_TXOFF_CONFIG(INLINE) && loc.mbuf_free)
3729 __mlx5_tx_free_mbuf(txq, pkts, loc.mbuf_free, olx);
3730 return loc.pkts_sent;
3733 #endif /* RTE_PMD_MLX5_TX_H_ */