1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
5 #include <rte_ethdev_driver.h>
6 #include <rte_interrupts.h>
8 #include <rte_malloc.h>
11 #include "mlx5_rxtx.h"
13 /* Destroy Event Queue Notification Channel. */
15 mlx5_txpp_destroy_eqn(struct mlx5_dev_ctx_shared *sh)
18 mlx5_glue->devx_destroy_event_channel(sh->txpp.echan);
19 sh->txpp.echan = NULL;
24 /* Create Event Queue Notification Channel. */
26 mlx5_txpp_create_eqn(struct mlx5_dev_ctx_shared *sh)
30 MLX5_ASSERT(!sh->txpp.echan);
31 lcore = (uint32_t)rte_lcore_to_cpu_id(-1);
32 if (mlx5_glue->devx_query_eqn(sh->ctx, lcore, &sh->txpp.eqn)) {
34 DRV_LOG(ERR, "Failed to query EQ number %d.", rte_errno);
38 sh->txpp.echan = mlx5_glue->devx_create_event_channel(sh->ctx,
39 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
40 if (!sh->txpp.echan) {
43 DRV_LOG(ERR, "Failed to create event channel %d.",
51 mlx5_txpp_destroy_clock_queue(struct mlx5_dev_ctx_shared *sh)
53 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
56 claim_zero(mlx5_devx_cmd_destroy(wq->sq));
58 claim_zero(mlx5_glue->devx_umem_dereg(wq->sq_umem));
60 rte_free((void *)(uintptr_t)wq->sq_buf);
62 claim_zero(mlx5_devx_cmd_destroy(wq->cq));
64 claim_zero(mlx5_glue->devx_umem_dereg(wq->cq_umem));
66 rte_free((void *)(uintptr_t)wq->cq_buf);
67 memset(wq, 0, sizeof(*wq));
71 mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh)
73 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
74 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->wqes;
75 struct mlx5_wqe_cseg *cs = &wqe->cseg;
76 uint32_t wqe_size, opcode, i;
79 /* For test purposes fill the WQ with SEND inline packet. */
81 wqe_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
83 2 * MLX5_WQE_ESEG_SIZE -
84 MLX5_ESEG_MIN_INLINE_SIZE,
86 opcode = MLX5_OPCODE_SEND;
88 wqe_size = MLX5_WSEG_SIZE;
89 opcode = MLX5_OPCODE_NOP;
91 cs->opcode = rte_cpu_to_be_32(opcode | 0); /* Index is ignored. */
92 cs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) |
93 (wqe_size / MLX5_WSEG_SIZE));
94 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS << MLX5_COMP_MODE_OFFSET);
95 cs->misc = RTE_BE32(0);
96 wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE);
98 struct mlx5_wqe_eseg *es = &wqe->eseg;
99 struct rte_ether_hdr *eth_hdr;
100 struct rte_ipv4_hdr *ip_hdr;
101 struct rte_udp_hdr *udp_hdr;
103 /* Build the inline test packet pattern. */
104 MLX5_ASSERT(wqe_size <= MLX5_WQE_SIZE_MAX);
105 MLX5_ASSERT(MLX5_TXPP_TEST_PKT_SIZE >=
106 (sizeof(struct rte_ether_hdr) +
107 sizeof(struct rte_ipv4_hdr)));
109 es->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
114 es->inline_hdr_sz = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE);
115 /* Build test packet L2 header (Ethernet). */
116 dst = (uint8_t *)&es->inline_data;
117 eth_hdr = (struct rte_ether_hdr *)dst;
118 rte_eth_random_addr(ð_hdr->d_addr.addr_bytes[0]);
119 rte_eth_random_addr(ð_hdr->s_addr.addr_bytes[0]);
120 eth_hdr->ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
121 /* Build test packet L3 header (IP v4). */
122 dst += sizeof(struct rte_ether_hdr);
123 ip_hdr = (struct rte_ipv4_hdr *)dst;
124 ip_hdr->version_ihl = RTE_IPV4_VHL_DEF;
125 ip_hdr->type_of_service = 0;
126 ip_hdr->fragment_offset = 0;
127 ip_hdr->time_to_live = 64;
128 ip_hdr->next_proto_id = IPPROTO_UDP;
129 ip_hdr->packet_id = 0;
130 ip_hdr->total_length = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE -
131 sizeof(struct rte_ether_hdr));
132 /* use RFC5735 / RFC2544 reserved network test addresses */
133 ip_hdr->src_addr = RTE_BE32((198U << 24) | (18 << 16) |
135 ip_hdr->dst_addr = RTE_BE32((198U << 24) | (18 << 16) |
137 if (MLX5_TXPP_TEST_PKT_SIZE <
138 (sizeof(struct rte_ether_hdr) +
139 sizeof(struct rte_ipv4_hdr) +
140 sizeof(struct rte_udp_hdr)))
142 /* Build test packet L4 header (UDP). */
143 dst += sizeof(struct rte_ipv4_hdr);
144 udp_hdr = (struct rte_udp_hdr *)dst;
145 udp_hdr->src_port = RTE_BE16(9); /* RFC863 Discard. */
146 udp_hdr->dst_port = RTE_BE16(9);
147 udp_hdr->dgram_len = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE -
148 sizeof(struct rte_ether_hdr) -
149 sizeof(struct rte_ipv4_hdr));
150 udp_hdr->dgram_cksum = 0;
151 /* Fill the test packet data. */
152 dst += sizeof(struct rte_udp_hdr);
153 for (i = sizeof(struct rte_ether_hdr) +
154 sizeof(struct rte_ipv4_hdr) +
155 sizeof(struct rte_udp_hdr);
156 i < MLX5_TXPP_TEST_PKT_SIZE; i++)
157 *dst++ = (uint8_t)(i & 0xFF);
160 /* Duplicate the pattern to the next WQEs. */
161 dst = (uint8_t *)(uintptr_t)wq->sq_buf;
162 for (i = 1; i < MLX5_TXPP_CLKQ_SIZE; i++) {
164 rte_memcpy(dst, (void *)(uintptr_t)wq->sq_buf, wqe_size);
168 /* Creates the Clock Queue for packet pacing, returns zero on success. */
170 mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)
172 struct mlx5_devx_create_sq_attr sq_attr = { 0 };
173 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
174 struct mlx5_devx_cq_attr cq_attr = { 0 };
175 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
176 size_t page_size = sysconf(_SC_PAGESIZE);
177 uint32_t umem_size, umem_dbrec;
180 /* Allocate memory buffer for CQEs and doorbell record. */
181 umem_size = sizeof(struct mlx5_cqe) * MLX5_TXPP_CLKQ_SIZE;
182 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
183 umem_size += MLX5_DBR_SIZE;
184 wq->cq_buf = rte_zmalloc_socket(__func__, umem_size,
185 page_size, sh->numa_node);
187 DRV_LOG(ERR, "Failed to allocate memory for Clock Queue.");
190 /* Register allocated buffer in user space with DevX. */
191 wq->cq_umem = mlx5_glue->devx_umem_reg(sh->ctx,
192 (void *)(uintptr_t)wq->cq_buf,
194 IBV_ACCESS_LOCAL_WRITE);
197 DRV_LOG(ERR, "Failed to register umem for Clock Queue.");
200 /* Create completion queue object for Clock Queue. */
201 cq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?
202 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;
203 cq_attr.use_first_only = 1;
204 cq_attr.overrun_ignore = 1;
205 cq_attr.uar_page_id = sh->tx_uar->page_id;
206 cq_attr.eqn = sh->txpp.eqn;
207 cq_attr.q_umem_valid = 1;
208 cq_attr.q_umem_offset = 0;
209 cq_attr.q_umem_id = wq->cq_umem->umem_id;
210 cq_attr.db_umem_valid = 1;
211 cq_attr.db_umem_offset = umem_dbrec;
212 cq_attr.db_umem_id = wq->cq_umem->umem_id;
213 cq_attr.log_cq_size = rte_log2_u32(MLX5_TXPP_CLKQ_SIZE);
214 cq_attr.log_page_size = rte_log2_u32(page_size);
215 wq->cq = mlx5_devx_cmd_create_cq(sh->ctx, &cq_attr);
218 DRV_LOG(ERR, "Failed to create CQ for Clock Queue.");
221 wq->cq_dbrec = RTE_PTR_ADD(wq->cq_buf, umem_dbrec);
223 /* Allocate memory buffer for Send Queue WQEs. */
225 wq->sq_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
227 2 * MLX5_WQE_ESEG_SIZE -
228 MLX5_ESEG_MIN_INLINE_SIZE,
229 MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
230 wq->sq_size *= MLX5_TXPP_CLKQ_SIZE;
232 wq->sq_size = MLX5_TXPP_CLKQ_SIZE;
234 /* There should not be WQE leftovers in the cyclic queue. */
235 MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));
236 umem_size = MLX5_WQE_SIZE * wq->sq_size;
237 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
238 umem_size += MLX5_DBR_SIZE;
239 wq->sq_buf = rte_zmalloc_socket(__func__, umem_size,
240 page_size, sh->numa_node);
242 DRV_LOG(ERR, "Failed to allocate memory for Clock Queue.");
246 /* Register allocated buffer in user space with DevX. */
247 wq->sq_umem = mlx5_glue->devx_umem_reg(sh->ctx,
248 (void *)(uintptr_t)wq->sq_buf,
250 IBV_ACCESS_LOCAL_WRITE);
253 DRV_LOG(ERR, "Failed to register umem for Clock Queue.");
256 /* Create send queue object for Clock Queue. */
258 sq_attr.tis_lst_sz = 1;
259 sq_attr.tis_num = sh->tis->id;
260 sq_attr.non_wire = 0;
261 sq_attr.static_sq_wq = 1;
263 sq_attr.non_wire = 1;
264 sq_attr.static_sq_wq = 1;
266 sq_attr.state = MLX5_SQC_STATE_RST;
267 sq_attr.cqn = wq->cq->id;
268 sq_attr.wq_attr.cd_slave = 1;
269 sq_attr.wq_attr.uar_page = sh->tx_uar->page_id;
270 sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
271 sq_attr.wq_attr.pd = sh->pdn;
272 sq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);
273 sq_attr.wq_attr.log_wq_sz = rte_log2_u32(wq->sq_size);
274 sq_attr.wq_attr.dbr_umem_valid = 1;
275 sq_attr.wq_attr.dbr_addr = umem_dbrec;
276 sq_attr.wq_attr.dbr_umem_id = wq->sq_umem->umem_id;
277 sq_attr.wq_attr.wq_umem_valid = 1;
278 sq_attr.wq_attr.wq_umem_id = wq->sq_umem->umem_id;
279 /* umem_offset must be zero for static_sq_wq queue. */
280 sq_attr.wq_attr.wq_umem_offset = 0;
281 wq->sq = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr);
284 DRV_LOG(ERR, "Failed to create SQ for Clock Queue.");
287 wq->sq_dbrec = RTE_PTR_ADD(wq->sq_buf, umem_dbrec +
288 MLX5_SND_DBR * sizeof(uint32_t));
289 /* Build the WQEs in the Send Queue before goto Ready state. */
290 mlx5_txpp_fill_wqe_clock_queue(sh);
291 /* Change queue state to ready. */
292 msq_attr.sq_state = MLX5_SQC_STATE_RST;
293 msq_attr.state = MLX5_SQC_STATE_RDY;
295 ret = mlx5_devx_cmd_modify_sq(wq->sq, &msq_attr);
297 DRV_LOG(ERR, "Failed to set SQ ready state Clock Queue.");
303 mlx5_txpp_destroy_clock_queue(sh);
309 * The routine initializes the packet pacing infrastructure:
310 * - allocates PP context
313 * - attaches rearm interrupt handler
315 * Returns 0 on success, negative otherwise
318 mlx5_txpp_create(struct mlx5_dev_ctx_shared *sh, struct mlx5_priv *priv)
320 int tx_pp = priv->config.tx_pp;
323 /* Store the requested pacing parameters. */
324 sh->txpp.tick = tx_pp >= 0 ? tx_pp : -tx_pp;
325 sh->txpp.test = !!(tx_pp < 0);
326 sh->txpp.skew = priv->config.tx_skew;
327 sh->txpp.freq = priv->config.hca_attr.dev_freq_khz;
328 ret = mlx5_txpp_create_eqn(sh);
331 ret = mlx5_txpp_create_clock_queue(sh);
336 mlx5_txpp_destroy_clock_queue(sh);
337 mlx5_txpp_destroy_eqn(sh);
346 * The routine destroys the packet pacing infrastructure:
347 * - detaches rearm interrupt handler
353 mlx5_txpp_destroy(struct mlx5_dev_ctx_shared *sh)
355 mlx5_txpp_destroy_clock_queue(sh);
356 mlx5_txpp_destroy_eqn(sh);
363 * Creates and starts packet pacing infrastructure on specified device.
366 * Pointer to Ethernet device structure.
369 * 0 on success, a negative errno value otherwise and rte_errno is set.
372 mlx5_txpp_start(struct rte_eth_dev *dev)
374 struct mlx5_priv *priv = dev->data->dev_private;
375 struct mlx5_dev_ctx_shared *sh = priv->sh;
379 if (!priv->config.tx_pp) {
380 /* Packet pacing is not requested for the device. */
381 MLX5_ASSERT(priv->txpp_en == 0);
385 /* Packet pacing is already enabled for the device. */
386 MLX5_ASSERT(sh->txpp.refcnt);
389 if (priv->config.tx_pp > 0) {
390 ret = rte_mbuf_dynflag_lookup
391 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
395 ret = pthread_mutex_lock(&sh->txpp.mutex);
398 if (sh->txpp.refcnt) {
402 err = mlx5_txpp_create(sh, priv);
404 MLX5_ASSERT(sh->txpp.tick);
411 ret = pthread_mutex_unlock(&sh->txpp.mutex);
418 * Stops and destroys packet pacing infrastructure on specified device.
421 * Pointer to Ethernet device structure.
424 * 0 on success, a negative errno value otherwise and rte_errno is set.
427 mlx5_txpp_stop(struct rte_eth_dev *dev)
429 struct mlx5_priv *priv = dev->data->dev_private;
430 struct mlx5_dev_ctx_shared *sh = priv->sh;
433 if (!priv->txpp_en) {
434 /* Packet pacing is already disabled for the device. */
438 ret = pthread_mutex_lock(&sh->txpp.mutex);
441 MLX5_ASSERT(sh->txpp.refcnt);
442 if (!sh->txpp.refcnt || --sh->txpp.refcnt)
444 /* No references any more, do actual destroy. */
445 mlx5_txpp_destroy(sh);
446 ret = pthread_mutex_unlock(&sh->txpp.mutex);