1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
8 #include <rte_ethdev_driver.h>
9 #include <rte_interrupts.h>
10 #include <rte_alarm.h>
11 #include <rte_malloc.h>
12 #include <rte_cycles.h>
13 #include <rte_eal_paging.h>
15 #include <mlx5_malloc.h>
18 #include "mlx5_rxtx.h"
19 #include "mlx5_common_os.h"
21 static_assert(sizeof(struct mlx5_cqe_ts) == sizeof(rte_int128_t),
22 "Wrong timestamp CQE part size");
24 static const char * const mlx5_txpp_stat_names[] = {
25 "tx_pp_missed_interrupt_errors", /* Missed service interrupt. */
26 "tx_pp_rearm_queue_errors", /* Rearm Queue errors. */
27 "tx_pp_clock_queue_errors", /* Clock Queue errors. */
28 "tx_pp_timestamp_past_errors", /* Timestamp in the past. */
29 "tx_pp_timestamp_future_errors", /* Timestamp in the distant future. */
30 "tx_pp_jitter", /* Timestamp jitter (one Clock Queue completion). */
31 "tx_pp_wander", /* Timestamp wander (half of Clock Queue CQEs). */
32 "tx_pp_sync_lost", /* Scheduling synchronization lost. */
35 /* Destroy Event Queue Notification Channel. */
37 mlx5_txpp_destroy_event_channel(struct mlx5_dev_ctx_shared *sh)
40 mlx5_os_devx_destroy_event_channel(sh->txpp.echan);
41 sh->txpp.echan = NULL;
45 /* Create Event Queue Notification Channel. */
47 mlx5_txpp_create_event_channel(struct mlx5_dev_ctx_shared *sh)
49 MLX5_ASSERT(!sh->txpp.echan);
50 sh->txpp.echan = mlx5_os_devx_create_event_channel(sh->ctx,
51 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
52 if (!sh->txpp.echan) {
54 DRV_LOG(ERR, "Failed to create event channel %d.", rte_errno);
61 mlx5_txpp_free_pp_index(struct mlx5_dev_ctx_shared *sh)
63 #ifdef HAVE_MLX5DV_PP_ALLOC
65 mlx5_glue->dv_free_pp(sh->txpp.pp);
71 DRV_LOG(ERR, "Freeing pacing index is not supported.");
75 /* Allocate Packet Pacing index from kernel via mlx5dv call. */
77 mlx5_txpp_alloc_pp_index(struct mlx5_dev_ctx_shared *sh)
79 #ifdef HAVE_MLX5DV_PP_ALLOC
80 uint32_t pp[MLX5_ST_SZ_DW(set_pp_rate_limit_context)];
83 MLX5_ASSERT(!sh->txpp.pp);
84 memset(&pp, 0, sizeof(pp));
85 rate = NS_PER_S / sh->txpp.tick;
86 if (rate * sh->txpp.tick != NS_PER_S)
87 DRV_LOG(WARNING, "Packet pacing frequency is not precise.");
91 len = RTE_MAX(MLX5_TXPP_TEST_PKT_SIZE,
92 (size_t)RTE_ETHER_MIN_LEN);
93 MLX5_SET(set_pp_rate_limit_context, &pp,
94 burst_upper_bound, len);
95 MLX5_SET(set_pp_rate_limit_context, &pp,
96 typical_packet_size, len);
97 /* Convert packets per second into kilobits. */
98 rate = (rate * len) / (1000ul / CHAR_BIT);
99 DRV_LOG(INFO, "Packet pacing rate set to %" PRIu64, rate);
101 MLX5_SET(set_pp_rate_limit_context, &pp, rate_limit, rate);
102 MLX5_SET(set_pp_rate_limit_context, &pp, rate_mode,
103 sh->txpp.test ? MLX5_DATA_RATE : MLX5_WQE_RATE);
104 sh->txpp.pp = mlx5_glue->dv_alloc_pp
105 (sh->ctx, sizeof(pp), &pp,
106 MLX5DV_PP_ALLOC_FLAGS_DEDICATED_INDEX);
107 if (sh->txpp.pp == NULL) {
108 DRV_LOG(ERR, "Failed to allocate packet pacing index.");
112 if (!((struct mlx5dv_pp *)sh->txpp.pp)->index) {
113 DRV_LOG(ERR, "Zero packet pacing index allocated.");
114 mlx5_txpp_free_pp_index(sh);
118 sh->txpp.pp_id = ((struct mlx5dv_pp *)(sh->txpp.pp))->index;
122 DRV_LOG(ERR, "Allocating pacing index is not supported.");
129 mlx5_txpp_destroy_send_queue(struct mlx5_txpp_wq *wq)
132 claim_zero(mlx5_devx_cmd_destroy(wq->sq));
134 claim_zero(mlx5_os_umem_dereg(wq->sq_umem));
136 mlx5_free((void *)(uintptr_t)wq->sq_buf);
138 claim_zero(mlx5_devx_cmd_destroy(wq->cq));
140 claim_zero(mlx5_os_umem_dereg(wq->cq_umem));
142 mlx5_free((void *)(uintptr_t)wq->cq_buf);
143 memset(wq, 0, sizeof(*wq));
147 mlx5_txpp_destroy_rearm_queue(struct mlx5_dev_ctx_shared *sh)
149 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
151 mlx5_txpp_destroy_send_queue(wq);
155 mlx5_txpp_destroy_clock_queue(struct mlx5_dev_ctx_shared *sh)
157 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
159 mlx5_txpp_destroy_send_queue(wq);
161 mlx5_free(sh->txpp.tsa);
167 mlx5_txpp_doorbell_rearm_queue(struct mlx5_dev_ctx_shared *sh, uint16_t ci)
169 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
177 cs.w32[0] = rte_cpu_to_be_32(rte_be_to_cpu_32
178 (wq->wqes[ci & (wq->sq_size - 1)].ctrl[0]) | (ci - 1) << 8);
179 cs.w32[1] = wq->wqes[ci & (wq->sq_size - 1)].ctrl[1];
180 /* Update SQ doorbell record with new SQ ci. */
181 rte_compiler_barrier();
182 *wq->sq_dbrec = rte_cpu_to_be_32(wq->sq_ci);
183 /* Make sure the doorbell record is updated. */
185 /* Write to doorbel register to start processing. */
186 reg_addr = mlx5_os_get_devx_uar_reg_addr(sh->tx_uar);
187 __mlx5_uar_write64_relaxed(cs.w64, reg_addr, NULL);
192 mlx5_txpp_fill_cqe_rearm_queue(struct mlx5_dev_ctx_shared *sh)
194 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
195 struct mlx5_cqe *cqe = (struct mlx5_cqe *)(uintptr_t)wq->cqes;
198 for (i = 0; i < MLX5_TXPP_REARM_CQ_SIZE; i++) {
199 cqe->op_own = (MLX5_CQE_INVALID << 4) | MLX5_CQE_OWNER_MASK;
205 mlx5_txpp_fill_wqe_rearm_queue(struct mlx5_dev_ctx_shared *sh)
207 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
208 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->wqes;
211 for (i = 0; i < wq->sq_size; i += 2) {
212 struct mlx5_wqe_cseg *cs;
213 struct mlx5_wqe_qseg *qs;
216 /* Build SEND_EN request with slave WQE index. */
217 cs = &wqe[i + 0].cseg;
218 cs->opcode = RTE_BE32(MLX5_OPCODE_SEND_EN | 0);
219 cs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) | 2);
220 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS <<
221 MLX5_COMP_MODE_OFFSET);
222 cs->misc = RTE_BE32(0);
223 qs = RTE_PTR_ADD(cs, sizeof(struct mlx5_wqe_cseg));
224 index = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM) &
225 ((1 << MLX5_WQ_INDEX_WIDTH) - 1);
226 qs->max_index = rte_cpu_to_be_32(index);
227 qs->qpn_cqn = rte_cpu_to_be_32(sh->txpp.clock_queue.sq->id);
228 /* Build WAIT request with slave CQE index. */
229 cs = &wqe[i + 1].cseg;
230 cs->opcode = RTE_BE32(MLX5_OPCODE_WAIT | 0);
231 cs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) | 2);
232 cs->flags = RTE_BE32(MLX5_COMP_ONLY_ERR <<
233 MLX5_COMP_MODE_OFFSET);
234 cs->misc = RTE_BE32(0);
235 qs = RTE_PTR_ADD(cs, sizeof(struct mlx5_wqe_cseg));
236 index = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM / 2) &
237 ((1 << MLX5_CQ_INDEX_WIDTH) - 1);
238 qs->max_index = rte_cpu_to_be_32(index);
239 qs->qpn_cqn = rte_cpu_to_be_32(sh->txpp.clock_queue.cq->id);
243 /* Creates the Rearm Queue to fire the requests to Clock Queue in realtime. */
245 mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)
247 struct mlx5_devx_create_sq_attr sq_attr = { 0 };
248 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
249 struct mlx5_devx_cq_attr cq_attr = { 0 };
250 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
252 uint32_t umem_size, umem_dbrec;
255 page_size = rte_mem_page_size();
256 if (page_size == (size_t)-1) {
257 DRV_LOG(ERR, "Failed to get mem page size");
260 /* Allocate memory buffer for CQEs and doorbell record. */
261 umem_size = sizeof(struct mlx5_cqe) * MLX5_TXPP_REARM_CQ_SIZE;
262 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
263 umem_size += MLX5_DBR_SIZE;
264 wq->cq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,
265 page_size, sh->numa_node);
267 DRV_LOG(ERR, "Failed to allocate memory for Rearm Queue.");
270 /* Register allocated buffer in user space with DevX. */
271 wq->cq_umem = mlx5_os_umem_reg(sh->ctx,
272 (void *)(uintptr_t)wq->cq_buf,
274 IBV_ACCESS_LOCAL_WRITE);
277 DRV_LOG(ERR, "Failed to register umem for Rearm Queue.");
280 /* Create completion queue object for Rearm Queue. */
281 cq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?
282 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;
283 cq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar);
284 cq_attr.eqn = sh->eqn;
285 cq_attr.q_umem_valid = 1;
286 cq_attr.q_umem_offset = 0;
287 cq_attr.q_umem_id = mlx5_os_get_umem_id(wq->cq_umem);
288 cq_attr.db_umem_valid = 1;
289 cq_attr.db_umem_offset = umem_dbrec;
290 cq_attr.db_umem_id = mlx5_os_get_umem_id(wq->cq_umem);
291 cq_attr.log_cq_size = rte_log2_u32(MLX5_TXPP_REARM_CQ_SIZE);
292 cq_attr.log_page_size = rte_log2_u32(page_size);
293 wq->cq = mlx5_devx_cmd_create_cq(sh->ctx, &cq_attr);
296 DRV_LOG(ERR, "Failed to create CQ for Rearm Queue.");
299 wq->cq_dbrec = RTE_PTR_ADD(wq->cq_buf, umem_dbrec);
302 /* Mark all CQEs initially as invalid. */
303 mlx5_txpp_fill_cqe_rearm_queue(sh);
305 * Allocate memory buffer for Send Queue WQEs.
306 * There should be no WQE leftovers in the cyclic queue.
308 wq->sq_size = MLX5_TXPP_REARM_SQ_SIZE;
309 MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));
310 umem_size = MLX5_WQE_SIZE * wq->sq_size;
311 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
312 umem_size += MLX5_DBR_SIZE;
313 wq->sq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,
314 page_size, sh->numa_node);
316 DRV_LOG(ERR, "Failed to allocate memory for Rearm Queue.");
320 /* Register allocated buffer in user space with DevX. */
321 wq->sq_umem = mlx5_os_umem_reg(sh->ctx,
322 (void *)(uintptr_t)wq->sq_buf,
324 IBV_ACCESS_LOCAL_WRITE);
327 DRV_LOG(ERR, "Failed to register umem for Rearm Queue.");
330 /* Create send queue object for Rearm Queue. */
331 sq_attr.state = MLX5_SQC_STATE_RST;
332 sq_attr.tis_lst_sz = 1;
333 sq_attr.tis_num = sh->tis->id;
334 sq_attr.cqn = wq->cq->id;
335 sq_attr.cd_master = 1;
336 sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);
337 sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
338 sq_attr.wq_attr.pd = sh->pdn;
339 sq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);
340 sq_attr.wq_attr.log_wq_sz = rte_log2_u32(wq->sq_size);
341 sq_attr.wq_attr.dbr_umem_valid = 1;
342 sq_attr.wq_attr.dbr_addr = umem_dbrec;
343 sq_attr.wq_attr.dbr_umem_id = mlx5_os_get_umem_id(wq->sq_umem);
344 sq_attr.wq_attr.wq_umem_valid = 1;
345 sq_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(wq->sq_umem);
346 sq_attr.wq_attr.wq_umem_offset = 0;
347 wq->sq = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr);
350 DRV_LOG(ERR, "Failed to create SQ for Rearm Queue.");
353 wq->sq_dbrec = RTE_PTR_ADD(wq->sq_buf, umem_dbrec +
354 MLX5_SND_DBR * sizeof(uint32_t));
355 /* Build the WQEs in the Send Queue before goto Ready state. */
356 mlx5_txpp_fill_wqe_rearm_queue(sh);
357 /* Change queue state to ready. */
358 msq_attr.sq_state = MLX5_SQC_STATE_RST;
359 msq_attr.state = MLX5_SQC_STATE_RDY;
360 ret = mlx5_devx_cmd_modify_sq(wq->sq, &msq_attr);
362 DRV_LOG(ERR, "Failed to set SQ ready state Rearm Queue.");
368 mlx5_txpp_destroy_rearm_queue(sh);
374 mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh)
376 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
377 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->wqes;
378 struct mlx5_wqe_cseg *cs = &wqe->cseg;
379 uint32_t wqe_size, opcode, i;
382 /* For test purposes fill the WQ with SEND inline packet. */
384 wqe_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
386 2 * MLX5_WQE_ESEG_SIZE -
387 MLX5_ESEG_MIN_INLINE_SIZE,
389 opcode = MLX5_OPCODE_SEND;
391 wqe_size = MLX5_WSEG_SIZE;
392 opcode = MLX5_OPCODE_NOP;
394 cs->opcode = rte_cpu_to_be_32(opcode | 0); /* Index is ignored. */
395 cs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) |
396 (wqe_size / MLX5_WSEG_SIZE));
397 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS << MLX5_COMP_MODE_OFFSET);
398 cs->misc = RTE_BE32(0);
399 wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE);
401 struct mlx5_wqe_eseg *es = &wqe->eseg;
402 struct rte_ether_hdr *eth_hdr;
403 struct rte_ipv4_hdr *ip_hdr;
404 struct rte_udp_hdr *udp_hdr;
406 /* Build the inline test packet pattern. */
407 MLX5_ASSERT(wqe_size <= MLX5_WQE_SIZE_MAX);
408 MLX5_ASSERT(MLX5_TXPP_TEST_PKT_SIZE >=
409 (sizeof(struct rte_ether_hdr) +
410 sizeof(struct rte_ipv4_hdr)));
412 es->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
417 es->inline_hdr_sz = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE);
418 /* Build test packet L2 header (Ethernet). */
419 dst = (uint8_t *)&es->inline_data;
420 eth_hdr = (struct rte_ether_hdr *)dst;
421 rte_eth_random_addr(ð_hdr->d_addr.addr_bytes[0]);
422 rte_eth_random_addr(ð_hdr->s_addr.addr_bytes[0]);
423 eth_hdr->ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
424 /* Build test packet L3 header (IP v4). */
425 dst += sizeof(struct rte_ether_hdr);
426 ip_hdr = (struct rte_ipv4_hdr *)dst;
427 ip_hdr->version_ihl = RTE_IPV4_VHL_DEF;
428 ip_hdr->type_of_service = 0;
429 ip_hdr->fragment_offset = 0;
430 ip_hdr->time_to_live = 64;
431 ip_hdr->next_proto_id = IPPROTO_UDP;
432 ip_hdr->packet_id = 0;
433 ip_hdr->total_length = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE -
434 sizeof(struct rte_ether_hdr));
435 /* use RFC5735 / RFC2544 reserved network test addresses */
436 ip_hdr->src_addr = RTE_BE32((198U << 24) | (18 << 16) |
438 ip_hdr->dst_addr = RTE_BE32((198U << 24) | (18 << 16) |
440 if (MLX5_TXPP_TEST_PKT_SIZE <
441 (sizeof(struct rte_ether_hdr) +
442 sizeof(struct rte_ipv4_hdr) +
443 sizeof(struct rte_udp_hdr)))
445 /* Build test packet L4 header (UDP). */
446 dst += sizeof(struct rte_ipv4_hdr);
447 udp_hdr = (struct rte_udp_hdr *)dst;
448 udp_hdr->src_port = RTE_BE16(9); /* RFC863 Discard. */
449 udp_hdr->dst_port = RTE_BE16(9);
450 udp_hdr->dgram_len = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE -
451 sizeof(struct rte_ether_hdr) -
452 sizeof(struct rte_ipv4_hdr));
453 udp_hdr->dgram_cksum = 0;
454 /* Fill the test packet data. */
455 dst += sizeof(struct rte_udp_hdr);
456 for (i = sizeof(struct rte_ether_hdr) +
457 sizeof(struct rte_ipv4_hdr) +
458 sizeof(struct rte_udp_hdr);
459 i < MLX5_TXPP_TEST_PKT_SIZE; i++)
460 *dst++ = (uint8_t)(i & 0xFF);
463 /* Duplicate the pattern to the next WQEs. */
464 dst = (uint8_t *)(uintptr_t)wq->sq_buf;
465 for (i = 1; i < MLX5_TXPP_CLKQ_SIZE; i++) {
467 rte_memcpy(dst, (void *)(uintptr_t)wq->sq_buf, wqe_size);
471 /* Creates the Clock Queue for packet pacing, returns zero on success. */
473 mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)
475 struct mlx5_devx_create_sq_attr sq_attr = { 0 };
476 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
477 struct mlx5_devx_cq_attr cq_attr = { 0 };
478 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
480 uint32_t umem_size, umem_dbrec;
483 page_size = rte_mem_page_size();
484 if (page_size == (size_t)-1) {
485 DRV_LOG(ERR, "Failed to get mem page size");
488 sh->txpp.tsa = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
489 MLX5_TXPP_REARM_SQ_SIZE *
490 sizeof(struct mlx5_txpp_ts),
493 DRV_LOG(ERR, "Failed to allocate memory for CQ stats.");
498 /* Allocate memory buffer for CQEs and doorbell record. */
499 umem_size = sizeof(struct mlx5_cqe) * MLX5_TXPP_CLKQ_SIZE;
500 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
501 umem_size += MLX5_DBR_SIZE;
502 wq->cq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,
503 page_size, sh->numa_node);
505 DRV_LOG(ERR, "Failed to allocate memory for Clock Queue.");
508 /* Register allocated buffer in user space with DevX. */
509 wq->cq_umem = mlx5_os_umem_reg(sh->ctx,
510 (void *)(uintptr_t)wq->cq_buf,
512 IBV_ACCESS_LOCAL_WRITE);
515 DRV_LOG(ERR, "Failed to register umem for Clock Queue.");
518 /* Create completion queue object for Clock Queue. */
519 cq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?
520 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;
521 cq_attr.use_first_only = 1;
522 cq_attr.overrun_ignore = 1;
523 cq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar);
524 cq_attr.eqn = sh->eqn;
525 cq_attr.q_umem_valid = 1;
526 cq_attr.q_umem_offset = 0;
527 cq_attr.q_umem_id = mlx5_os_get_umem_id(wq->cq_umem);
528 cq_attr.db_umem_valid = 1;
529 cq_attr.db_umem_offset = umem_dbrec;
530 cq_attr.db_umem_id = mlx5_os_get_umem_id(wq->cq_umem);
531 cq_attr.log_cq_size = rte_log2_u32(MLX5_TXPP_CLKQ_SIZE);
532 cq_attr.log_page_size = rte_log2_u32(page_size);
533 wq->cq = mlx5_devx_cmd_create_cq(sh->ctx, &cq_attr);
536 DRV_LOG(ERR, "Failed to create CQ for Clock Queue.");
539 wq->cq_dbrec = RTE_PTR_ADD(wq->cq_buf, umem_dbrec);
541 /* Allocate memory buffer for Send Queue WQEs. */
543 wq->sq_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
545 2 * MLX5_WQE_ESEG_SIZE -
546 MLX5_ESEG_MIN_INLINE_SIZE,
547 MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
548 wq->sq_size *= MLX5_TXPP_CLKQ_SIZE;
550 wq->sq_size = MLX5_TXPP_CLKQ_SIZE;
552 /* There should not be WQE leftovers in the cyclic queue. */
553 MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));
554 umem_size = MLX5_WQE_SIZE * wq->sq_size;
555 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
556 umem_size += MLX5_DBR_SIZE;
557 wq->sq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,
558 page_size, sh->numa_node);
560 DRV_LOG(ERR, "Failed to allocate memory for Clock Queue.");
564 /* Register allocated buffer in user space with DevX. */
565 wq->sq_umem = mlx5_os_umem_reg(sh->ctx,
566 (void *)(uintptr_t)wq->sq_buf,
568 IBV_ACCESS_LOCAL_WRITE);
571 DRV_LOG(ERR, "Failed to register umem for Clock Queue.");
574 /* Create send queue object for Clock Queue. */
576 sq_attr.tis_lst_sz = 1;
577 sq_attr.tis_num = sh->tis->id;
578 sq_attr.non_wire = 0;
579 sq_attr.static_sq_wq = 1;
581 sq_attr.non_wire = 1;
582 sq_attr.static_sq_wq = 1;
584 sq_attr.state = MLX5_SQC_STATE_RST;
585 sq_attr.cqn = wq->cq->id;
586 sq_attr.packet_pacing_rate_limit_index = sh->txpp.pp_id;
587 sq_attr.wq_attr.cd_slave = 1;
588 sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);
589 sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
590 sq_attr.wq_attr.pd = sh->pdn;
591 sq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);
592 sq_attr.wq_attr.log_wq_sz = rte_log2_u32(wq->sq_size);
593 sq_attr.wq_attr.dbr_umem_valid = 1;
594 sq_attr.wq_attr.dbr_addr = umem_dbrec;
595 sq_attr.wq_attr.dbr_umem_id = mlx5_os_get_umem_id(wq->sq_umem);
596 sq_attr.wq_attr.wq_umem_valid = 1;
597 sq_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(wq->sq_umem);
598 /* umem_offset must be zero for static_sq_wq queue. */
599 sq_attr.wq_attr.wq_umem_offset = 0;
600 wq->sq = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr);
603 DRV_LOG(ERR, "Failed to create SQ for Clock Queue.");
606 wq->sq_dbrec = RTE_PTR_ADD(wq->sq_buf, umem_dbrec +
607 MLX5_SND_DBR * sizeof(uint32_t));
608 /* Build the WQEs in the Send Queue before goto Ready state. */
609 mlx5_txpp_fill_wqe_clock_queue(sh);
610 /* Change queue state to ready. */
611 msq_attr.sq_state = MLX5_SQC_STATE_RST;
612 msq_attr.state = MLX5_SQC_STATE_RDY;
614 ret = mlx5_devx_cmd_modify_sq(wq->sq, &msq_attr);
616 DRV_LOG(ERR, "Failed to set SQ ready state Clock Queue.");
622 mlx5_txpp_destroy_clock_queue(sh);
627 /* Enable notification from the Rearm Queue CQ. */
629 mlx5_txpp_cq_arm(struct mlx5_dev_ctx_shared *sh)
633 struct mlx5_txpp_wq *aq = &sh->txpp.rearm_queue;
634 uint32_t arm_sn = aq->arm_sn << MLX5_CQ_SQN_OFFSET;
635 uint32_t db_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | aq->cq_ci;
636 uint64_t db_be = rte_cpu_to_be_64(((uint64_t)db_hi << 32) | aq->cq->id);
637 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
638 uint32_t *addr = RTE_PTR_ADD(base_addr, MLX5_CQ_DOORBELL);
640 rte_compiler_barrier();
641 aq->cq_dbrec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(db_hi);
644 *(uint64_t *)addr = db_be;
646 *(uint32_t *)addr = db_be;
648 *((uint32_t *)addr + 1) = db_be >> 32;
653 #if defined(RTE_ARCH_X86_64)
655 mlx5_atomic128_compare_exchange(rte_int128_t *dst,
657 const rte_int128_t *src)
661 asm volatile (MPLOCKED
664 : [dst] "=m" (dst->val[0]),
680 mlx5_atomic_read_cqe(rte_int128_t *from, rte_int128_t *ts)
683 * The only CQE of Clock Queue is being continuously
684 * update by hardware with soecified rate. We have to
685 * read timestump and WQE completion index atomically.
687 #if defined(RTE_ARCH_X86_64)
690 memset(&src, 0, sizeof(src));
692 /* if (*from == *ts) *from = *src else *ts = *from; */
693 mlx5_atomic128_compare_exchange(from, ts, &src);
695 uint64_t *cqe = (uint64_t *)from;
698 * Power architecture does not support 16B compare-and-swap.
699 * ARM implements it in software, code below is more relevant.
705 rte_compiler_barrier();
706 tm = __atomic_load_n(cqe + 0, __ATOMIC_RELAXED);
707 op = __atomic_load_n(cqe + 1, __ATOMIC_RELAXED);
708 rte_compiler_barrier();
709 if (tm != __atomic_load_n(cqe + 0, __ATOMIC_RELAXED))
711 if (op != __atomic_load_n(cqe + 1, __ATOMIC_RELAXED))
721 /* Stores timestamp in the cache structure to share data with datapath. */
723 mlx5_txpp_cache_timestamp(struct mlx5_dev_ctx_shared *sh,
724 uint64_t ts, uint64_t ci)
726 ci = ci << (64 - MLX5_CQ_INDEX_WIDTH);
727 ci |= (ts << MLX5_CQ_INDEX_WIDTH) >> MLX5_CQ_INDEX_WIDTH;
728 rte_compiler_barrier();
729 __atomic_store_n(&sh->txpp.ts.ts, ts, __ATOMIC_RELAXED);
730 __atomic_store_n(&sh->txpp.ts.ci_ts, ci, __ATOMIC_RELAXED);
734 /* Reads timestamp from Clock Queue CQE and stores in the cache. */
736 mlx5_txpp_update_timestamp(struct mlx5_dev_ctx_shared *sh)
738 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
739 struct mlx5_cqe *cqe = (struct mlx5_cqe *)(uintptr_t)wq->cqes;
742 struct mlx5_cqe_ts cts;
747 mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128);
748 if (to.cts.op_own >> 4) {
749 DRV_LOG(DEBUG, "Clock Queue error sync lost.");
750 __atomic_fetch_add(&sh->txpp.err_clock_queue,
751 1, __ATOMIC_RELAXED);
752 sh->txpp.sync_lost = 1;
755 ci = rte_be_to_cpu_16(to.cts.wqe_counter);
756 ts = rte_be_to_cpu_64(to.cts.timestamp);
757 ts = mlx5_txpp_convert_rx_ts(sh, ts);
758 wq->cq_ci += (ci - wq->sq_ci) & UINT16_MAX;
760 mlx5_txpp_cache_timestamp(sh, ts, wq->cq_ci);
763 /* Waits for the first completion on Clock Queue to init timestamp. */
765 mlx5_txpp_init_timestamp(struct mlx5_dev_ctx_shared *sh)
767 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
772 for (wait = 0; wait < MLX5_TXPP_WAIT_INIT_TS; wait++) {
773 mlx5_txpp_update_timestamp(sh);
776 /* Wait one millisecond and try again. */
777 rte_delay_us_sleep(US_PER_S / MS_PER_S);
779 DRV_LOG(ERR, "Unable to initialize timestamp.");
780 sh->txpp.sync_lost = 1;
783 #ifdef HAVE_IBV_DEVX_EVENT
784 /* Gather statistics for timestamp from Clock Queue CQE. */
786 mlx5_txpp_gather_timestamp(struct mlx5_dev_ctx_shared *sh)
788 /* Check whether we have a valid timestamp. */
789 if (!sh->txpp.clock_queue.sq_ci && !sh->txpp.ts_n)
791 MLX5_ASSERT(sh->txpp.ts_p < MLX5_TXPP_REARM_SQ_SIZE);
792 __atomic_store_n(&sh->txpp.tsa[sh->txpp.ts_p].ts,
793 sh->txpp.ts.ts, __ATOMIC_RELAXED);
794 __atomic_store_n(&sh->txpp.tsa[sh->txpp.ts_p].ci_ts,
795 sh->txpp.ts.ci_ts, __ATOMIC_RELAXED);
796 if (++sh->txpp.ts_p >= MLX5_TXPP_REARM_SQ_SIZE)
798 if (sh->txpp.ts_n < MLX5_TXPP_REARM_SQ_SIZE)
802 /* Handles Rearm Queue completions in periodic service. */
803 static __rte_always_inline void
804 mlx5_txpp_handle_rearm_queue(struct mlx5_dev_ctx_shared *sh)
806 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
807 uint32_t cq_ci = wq->cq_ci;
812 volatile struct mlx5_cqe *cqe;
814 cqe = &wq->cqes[cq_ci & (MLX5_TXPP_REARM_CQ_SIZE - 1)];
815 ret = check_cqe(cqe, MLX5_TXPP_REARM_CQ_SIZE, cq_ci);
817 case MLX5_CQE_STATUS_ERR:
821 case MLX5_CQE_STATUS_SW_OWN:
825 case MLX5_CQE_STATUS_HW_OWN:
831 } while (ret != MLX5_CQE_STATUS_HW_OWN);
832 if (likely(cq_ci != wq->cq_ci)) {
833 /* Check whether we have missed interrupts. */
834 if (cq_ci - wq->cq_ci != 1) {
835 DRV_LOG(DEBUG, "Rearm Queue missed interrupt.");
836 __atomic_fetch_add(&sh->txpp.err_miss_int,
837 1, __ATOMIC_RELAXED);
838 /* Check sync lost on wqe index. */
839 if (cq_ci - wq->cq_ci >=
840 (((1UL << MLX5_WQ_INDEX_WIDTH) /
841 MLX5_TXPP_REARM) - 1))
844 /* Update doorbell record to notify hardware. */
845 rte_compiler_barrier();
846 *wq->cq_dbrec = rte_cpu_to_be_32(cq_ci);
849 /* Fire new requests to Rearm Queue. */
851 DRV_LOG(DEBUG, "Rearm Queue error sync lost.");
852 __atomic_fetch_add(&sh->txpp.err_rearm_queue,
853 1, __ATOMIC_RELAXED);
854 sh->txpp.sync_lost = 1;
859 /* Handles Clock Queue completions in periodic service. */
860 static __rte_always_inline void
861 mlx5_txpp_handle_clock_queue(struct mlx5_dev_ctx_shared *sh)
863 mlx5_txpp_update_timestamp(sh);
864 mlx5_txpp_gather_timestamp(sh);
868 /* Invoked periodically on Rearm Queue completions. */
870 mlx5_txpp_interrupt_handler(void *cb_arg)
872 #ifndef HAVE_IBV_DEVX_EVENT
873 RTE_SET_USED(cb_arg);
876 struct mlx5_dev_ctx_shared *sh = cb_arg;
878 struct mlx5dv_devx_async_event_hdr event_resp;
879 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
882 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
883 /* Process events in the loop. Only rearm completions are expected. */
884 while (mlx5_glue->devx_get_event
888 (ssize_t)sizeof(out.event_resp.cookie)) {
889 mlx5_txpp_handle_rearm_queue(sh);
890 mlx5_txpp_handle_clock_queue(sh);
891 mlx5_txpp_cq_arm(sh);
892 mlx5_txpp_doorbell_rearm_queue
893 (sh, sh->txpp.rearm_queue.sq_ci - 1);
895 #endif /* HAVE_IBV_DEVX_ASYNC */
899 mlx5_txpp_stop_service(struct mlx5_dev_ctx_shared *sh)
901 if (!sh->txpp.intr_handle.fd)
903 mlx5_intr_callback_unregister(&sh->txpp.intr_handle,
904 mlx5_txpp_interrupt_handler, sh);
905 sh->txpp.intr_handle.fd = 0;
908 /* Attach interrupt handler and fires first request to Rearm Queue. */
910 mlx5_txpp_start_service(struct mlx5_dev_ctx_shared *sh)
912 uint16_t event_nums[1] = {0};
916 sh->txpp.err_miss_int = 0;
917 sh->txpp.err_rearm_queue = 0;
918 sh->txpp.err_clock_queue = 0;
919 sh->txpp.err_ts_past = 0;
920 sh->txpp.err_ts_future = 0;
921 /* Attach interrupt handler to process Rearm Queue completions. */
922 fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan);
923 ret = mlx5_os_set_nonblock_channel_fd(fd);
925 DRV_LOG(ERR, "Failed to change event channel FD.");
929 memset(&sh->txpp.intr_handle, 0, sizeof(sh->txpp.intr_handle));
930 fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan);
931 sh->txpp.intr_handle.fd = fd;
932 sh->txpp.intr_handle.type = RTE_INTR_HANDLE_EXT;
933 if (rte_intr_callback_register(&sh->txpp.intr_handle,
934 mlx5_txpp_interrupt_handler, sh)) {
935 sh->txpp.intr_handle.fd = 0;
936 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
939 /* Subscribe CQ event to the event channel controlled by the driver. */
940 ret = mlx5_os_devx_subscribe_devx_event(sh->txpp.echan,
941 sh->txpp.rearm_queue.cq->obj,
945 DRV_LOG(ERR, "Failed to subscribe CQE event.");
949 /* Enable interrupts in the CQ. */
950 mlx5_txpp_cq_arm(sh);
951 /* Fire the first request on Rearm Queue. */
952 mlx5_txpp_doorbell_rearm_queue(sh, sh->txpp.rearm_queue.sq_size - 1);
953 mlx5_txpp_init_timestamp(sh);
958 * The routine initializes the packet pacing infrastructure:
959 * - allocates PP context
962 * - attaches rearm interrupt handler
963 * - starts Clock Queue
965 * Returns 0 on success, negative otherwise
968 mlx5_txpp_create(struct mlx5_dev_ctx_shared *sh, struct mlx5_priv *priv)
970 int tx_pp = priv->config.tx_pp;
973 /* Store the requested pacing parameters. */
974 sh->txpp.tick = tx_pp >= 0 ? tx_pp : -tx_pp;
975 sh->txpp.test = !!(tx_pp < 0);
976 sh->txpp.skew = priv->config.tx_skew;
977 sh->txpp.freq = priv->config.hca_attr.dev_freq_khz;
978 ret = mlx5_txpp_create_event_channel(sh);
981 ret = mlx5_txpp_alloc_pp_index(sh);
984 ret = mlx5_txpp_create_clock_queue(sh);
987 ret = mlx5_txpp_create_rearm_queue(sh);
990 ret = mlx5_txpp_start_service(sh);
995 mlx5_txpp_stop_service(sh);
996 mlx5_txpp_destroy_rearm_queue(sh);
997 mlx5_txpp_destroy_clock_queue(sh);
998 mlx5_txpp_free_pp_index(sh);
999 mlx5_txpp_destroy_event_channel(sh);
1008 * The routine destroys the packet pacing infrastructure:
1009 * - detaches rearm interrupt handler
1015 mlx5_txpp_destroy(struct mlx5_dev_ctx_shared *sh)
1017 mlx5_txpp_stop_service(sh);
1018 mlx5_txpp_destroy_rearm_queue(sh);
1019 mlx5_txpp_destroy_clock_queue(sh);
1020 mlx5_txpp_free_pp_index(sh);
1021 mlx5_txpp_destroy_event_channel(sh);
1028 * Creates and starts packet pacing infrastructure on specified device.
1031 * Pointer to Ethernet device structure.
1034 * 0 on success, a negative errno value otherwise and rte_errno is set.
1037 mlx5_txpp_start(struct rte_eth_dev *dev)
1039 struct mlx5_priv *priv = dev->data->dev_private;
1040 struct mlx5_dev_ctx_shared *sh = priv->sh;
1044 if (!priv->config.tx_pp) {
1045 /* Packet pacing is not requested for the device. */
1046 MLX5_ASSERT(priv->txpp_en == 0);
1049 if (priv->txpp_en) {
1050 /* Packet pacing is already enabled for the device. */
1051 MLX5_ASSERT(sh->txpp.refcnt);
1054 if (priv->config.tx_pp > 0) {
1055 ret = rte_mbuf_dynflag_lookup
1056 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
1060 ret = pthread_mutex_lock(&sh->txpp.mutex);
1063 if (sh->txpp.refcnt) {
1067 err = mlx5_txpp_create(sh, priv);
1069 MLX5_ASSERT(sh->txpp.tick);
1071 sh->txpp.refcnt = 1;
1076 ret = pthread_mutex_unlock(&sh->txpp.mutex);
1083 * Stops and destroys packet pacing infrastructure on specified device.
1086 * Pointer to Ethernet device structure.
1089 * 0 on success, a negative errno value otherwise and rte_errno is set.
1092 mlx5_txpp_stop(struct rte_eth_dev *dev)
1094 struct mlx5_priv *priv = dev->data->dev_private;
1095 struct mlx5_dev_ctx_shared *sh = priv->sh;
1098 if (!priv->txpp_en) {
1099 /* Packet pacing is already disabled for the device. */
1103 ret = pthread_mutex_lock(&sh->txpp.mutex);
1106 MLX5_ASSERT(sh->txpp.refcnt);
1107 if (!sh->txpp.refcnt || --sh->txpp.refcnt)
1109 /* No references any more, do actual destroy. */
1110 mlx5_txpp_destroy(sh);
1111 ret = pthread_mutex_unlock(&sh->txpp.mutex);
1117 * Read the current clock counter of an Ethernet device
1119 * This returns the current raw clock value of an Ethernet device. It is
1120 * a raw amount of ticks, with no given time reference.
1121 * The value returned here is from the same clock than the one
1122 * filling timestamp field of Rx/Tx packets when using hardware timestamp
1123 * offload. Therefore it can be used to compute a precise conversion of
1124 * the device clock to the real time.
1127 * Pointer to Ethernet device structure.
1129 * Pointer to the uint64_t that holds the raw clock value.
1133 * - -ENOTSUP: The function is not supported in this mode. Requires
1134 * packet pacing module configured and started (tx_pp devarg)
1137 mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp)
1139 struct mlx5_priv *priv = dev->data->dev_private;
1140 struct mlx5_dev_ctx_shared *sh = priv->sh;
1143 if (sh->txpp.refcnt) {
1144 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
1145 struct mlx5_cqe *cqe = (struct mlx5_cqe *)(uintptr_t)wq->cqes;
1148 struct mlx5_cqe_ts cts;
1152 mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128);
1153 if (to.cts.op_own >> 4) {
1154 DRV_LOG(DEBUG, "Clock Queue error sync lost.");
1155 __atomic_fetch_add(&sh->txpp.err_clock_queue,
1156 1, __ATOMIC_RELAXED);
1157 sh->txpp.sync_lost = 1;
1160 ts = rte_be_to_cpu_64(to.cts.timestamp);
1161 ts = mlx5_txpp_convert_rx_ts(sh, ts);
1165 /* Not supported in isolated mode - kernel does not see the CQEs. */
1166 if (priv->isolated || rte_eal_process_type() != RTE_PROC_PRIMARY)
1168 ret = mlx5_read_clock(dev, timestamp);
1173 * DPDK callback to clear device extended statistics.
1176 * Pointer to Ethernet device structure.
1179 * 0 on success and stats is reset, negative errno value otherwise and
1182 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev)
1184 struct mlx5_priv *priv = dev->data->dev_private;
1185 struct mlx5_dev_ctx_shared *sh = priv->sh;
1187 __atomic_store_n(&sh->txpp.err_miss_int, 0, __ATOMIC_RELAXED);
1188 __atomic_store_n(&sh->txpp.err_rearm_queue, 0, __ATOMIC_RELAXED);
1189 __atomic_store_n(&sh->txpp.err_clock_queue, 0, __ATOMIC_RELAXED);
1190 __atomic_store_n(&sh->txpp.err_ts_past, 0, __ATOMIC_RELAXED);
1191 __atomic_store_n(&sh->txpp.err_ts_future, 0, __ATOMIC_RELAXED);
1196 * Routine to retrieve names of extended device statistics
1197 * for packet send scheduling. It appends the specific stats names
1198 * after the parts filled by preceding modules (eth stats, etc.)
1201 * Pointer to Ethernet device structure.
1202 * @param[out] xstats_names
1203 * Buffer to insert names into.
1207 * Number of names filled by preceding statistics modules.
1210 * Number of xstats names.
1212 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1213 struct rte_eth_xstat_name *xstats_names,
1214 unsigned int n, unsigned int n_used)
1216 unsigned int n_txpp = RTE_DIM(mlx5_txpp_stat_names);
1219 if (n >= n_used + n_txpp && xstats_names) {
1220 for (i = 0; i < n_txpp; ++i) {
1221 strncpy(xstats_names[i + n_used].name,
1222 mlx5_txpp_stat_names[i],
1223 RTE_ETH_XSTATS_NAME_SIZE);
1224 xstats_names[i + n_used].name
1225 [RTE_ETH_XSTATS_NAME_SIZE - 1] = 0;
1228 return n_used + n_txpp;
1232 mlx5_txpp_read_tsa(struct mlx5_dev_txpp *txpp,
1233 struct mlx5_txpp_ts *tsa, uint16_t idx)
1238 ts = __atomic_load_n(&txpp->tsa[idx].ts, __ATOMIC_RELAXED);
1239 ci = __atomic_load_n(&txpp->tsa[idx].ci_ts, __ATOMIC_RELAXED);
1240 rte_compiler_barrier();
1241 if ((ci ^ ts) << MLX5_CQ_INDEX_WIDTH != 0)
1243 if (__atomic_load_n(&txpp->tsa[idx].ts,
1244 __ATOMIC_RELAXED) != ts)
1246 if (__atomic_load_n(&txpp->tsa[idx].ci_ts,
1247 __ATOMIC_RELAXED) != ci)
1256 * Jitter reflects the clock change between
1257 * neighbours Clock Queue completions.
1260 mlx5_txpp_xstats_jitter(struct mlx5_dev_txpp *txpp)
1262 struct mlx5_txpp_ts tsa0, tsa1;
1266 if (txpp->ts_n < 2) {
1267 /* No gathered enough reports yet. */
1274 rte_compiler_barrier();
1277 ts_0 += MLX5_TXPP_REARM_SQ_SIZE;
1280 ts_1 += MLX5_TXPP_REARM_SQ_SIZE;
1281 mlx5_txpp_read_tsa(txpp, &tsa0, ts_0);
1282 mlx5_txpp_read_tsa(txpp, &tsa1, ts_1);
1283 rte_compiler_barrier();
1284 } while (ts_p != txpp->ts_p);
1285 /* We have two neighbor reports, calculate the jitter. */
1286 dts = tsa1.ts - tsa0.ts;
1287 dci = (tsa1.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH)) -
1288 (tsa0.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH));
1290 dci += 1 << MLX5_CQ_INDEX_WIDTH;
1292 return (dts > dci) ? dts - dci : dci - dts;
1296 * Wander reflects the long-term clock change
1297 * over the entire length of all Clock Queue completions.
1300 mlx5_txpp_xstats_wander(struct mlx5_dev_txpp *txpp)
1302 struct mlx5_txpp_ts tsa0, tsa1;
1306 if (txpp->ts_n < MLX5_TXPP_REARM_SQ_SIZE) {
1307 /* No gathered enough reports yet. */
1314 rte_compiler_barrier();
1315 ts_0 = ts_p - MLX5_TXPP_REARM_SQ_SIZE / 2 - 1;
1317 ts_0 += MLX5_TXPP_REARM_SQ_SIZE;
1320 ts_1 += MLX5_TXPP_REARM_SQ_SIZE;
1321 mlx5_txpp_read_tsa(txpp, &tsa0, ts_0);
1322 mlx5_txpp_read_tsa(txpp, &tsa1, ts_1);
1323 rte_compiler_barrier();
1324 } while (ts_p != txpp->ts_p);
1325 /* We have two neighbor reports, calculate the jitter. */
1326 dts = tsa1.ts - tsa0.ts;
1327 dci = (tsa1.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH)) -
1328 (tsa0.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH));
1329 dci += 1 << MLX5_CQ_INDEX_WIDTH;
1331 return (dts > dci) ? dts - dci : dci - dts;
1335 * Routine to retrieve extended device statistics
1336 * for packet send scheduling. It appends the specific statistics
1337 * after the parts filled by preceding modules (eth stats, etc.)
1340 * Pointer to Ethernet device.
1342 * Pointer to rte extended stats table.
1344 * The size of the stats table.
1346 * Number of stats filled by preceding statistics modules.
1349 * Number of extended stats on success and stats is filled,
1350 * negative on error and rte_errno is set.
1353 mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1354 struct rte_eth_xstat *stats,
1355 unsigned int n, unsigned int n_used)
1357 unsigned int n_txpp = RTE_DIM(mlx5_txpp_stat_names);
1359 if (n >= n_used + n_txpp && stats) {
1360 struct mlx5_priv *priv = dev->data->dev_private;
1361 struct mlx5_dev_ctx_shared *sh = priv->sh;
1364 for (i = 0; i < n_txpp; ++i)
1365 stats[n_used + i].id = n_used + i;
1366 stats[n_used + 0].value =
1367 __atomic_load_n(&sh->txpp.err_miss_int,
1369 stats[n_used + 1].value =
1370 __atomic_load_n(&sh->txpp.err_rearm_queue,
1372 stats[n_used + 2].value =
1373 __atomic_load_n(&sh->txpp.err_clock_queue,
1375 stats[n_used + 3].value =
1376 __atomic_load_n(&sh->txpp.err_ts_past,
1378 stats[n_used + 4].value =
1379 __atomic_load_n(&sh->txpp.err_ts_future,
1381 stats[n_used + 5].value = mlx5_txpp_xstats_jitter(&sh->txpp);
1382 stats[n_used + 6].value = mlx5_txpp_xstats_wander(&sh->txpp);
1383 stats[n_used + 7].value = sh->txpp.sync_lost;
1385 return n_used + n_txpp;