1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
8 #include <rte_ethdev_driver.h>
9 #include <rte_interrupts.h>
10 #include <rte_alarm.h>
11 #include <rte_malloc.h>
12 #include <rte_cycles.h>
15 #include "mlx5_rxtx.h"
16 #include "mlx5_common_os.h"
18 static const char * const mlx5_txpp_stat_names[] = {
19 "txpp_err_miss_int", /* Missed service interrupt. */
20 "txpp_err_rearm_queue", /* Rearm Queue errors. */
21 "txpp_err_clock_queue", /* Clock Queue errors. */
22 "txpp_err_ts_past", /* Timestamp in the past. */
23 "txpp_err_ts_future", /* Timestamp in the distant future. */
24 "txpp_jitter", /* Timestamp jitter (one Clock Queue completion). */
25 "txpp_wander", /* Timestamp jitter (half of Clock Queue completions). */
26 "txpp_sync_lost", /* Scheduling synchronization lost. */
29 /* Destroy Event Queue Notification Channel. */
31 mlx5_txpp_destroy_eqn(struct mlx5_dev_ctx_shared *sh)
34 mlx5_glue->devx_destroy_event_channel(sh->txpp.echan);
35 sh->txpp.echan = NULL;
40 /* Create Event Queue Notification Channel. */
42 mlx5_txpp_create_eqn(struct mlx5_dev_ctx_shared *sh)
46 MLX5_ASSERT(!sh->txpp.echan);
47 lcore = (uint32_t)rte_lcore_to_cpu_id(-1);
48 if (mlx5_glue->devx_query_eqn(sh->ctx, lcore, &sh->txpp.eqn)) {
50 DRV_LOG(ERR, "Failed to query EQ number %d.", rte_errno);
54 sh->txpp.echan = mlx5_glue->devx_create_event_channel(sh->ctx,
55 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
56 if (!sh->txpp.echan) {
59 DRV_LOG(ERR, "Failed to create event channel %d.",
67 mlx5_txpp_free_pp_index(struct mlx5_dev_ctx_shared *sh)
70 mlx5_glue->dv_free_pp(sh->txpp.pp);
76 /* Allocate Packet Pacing index from kernel via mlx5dv call. */
78 mlx5_txpp_alloc_pp_index(struct mlx5_dev_ctx_shared *sh)
80 #ifdef HAVE_MLX5DV_PP_ALLOC
81 uint32_t pp[MLX5_ST_SZ_DW(set_pp_rate_limit_context)];
84 MLX5_ASSERT(!sh->txpp.pp);
85 memset(&pp, 0, sizeof(pp));
86 rate = NS_PER_S / sh->txpp.tick;
87 if (rate * sh->txpp.tick != NS_PER_S)
88 DRV_LOG(WARNING, "Packet pacing frequency is not precise.");
92 len = RTE_MAX(MLX5_TXPP_TEST_PKT_SIZE,
93 (size_t)RTE_ETHER_MIN_LEN);
94 MLX5_SET(set_pp_rate_limit_context, &pp,
95 burst_upper_bound, len);
96 MLX5_SET(set_pp_rate_limit_context, &pp,
97 typical_packet_size, len);
98 /* Convert packets per second into kilobits. */
99 rate = (rate * len) / (1000ul / CHAR_BIT);
100 DRV_LOG(INFO, "Packet pacing rate set to %" PRIu64, rate);
102 MLX5_SET(set_pp_rate_limit_context, &pp, rate_limit, rate);
103 MLX5_SET(set_pp_rate_limit_context, &pp, rate_mode,
104 sh->txpp.test ? MLX5_DATA_RATE : MLX5_WQE_RATE);
105 sh->txpp.pp = mlx5_glue->dv_alloc_pp
106 (sh->ctx, sizeof(pp), &pp,
107 MLX5DV_PP_ALLOC_FLAGS_DEDICATED_INDEX);
108 if (sh->txpp.pp == NULL) {
109 DRV_LOG(ERR, "Failed to allocate packet pacing index.");
113 if (!sh->txpp.pp->index) {
114 DRV_LOG(ERR, "Zero packet pacing index allocated.");
115 mlx5_txpp_free_pp_index(sh);
119 sh->txpp.pp_id = sh->txpp.pp->index;
123 DRV_LOG(ERR, "Allocating pacing index is not supported.");
130 mlx5_txpp_destroy_send_queue(struct mlx5_txpp_wq *wq)
133 claim_zero(mlx5_devx_cmd_destroy(wq->sq));
135 claim_zero(mlx5_glue->devx_umem_dereg(wq->sq_umem));
137 rte_free((void *)(uintptr_t)wq->sq_buf);
139 claim_zero(mlx5_devx_cmd_destroy(wq->cq));
141 claim_zero(mlx5_glue->devx_umem_dereg(wq->cq_umem));
143 rte_free((void *)(uintptr_t)wq->cq_buf);
144 memset(wq, 0, sizeof(*wq));
148 mlx5_txpp_destroy_rearm_queue(struct mlx5_dev_ctx_shared *sh)
150 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
152 mlx5_txpp_destroy_send_queue(wq);
156 mlx5_txpp_destroy_clock_queue(struct mlx5_dev_ctx_shared *sh)
158 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
160 mlx5_txpp_destroy_send_queue(wq);
162 rte_free(sh->txpp.tsa);
168 mlx5_txpp_doorbell_rearm_queue(struct mlx5_dev_ctx_shared *sh, uint16_t ci)
170 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
177 cs.w32[0] = rte_cpu_to_be_32(rte_be_to_cpu_32
178 (wq->wqes[ci & (wq->sq_size - 1)].ctrl[0]) | (ci - 1) << 8);
179 cs.w32[1] = wq->wqes[ci & (wq->sq_size - 1)].ctrl[1];
180 /* Update SQ doorbell record with new SQ ci. */
181 rte_compiler_barrier();
182 *wq->sq_dbrec = rte_cpu_to_be_32(wq->sq_ci);
183 /* Make sure the doorbell record is updated. */
185 /* Write to doorbel register to start processing. */
186 __mlx5_uar_write64_relaxed(cs.w64, sh->tx_uar->reg_addr, NULL);
191 mlx5_txpp_fill_cqe_rearm_queue(struct mlx5_dev_ctx_shared *sh)
193 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
194 struct mlx5_cqe *cqe = (struct mlx5_cqe *)(uintptr_t)wq->cqes;
197 for (i = 0; i < MLX5_TXPP_REARM_CQ_SIZE; i++) {
198 cqe->op_own = (MLX5_CQE_INVALID << 4) | MLX5_CQE_OWNER_MASK;
204 mlx5_txpp_fill_wqe_rearm_queue(struct mlx5_dev_ctx_shared *sh)
206 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
207 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->wqes;
210 for (i = 0; i < wq->sq_size; i += 2) {
211 struct mlx5_wqe_cseg *cs;
212 struct mlx5_wqe_qseg *qs;
215 /* Build SEND_EN request with slave WQE index. */
216 cs = &wqe[i + 0].cseg;
217 cs->opcode = RTE_BE32(MLX5_OPCODE_SEND_EN | 0);
218 cs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) | 2);
219 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS <<
220 MLX5_COMP_MODE_OFFSET);
221 cs->misc = RTE_BE32(0);
222 qs = RTE_PTR_ADD(cs, sizeof(struct mlx5_wqe_cseg));
223 index = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM) &
224 ((1 << MLX5_WQ_INDEX_WIDTH) - 1);
225 qs->max_index = rte_cpu_to_be_32(index);
226 qs->qpn_cqn = rte_cpu_to_be_32(sh->txpp.clock_queue.sq->id);
227 /* Build WAIT request with slave CQE index. */
228 cs = &wqe[i + 1].cseg;
229 cs->opcode = RTE_BE32(MLX5_OPCODE_WAIT | 0);
230 cs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) | 2);
231 cs->flags = RTE_BE32(MLX5_COMP_ONLY_ERR <<
232 MLX5_COMP_MODE_OFFSET);
233 cs->misc = RTE_BE32(0);
234 qs = RTE_PTR_ADD(cs, sizeof(struct mlx5_wqe_cseg));
235 index = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM / 2) &
236 ((1 << MLX5_CQ_INDEX_WIDTH) - 1);
237 qs->max_index = rte_cpu_to_be_32(index);
238 qs->qpn_cqn = rte_cpu_to_be_32(sh->txpp.clock_queue.cq->id);
242 /* Creates the Rearm Queue to fire the requests to Clock Queue in realtime. */
244 mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)
246 struct mlx5_devx_create_sq_attr sq_attr = { 0 };
247 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
248 struct mlx5_devx_cq_attr cq_attr = { 0 };
249 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
250 size_t page_size = sysconf(_SC_PAGESIZE);
251 uint32_t umem_size, umem_dbrec;
254 /* Allocate memory buffer for CQEs and doorbell record. */
255 umem_size = sizeof(struct mlx5_cqe) * MLX5_TXPP_REARM_CQ_SIZE;
256 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
257 umem_size += MLX5_DBR_SIZE;
258 wq->cq_buf = rte_zmalloc_socket(__func__, umem_size,
259 page_size, sh->numa_node);
261 DRV_LOG(ERR, "Failed to allocate memory for Rearm Queue.");
264 /* Register allocated buffer in user space with DevX. */
265 wq->cq_umem = mlx5_glue->devx_umem_reg(sh->ctx,
266 (void *)(uintptr_t)wq->cq_buf,
268 IBV_ACCESS_LOCAL_WRITE);
271 DRV_LOG(ERR, "Failed to register umem for Rearm Queue.");
274 /* Create completion queue object for Rearm Queue. */
275 cq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?
276 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;
277 cq_attr.uar_page_id = sh->tx_uar->page_id;
278 cq_attr.eqn = sh->txpp.eqn;
279 cq_attr.q_umem_valid = 1;
280 cq_attr.q_umem_offset = 0;
281 cq_attr.q_umem_id = mlx5_os_get_umem_id(wq->cq_umem);
282 cq_attr.db_umem_valid = 1;
283 cq_attr.db_umem_offset = umem_dbrec;
284 cq_attr.db_umem_id = mlx5_os_get_umem_id(wq->cq_umem);
285 cq_attr.log_cq_size = rte_log2_u32(MLX5_TXPP_REARM_CQ_SIZE);
286 cq_attr.log_page_size = rte_log2_u32(page_size);
287 wq->cq = mlx5_devx_cmd_create_cq(sh->ctx, &cq_attr);
290 DRV_LOG(ERR, "Failed to create CQ for Rearm Queue.");
293 wq->cq_dbrec = RTE_PTR_ADD(wq->cq_buf, umem_dbrec);
296 /* Mark all CQEs initially as invalid. */
297 mlx5_txpp_fill_cqe_rearm_queue(sh);
299 * Allocate memory buffer for Send Queue WQEs.
300 * There should be no WQE leftovers in the cyclic queue.
302 wq->sq_size = MLX5_TXPP_REARM_SQ_SIZE;
303 MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));
304 umem_size = MLX5_WQE_SIZE * wq->sq_size;
305 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
306 umem_size += MLX5_DBR_SIZE;
307 wq->sq_buf = rte_zmalloc_socket(__func__, umem_size,
308 page_size, sh->numa_node);
310 DRV_LOG(ERR, "Failed to allocate memory for Rearm Queue.");
314 /* Register allocated buffer in user space with DevX. */
315 wq->sq_umem = mlx5_glue->devx_umem_reg(sh->ctx,
316 (void *)(uintptr_t)wq->sq_buf,
318 IBV_ACCESS_LOCAL_WRITE);
321 DRV_LOG(ERR, "Failed to register umem for Rearm Queue.");
324 /* Create send queue object for Rearm Queue. */
325 sq_attr.state = MLX5_SQC_STATE_RST;
326 sq_attr.tis_lst_sz = 1;
327 sq_attr.tis_num = sh->tis->id;
328 sq_attr.cqn = wq->cq->id;
329 sq_attr.cd_master = 1;
330 sq_attr.wq_attr.uar_page = sh->tx_uar->page_id;
331 sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
332 sq_attr.wq_attr.pd = sh->pdn;
333 sq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);
334 sq_attr.wq_attr.log_wq_sz = rte_log2_u32(wq->sq_size);
335 sq_attr.wq_attr.dbr_umem_valid = 1;
336 sq_attr.wq_attr.dbr_addr = umem_dbrec;
337 sq_attr.wq_attr.dbr_umem_id = mlx5_os_get_umem_id(wq->sq_umem);
338 sq_attr.wq_attr.wq_umem_valid = 1;
339 sq_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(wq->sq_umem);
340 sq_attr.wq_attr.wq_umem_offset = 0;
341 wq->sq = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr);
344 DRV_LOG(ERR, "Failed to create SQ for Rearm Queue.");
347 wq->sq_dbrec = RTE_PTR_ADD(wq->sq_buf, umem_dbrec +
348 MLX5_SND_DBR * sizeof(uint32_t));
349 /* Build the WQEs in the Send Queue before goto Ready state. */
350 mlx5_txpp_fill_wqe_rearm_queue(sh);
351 /* Change queue state to ready. */
352 msq_attr.sq_state = MLX5_SQC_STATE_RST;
353 msq_attr.state = MLX5_SQC_STATE_RDY;
354 ret = mlx5_devx_cmd_modify_sq(wq->sq, &msq_attr);
356 DRV_LOG(ERR, "Failed to set SQ ready state Rearm Queue.");
362 mlx5_txpp_destroy_rearm_queue(sh);
368 mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh)
370 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
371 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->wqes;
372 struct mlx5_wqe_cseg *cs = &wqe->cseg;
373 uint32_t wqe_size, opcode, i;
376 /* For test purposes fill the WQ with SEND inline packet. */
378 wqe_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
380 2 * MLX5_WQE_ESEG_SIZE -
381 MLX5_ESEG_MIN_INLINE_SIZE,
383 opcode = MLX5_OPCODE_SEND;
385 wqe_size = MLX5_WSEG_SIZE;
386 opcode = MLX5_OPCODE_NOP;
388 cs->opcode = rte_cpu_to_be_32(opcode | 0); /* Index is ignored. */
389 cs->sq_ds = rte_cpu_to_be_32((wq->sq->id << 8) |
390 (wqe_size / MLX5_WSEG_SIZE));
391 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS << MLX5_COMP_MODE_OFFSET);
392 cs->misc = RTE_BE32(0);
393 wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE);
395 struct mlx5_wqe_eseg *es = &wqe->eseg;
396 struct rte_ether_hdr *eth_hdr;
397 struct rte_ipv4_hdr *ip_hdr;
398 struct rte_udp_hdr *udp_hdr;
400 /* Build the inline test packet pattern. */
401 MLX5_ASSERT(wqe_size <= MLX5_WQE_SIZE_MAX);
402 MLX5_ASSERT(MLX5_TXPP_TEST_PKT_SIZE >=
403 (sizeof(struct rte_ether_hdr) +
404 sizeof(struct rte_ipv4_hdr)));
406 es->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
411 es->inline_hdr_sz = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE);
412 /* Build test packet L2 header (Ethernet). */
413 dst = (uint8_t *)&es->inline_data;
414 eth_hdr = (struct rte_ether_hdr *)dst;
415 rte_eth_random_addr(ð_hdr->d_addr.addr_bytes[0]);
416 rte_eth_random_addr(ð_hdr->s_addr.addr_bytes[0]);
417 eth_hdr->ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
418 /* Build test packet L3 header (IP v4). */
419 dst += sizeof(struct rte_ether_hdr);
420 ip_hdr = (struct rte_ipv4_hdr *)dst;
421 ip_hdr->version_ihl = RTE_IPV4_VHL_DEF;
422 ip_hdr->type_of_service = 0;
423 ip_hdr->fragment_offset = 0;
424 ip_hdr->time_to_live = 64;
425 ip_hdr->next_proto_id = IPPROTO_UDP;
426 ip_hdr->packet_id = 0;
427 ip_hdr->total_length = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE -
428 sizeof(struct rte_ether_hdr));
429 /* use RFC5735 / RFC2544 reserved network test addresses */
430 ip_hdr->src_addr = RTE_BE32((198U << 24) | (18 << 16) |
432 ip_hdr->dst_addr = RTE_BE32((198U << 24) | (18 << 16) |
434 if (MLX5_TXPP_TEST_PKT_SIZE <
435 (sizeof(struct rte_ether_hdr) +
436 sizeof(struct rte_ipv4_hdr) +
437 sizeof(struct rte_udp_hdr)))
439 /* Build test packet L4 header (UDP). */
440 dst += sizeof(struct rte_ipv4_hdr);
441 udp_hdr = (struct rte_udp_hdr *)dst;
442 udp_hdr->src_port = RTE_BE16(9); /* RFC863 Discard. */
443 udp_hdr->dst_port = RTE_BE16(9);
444 udp_hdr->dgram_len = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE -
445 sizeof(struct rte_ether_hdr) -
446 sizeof(struct rte_ipv4_hdr));
447 udp_hdr->dgram_cksum = 0;
448 /* Fill the test packet data. */
449 dst += sizeof(struct rte_udp_hdr);
450 for (i = sizeof(struct rte_ether_hdr) +
451 sizeof(struct rte_ipv4_hdr) +
452 sizeof(struct rte_udp_hdr);
453 i < MLX5_TXPP_TEST_PKT_SIZE; i++)
454 *dst++ = (uint8_t)(i & 0xFF);
457 /* Duplicate the pattern to the next WQEs. */
458 dst = (uint8_t *)(uintptr_t)wq->sq_buf;
459 for (i = 1; i < MLX5_TXPP_CLKQ_SIZE; i++) {
461 rte_memcpy(dst, (void *)(uintptr_t)wq->sq_buf, wqe_size);
465 /* Creates the Clock Queue for packet pacing, returns zero on success. */
467 mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)
469 struct mlx5_devx_create_sq_attr sq_attr = { 0 };
470 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
471 struct mlx5_devx_cq_attr cq_attr = { 0 };
472 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
473 size_t page_size = sysconf(_SC_PAGESIZE);
474 uint32_t umem_size, umem_dbrec;
477 sh->txpp.tsa = rte_zmalloc_socket(__func__,
478 MLX5_TXPP_REARM_SQ_SIZE *
479 sizeof(struct mlx5_txpp_ts),
482 DRV_LOG(ERR, "Failed to allocate memory for CQ stats.");
487 /* Allocate memory buffer for CQEs and doorbell record. */
488 umem_size = sizeof(struct mlx5_cqe) * MLX5_TXPP_CLKQ_SIZE;
489 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
490 umem_size += MLX5_DBR_SIZE;
491 wq->cq_buf = rte_zmalloc_socket(__func__, umem_size,
492 page_size, sh->numa_node);
494 DRV_LOG(ERR, "Failed to allocate memory for Clock Queue.");
497 /* Register allocated buffer in user space with DevX. */
498 wq->cq_umem = mlx5_glue->devx_umem_reg(sh->ctx,
499 (void *)(uintptr_t)wq->cq_buf,
501 IBV_ACCESS_LOCAL_WRITE);
504 DRV_LOG(ERR, "Failed to register umem for Clock Queue.");
507 /* Create completion queue object for Clock Queue. */
508 cq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?
509 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;
510 cq_attr.use_first_only = 1;
511 cq_attr.overrun_ignore = 1;
512 cq_attr.uar_page_id = sh->tx_uar->page_id;
513 cq_attr.eqn = sh->txpp.eqn;
514 cq_attr.q_umem_valid = 1;
515 cq_attr.q_umem_offset = 0;
516 cq_attr.q_umem_id = wq->cq_umem->umem_id;
517 cq_attr.db_umem_valid = 1;
518 cq_attr.db_umem_offset = umem_dbrec;
519 cq_attr.db_umem_id = wq->cq_umem->umem_id;
520 cq_attr.log_cq_size = rte_log2_u32(MLX5_TXPP_CLKQ_SIZE);
521 cq_attr.log_page_size = rte_log2_u32(page_size);
522 wq->cq = mlx5_devx_cmd_create_cq(sh->ctx, &cq_attr);
525 DRV_LOG(ERR, "Failed to create CQ for Clock Queue.");
528 wq->cq_dbrec = RTE_PTR_ADD(wq->cq_buf, umem_dbrec);
530 /* Allocate memory buffer for Send Queue WQEs. */
532 wq->sq_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
534 2 * MLX5_WQE_ESEG_SIZE -
535 MLX5_ESEG_MIN_INLINE_SIZE,
536 MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
537 wq->sq_size *= MLX5_TXPP_CLKQ_SIZE;
539 wq->sq_size = MLX5_TXPP_CLKQ_SIZE;
541 /* There should not be WQE leftovers in the cyclic queue. */
542 MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));
543 umem_size = MLX5_WQE_SIZE * wq->sq_size;
544 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
545 umem_size += MLX5_DBR_SIZE;
546 wq->sq_buf = rte_zmalloc_socket(__func__, umem_size,
547 page_size, sh->numa_node);
549 DRV_LOG(ERR, "Failed to allocate memory for Clock Queue.");
553 /* Register allocated buffer in user space with DevX. */
554 wq->sq_umem = mlx5_glue->devx_umem_reg(sh->ctx,
555 (void *)(uintptr_t)wq->sq_buf,
557 IBV_ACCESS_LOCAL_WRITE);
560 DRV_LOG(ERR, "Failed to register umem for Clock Queue.");
563 /* Create send queue object for Clock Queue. */
565 sq_attr.tis_lst_sz = 1;
566 sq_attr.tis_num = sh->tis->id;
567 sq_attr.non_wire = 0;
568 sq_attr.static_sq_wq = 1;
570 sq_attr.non_wire = 1;
571 sq_attr.static_sq_wq = 1;
573 sq_attr.state = MLX5_SQC_STATE_RST;
574 sq_attr.cqn = wq->cq->id;
575 sq_attr.packet_pacing_rate_limit_index = sh->txpp.pp_id;
576 sq_attr.wq_attr.cd_slave = 1;
577 sq_attr.wq_attr.uar_page = sh->tx_uar->page_id;
578 sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
579 sq_attr.wq_attr.pd = sh->pdn;
580 sq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);
581 sq_attr.wq_attr.log_wq_sz = rte_log2_u32(wq->sq_size);
582 sq_attr.wq_attr.dbr_umem_valid = 1;
583 sq_attr.wq_attr.dbr_addr = umem_dbrec;
584 sq_attr.wq_attr.dbr_umem_id = wq->sq_umem->umem_id;
585 sq_attr.wq_attr.wq_umem_valid = 1;
586 sq_attr.wq_attr.wq_umem_id = wq->sq_umem->umem_id;
587 /* umem_offset must be zero for static_sq_wq queue. */
588 sq_attr.wq_attr.wq_umem_offset = 0;
589 wq->sq = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr);
592 DRV_LOG(ERR, "Failed to create SQ for Clock Queue.");
595 wq->sq_dbrec = RTE_PTR_ADD(wq->sq_buf, umem_dbrec +
596 MLX5_SND_DBR * sizeof(uint32_t));
597 /* Build the WQEs in the Send Queue before goto Ready state. */
598 mlx5_txpp_fill_wqe_clock_queue(sh);
599 /* Change queue state to ready. */
600 msq_attr.sq_state = MLX5_SQC_STATE_RST;
601 msq_attr.state = MLX5_SQC_STATE_RDY;
603 ret = mlx5_devx_cmd_modify_sq(wq->sq, &msq_attr);
605 DRV_LOG(ERR, "Failed to set SQ ready state Clock Queue.");
611 mlx5_txpp_destroy_clock_queue(sh);
616 /* Enable notification from the Rearm Queue CQ. */
618 mlx5_txpp_cq_arm(struct mlx5_dev_ctx_shared *sh)
620 struct mlx5_txpp_wq *aq = &sh->txpp.rearm_queue;
621 uint32_t arm_sn = aq->arm_sn << MLX5_CQ_SQN_OFFSET;
622 uint32_t db_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | aq->cq_ci;
623 uint64_t db_be = rte_cpu_to_be_64(((uint64_t)db_hi << 32) | aq->cq->id);
624 uint32_t *addr = RTE_PTR_ADD(sh->tx_uar->base_addr, MLX5_CQ_DOORBELL);
626 rte_compiler_barrier();
627 aq->cq_dbrec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(db_hi);
630 *(uint64_t *)addr = db_be;
632 *(uint32_t *)addr = db_be;
634 *((uint32_t *)addr + 1) = db_be >> 32;
640 mlx5_atomic_read_cqe(rte_int128_t *from, rte_int128_t *ts)
643 * The only CQE of Clock Queue is being continuously
644 * update by hardware with soecified rate. We have to
645 * read timestump and WQE completion index atomically.
647 #if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64)
650 memset(&src, 0, sizeof(src));
652 /* if (*from == *ts) *from = *src else *ts = *from; */
653 rte_atomic128_cmp_exchange(from, ts, &src, 0,
654 __ATOMIC_RELAXED, __ATOMIC_RELAXED);
656 rte_atomic64_t *cqe = (rte_atomic64_t *)from;
658 /* Power architecture does not support 16B compare-and-swap. */
663 rte_compiler_barrier();
664 tm = rte_atomic64_read(cqe + 0);
665 op = rte_atomic64_read(cqe + 1);
666 rte_compiler_barrier();
667 if (tm != rte_atomic64_read(cqe + 0))
669 if (op != rte_atomic64_read(cqe + 1))
679 /* Stores timestamp in the cache structure to share data with datapath. */
681 mlx5_txpp_cache_timestamp(struct mlx5_dev_ctx_shared *sh,
682 uint64_t ts, uint64_t ci)
684 ci = ci << (64 - MLX5_CQ_INDEX_WIDTH);
685 ci |= (ts << MLX5_CQ_INDEX_WIDTH) >> MLX5_CQ_INDEX_WIDTH;
686 rte_compiler_barrier();
687 rte_atomic64_set(&sh->txpp.ts.ts, ts);
688 rte_atomic64_set(&sh->txpp.ts.ci_ts, ci);
692 /* Reads timestamp from Clock Queue CQE and stores in the cache. */
694 mlx5_txpp_update_timestamp(struct mlx5_dev_ctx_shared *sh)
696 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
697 struct mlx5_cqe *cqe = (struct mlx5_cqe *)(uintptr_t)wq->cqes;
700 struct mlx5_cqe_ts cts;
705 static_assert(sizeof(struct mlx5_cqe_ts) == sizeof(rte_int128_t),
706 "Wrong timestamp CQE part size");
707 mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128);
708 if (to.cts.op_own >> 4) {
709 DRV_LOG(DEBUG, "Clock Queue error sync lost.");
710 rte_atomic32_inc(&sh->txpp.err_clock_queue);
711 sh->txpp.sync_lost = 1;
714 ci = rte_be_to_cpu_16(to.cts.wqe_counter);
715 ts = rte_be_to_cpu_64(to.cts.timestamp);
716 ts = mlx5_txpp_convert_rx_ts(sh, ts);
717 wq->cq_ci += (ci - wq->sq_ci) & UINT16_MAX;
719 mlx5_txpp_cache_timestamp(sh, ts, wq->cq_ci);
722 /* Waits for the first completion on Clock Queue to init timestamp. */
724 mlx5_txpp_init_timestamp(struct mlx5_dev_ctx_shared *sh)
726 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
731 for (wait = 0; wait < MLX5_TXPP_WAIT_INIT_TS; wait++) {
732 struct timespec onems;
734 mlx5_txpp_update_timestamp(sh);
737 /* Wait one millisecond and try again. */
739 onems.tv_nsec = NS_PER_S / MS_PER_S;
740 nanosleep(&onems, 0);
742 DRV_LOG(ERR, "Unable to initialize timestamp.");
743 sh->txpp.sync_lost = 1;
746 #ifdef HAVE_IBV_DEVX_EVENT
747 /* Gather statistics for timestamp from Clock Queue CQE. */
749 mlx5_txpp_gather_timestamp(struct mlx5_dev_ctx_shared *sh)
751 /* Check whether we have a valid timestamp. */
752 if (!sh->txpp.clock_queue.sq_ci && !sh->txpp.ts_n)
754 MLX5_ASSERT(sh->txpp.ts_p < MLX5_TXPP_REARM_SQ_SIZE);
755 sh->txpp.tsa[sh->txpp.ts_p] = sh->txpp.ts;
756 if (++sh->txpp.ts_p >= MLX5_TXPP_REARM_SQ_SIZE)
758 if (sh->txpp.ts_n < MLX5_TXPP_REARM_SQ_SIZE)
762 /* Handles Rearm Queue completions in periodic service. */
763 static __rte_always_inline void
764 mlx5_txpp_handle_rearm_queue(struct mlx5_dev_ctx_shared *sh)
766 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
767 uint32_t cq_ci = wq->cq_ci;
772 volatile struct mlx5_cqe *cqe;
774 cqe = &wq->cqes[cq_ci & (MLX5_TXPP_REARM_CQ_SIZE - 1)];
775 ret = check_cqe(cqe, MLX5_TXPP_REARM_CQ_SIZE, cq_ci);
777 case MLX5_CQE_STATUS_ERR:
781 case MLX5_CQE_STATUS_SW_OWN:
785 case MLX5_CQE_STATUS_HW_OWN:
791 } while (ret != MLX5_CQE_STATUS_HW_OWN);
792 if (likely(cq_ci != wq->cq_ci)) {
793 /* Check whether we have missed interrupts. */
794 if (cq_ci - wq->cq_ci != 1) {
795 DRV_LOG(DEBUG, "Rearm Queue missed interrupt.");
796 rte_atomic32_inc(&sh->txpp.err_miss_int);
797 /* Check sync lost on wqe index. */
798 if (cq_ci - wq->cq_ci >=
799 (((1UL << MLX5_WQ_INDEX_WIDTH) /
800 MLX5_TXPP_REARM) - 1))
803 /* Update doorbell record to notify hardware. */
804 rte_compiler_barrier();
805 *wq->cq_dbrec = rte_cpu_to_be_32(cq_ci);
808 /* Fire new requests to Rearm Queue. */
810 DRV_LOG(DEBUG, "Rearm Queue error sync lost.");
811 rte_atomic32_inc(&sh->txpp.err_rearm_queue);
812 sh->txpp.sync_lost = 1;
817 /* Handles Clock Queue completions in periodic service. */
818 static __rte_always_inline void
819 mlx5_txpp_handle_clock_queue(struct mlx5_dev_ctx_shared *sh)
821 mlx5_txpp_update_timestamp(sh);
822 mlx5_txpp_gather_timestamp(sh);
826 /* Invoked periodically on Rearm Queue completions. */
828 mlx5_txpp_interrupt_handler(void *cb_arg)
830 #ifndef HAVE_IBV_DEVX_EVENT
831 RTE_SET_USED(cb_arg);
834 struct mlx5_dev_ctx_shared *sh = cb_arg;
836 struct mlx5dv_devx_async_event_hdr event_resp;
837 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
840 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
841 /* Process events in the loop. Only rearm completions are expected. */
842 while (mlx5_glue->devx_get_event
846 (ssize_t)sizeof(out.event_resp.cookie)) {
847 mlx5_txpp_handle_rearm_queue(sh);
848 mlx5_txpp_handle_clock_queue(sh);
849 mlx5_txpp_cq_arm(sh);
850 mlx5_txpp_doorbell_rearm_queue
851 (sh, sh->txpp.rearm_queue.sq_ci - 1);
853 #endif /* HAVE_IBV_DEVX_ASYNC */
857 mlx5_txpp_stop_service(struct mlx5_dev_ctx_shared *sh)
859 if (!sh->txpp.intr_handle.fd)
861 mlx5_intr_callback_unregister(&sh->txpp.intr_handle,
862 mlx5_txpp_interrupt_handler, sh);
863 sh->txpp.intr_handle.fd = 0;
866 /* Attach interrupt handler and fires first request to Rearm Queue. */
868 mlx5_txpp_start_service(struct mlx5_dev_ctx_shared *sh)
870 uint16_t event_nums[1] = {0};
874 rte_atomic32_set(&sh->txpp.err_miss_int, 0);
875 rte_atomic32_set(&sh->txpp.err_rearm_queue, 0);
876 rte_atomic32_set(&sh->txpp.err_clock_queue, 0);
877 rte_atomic32_set(&sh->txpp.err_ts_past, 0);
878 rte_atomic32_set(&sh->txpp.err_ts_future, 0);
879 /* Attach interrupt handler to process Rearm Queue completions. */
880 flags = fcntl(sh->txpp.echan->fd, F_GETFL);
881 ret = fcntl(sh->txpp.echan->fd, F_SETFL, flags | O_NONBLOCK);
883 DRV_LOG(ERR, "Failed to change event channel FD.");
887 memset(&sh->txpp.intr_handle, 0, sizeof(sh->txpp.intr_handle));
888 sh->txpp.intr_handle.fd = sh->txpp.echan->fd;
889 sh->txpp.intr_handle.type = RTE_INTR_HANDLE_EXT;
890 if (rte_intr_callback_register(&sh->txpp.intr_handle,
891 mlx5_txpp_interrupt_handler, sh)) {
892 sh->txpp.intr_handle.fd = 0;
893 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
896 /* Subscribe CQ event to the event channel controlled by the driver. */
897 ret = mlx5_glue->devx_subscribe_devx_event(sh->txpp.echan,
898 sh->txpp.rearm_queue.cq->obj,
902 DRV_LOG(ERR, "Failed to subscribe CQE event.");
906 /* Enable interrupts in the CQ. */
907 mlx5_txpp_cq_arm(sh);
908 /* Fire the first request on Rearm Queue. */
909 mlx5_txpp_doorbell_rearm_queue(sh, sh->txpp.rearm_queue.sq_size - 1);
910 mlx5_txpp_init_timestamp(sh);
915 * The routine initializes the packet pacing infrastructure:
916 * - allocates PP context
919 * - attaches rearm interrupt handler
920 * - starts Clock Queue
922 * Returns 0 on success, negative otherwise
925 mlx5_txpp_create(struct mlx5_dev_ctx_shared *sh, struct mlx5_priv *priv)
927 int tx_pp = priv->config.tx_pp;
930 /* Store the requested pacing parameters. */
931 sh->txpp.tick = tx_pp >= 0 ? tx_pp : -tx_pp;
932 sh->txpp.test = !!(tx_pp < 0);
933 sh->txpp.skew = priv->config.tx_skew;
934 sh->txpp.freq = priv->config.hca_attr.dev_freq_khz;
935 ret = mlx5_txpp_create_eqn(sh);
938 ret = mlx5_txpp_alloc_pp_index(sh);
941 ret = mlx5_txpp_create_clock_queue(sh);
944 ret = mlx5_txpp_create_rearm_queue(sh);
947 ret = mlx5_txpp_start_service(sh);
952 mlx5_txpp_stop_service(sh);
953 mlx5_txpp_destroy_rearm_queue(sh);
954 mlx5_txpp_destroy_clock_queue(sh);
955 mlx5_txpp_free_pp_index(sh);
956 mlx5_txpp_destroy_eqn(sh);
965 * The routine destroys the packet pacing infrastructure:
966 * - detaches rearm interrupt handler
972 mlx5_txpp_destroy(struct mlx5_dev_ctx_shared *sh)
974 mlx5_txpp_stop_service(sh);
975 mlx5_txpp_destroy_rearm_queue(sh);
976 mlx5_txpp_destroy_clock_queue(sh);
977 mlx5_txpp_free_pp_index(sh);
978 mlx5_txpp_destroy_eqn(sh);
985 * Creates and starts packet pacing infrastructure on specified device.
988 * Pointer to Ethernet device structure.
991 * 0 on success, a negative errno value otherwise and rte_errno is set.
994 mlx5_txpp_start(struct rte_eth_dev *dev)
996 struct mlx5_priv *priv = dev->data->dev_private;
997 struct mlx5_dev_ctx_shared *sh = priv->sh;
1001 if (!priv->config.tx_pp) {
1002 /* Packet pacing is not requested for the device. */
1003 MLX5_ASSERT(priv->txpp_en == 0);
1006 if (priv->txpp_en) {
1007 /* Packet pacing is already enabled for the device. */
1008 MLX5_ASSERT(sh->txpp.refcnt);
1011 if (priv->config.tx_pp > 0) {
1012 ret = rte_mbuf_dynflag_lookup
1013 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
1017 ret = pthread_mutex_lock(&sh->txpp.mutex);
1020 if (sh->txpp.refcnt) {
1024 err = mlx5_txpp_create(sh, priv);
1026 MLX5_ASSERT(sh->txpp.tick);
1028 sh->txpp.refcnt = 1;
1033 ret = pthread_mutex_unlock(&sh->txpp.mutex);
1040 * Stops and destroys packet pacing infrastructure on specified device.
1043 * Pointer to Ethernet device structure.
1046 * 0 on success, a negative errno value otherwise and rte_errno is set.
1049 mlx5_txpp_stop(struct rte_eth_dev *dev)
1051 struct mlx5_priv *priv = dev->data->dev_private;
1052 struct mlx5_dev_ctx_shared *sh = priv->sh;
1055 if (!priv->txpp_en) {
1056 /* Packet pacing is already disabled for the device. */
1060 ret = pthread_mutex_lock(&sh->txpp.mutex);
1063 MLX5_ASSERT(sh->txpp.refcnt);
1064 if (!sh->txpp.refcnt || --sh->txpp.refcnt)
1066 /* No references any more, do actual destroy. */
1067 mlx5_txpp_destroy(sh);
1068 ret = pthread_mutex_unlock(&sh->txpp.mutex);
1074 * Read the current clock counter of an Ethernet device
1076 * This returns the current raw clock value of an Ethernet device. It is
1077 * a raw amount of ticks, with no given time reference.
1078 * The value returned here is from the same clock than the one
1079 * filling timestamp field of Rx/Tx packets when using hardware timestamp
1080 * offload. Therefore it can be used to compute a precise conversion of
1081 * the device clock to the real time.
1084 * Pointer to Ethernet device structure.
1086 * Pointer to the uint64_t that holds the raw clock value.
1090 * - -ENOTSUP: The function is not supported in this mode. Requires
1091 * packet pacing module configured and started (tx_pp devarg)
1094 mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp)
1096 struct mlx5_priv *priv = dev->data->dev_private;
1097 struct mlx5_dev_ctx_shared *sh = priv->sh;
1100 if (sh->txpp.refcnt) {
1101 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
1102 struct mlx5_cqe *cqe = (struct mlx5_cqe *)(uintptr_t)wq->cqes;
1105 struct mlx5_cqe_ts cts;
1109 mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128);
1110 if (to.cts.op_own >> 4) {
1111 DRV_LOG(DEBUG, "Clock Queue error sync lost.");
1112 rte_atomic32_inc(&sh->txpp.err_clock_queue);
1113 sh->txpp.sync_lost = 1;
1116 ts = rte_be_to_cpu_64(to.cts.timestamp);
1117 ts = mlx5_txpp_convert_rx_ts(sh, ts);
1121 /* Not supported in isolated mode - kernel does not see the CQEs. */
1122 if (priv->isolated || rte_eal_process_type() != RTE_PROC_PRIMARY)
1124 ret = mlx5_read_clock(dev, timestamp);
1129 * DPDK callback to clear device extended statistics.
1132 * Pointer to Ethernet device structure.
1135 * 0 on success and stats is reset, negative errno value otherwise and
1138 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev)
1140 struct mlx5_priv *priv = dev->data->dev_private;
1141 struct mlx5_dev_ctx_shared *sh = priv->sh;
1143 rte_atomic32_set(&sh->txpp.err_miss_int, 0);
1144 rte_atomic32_set(&sh->txpp.err_rearm_queue, 0);
1145 rte_atomic32_set(&sh->txpp.err_clock_queue, 0);
1146 rte_atomic32_set(&sh->txpp.err_ts_past, 0);
1147 rte_atomic32_set(&sh->txpp.err_ts_future, 0);
1152 * Routine to retrieve names of extended device statistics
1153 * for packet send scheduling. It appends the specific stats names
1154 * after the parts filled by preceding modules (eth stats, etc.)
1157 * Pointer to Ethernet device structure.
1158 * @param[out] xstats_names
1159 * Buffer to insert names into.
1163 * Number of names filled by preceding statistics modules.
1166 * Number of xstats names.
1168 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1169 struct rte_eth_xstat_name *xstats_names,
1170 unsigned int n, unsigned int n_used)
1172 unsigned int n_txpp = RTE_DIM(mlx5_txpp_stat_names);
1175 if (n >= n_used + n_txpp && xstats_names) {
1176 for (i = 0; i < n_txpp; ++i) {
1177 strncpy(xstats_names[i + n_used].name,
1178 mlx5_txpp_stat_names[i],
1179 RTE_ETH_XSTATS_NAME_SIZE);
1180 xstats_names[i + n_used].name
1181 [RTE_ETH_XSTATS_NAME_SIZE - 1] = 0;
1184 return n_used + n_txpp;
1188 mlx5_txpp_read_tsa(struct mlx5_dev_txpp *txpp,
1189 struct mlx5_txpp_ts *tsa, uint16_t idx)
1194 ts = rte_atomic64_read(&txpp->tsa[idx].ts);
1195 ci = rte_atomic64_read(&txpp->tsa[idx].ci_ts);
1196 rte_compiler_barrier();
1197 if ((ci ^ ts) << MLX5_CQ_INDEX_WIDTH != 0)
1199 if (rte_atomic64_read(&txpp->tsa[idx].ts) != ts)
1201 if (rte_atomic64_read(&txpp->tsa[idx].ci_ts) != ci)
1203 rte_atomic64_set(&tsa->ts, ts);
1204 rte_atomic64_set(&tsa->ci_ts, ci);
1210 * Jitter reflects the clock change between
1211 * neighbours Clock Queue completions.
1214 mlx5_txpp_xstats_jitter(struct mlx5_dev_txpp *txpp)
1216 struct mlx5_txpp_ts tsa0, tsa1;
1220 if (txpp->ts_n < 2) {
1221 /* No gathered enough reports yet. */
1228 rte_compiler_barrier();
1231 ts_0 += MLX5_TXPP_REARM_SQ_SIZE;
1234 ts_1 += MLX5_TXPP_REARM_SQ_SIZE;
1235 mlx5_txpp_read_tsa(txpp, &tsa0, ts_0);
1236 mlx5_txpp_read_tsa(txpp, &tsa1, ts_1);
1237 rte_compiler_barrier();
1238 } while (ts_p != txpp->ts_p);
1239 /* We have two neighbor reports, calculate the jitter. */
1240 dts = rte_atomic64_read(&tsa1.ts) - rte_atomic64_read(&tsa0.ts);
1241 dci = (rte_atomic64_read(&tsa1.ci_ts) >> (64 - MLX5_CQ_INDEX_WIDTH)) -
1242 (rte_atomic64_read(&tsa0.ci_ts) >> (64 - MLX5_CQ_INDEX_WIDTH));
1244 dci += 1 << MLX5_CQ_INDEX_WIDTH;
1246 return (dts > dci) ? dts - dci : dci - dts;
1250 * Wander reflects the long-term clock change
1251 * over the entire length of all Clock Queue completions.
1254 mlx5_txpp_xstats_wander(struct mlx5_dev_txpp *txpp)
1256 struct mlx5_txpp_ts tsa0, tsa1;
1260 if (txpp->ts_n < MLX5_TXPP_REARM_SQ_SIZE) {
1261 /* No gathered enough reports yet. */
1268 rte_compiler_barrier();
1269 ts_0 = ts_p - MLX5_TXPP_REARM_SQ_SIZE / 2 - 1;
1271 ts_0 += MLX5_TXPP_REARM_SQ_SIZE;
1274 ts_1 += MLX5_TXPP_REARM_SQ_SIZE;
1275 mlx5_txpp_read_tsa(txpp, &tsa0, ts_0);
1276 mlx5_txpp_read_tsa(txpp, &tsa1, ts_1);
1277 rte_compiler_barrier();
1278 } while (ts_p != txpp->ts_p);
1279 /* We have two neighbor reports, calculate the jitter. */
1280 dts = rte_atomic64_read(&tsa1.ts) - rte_atomic64_read(&tsa0.ts);
1281 dci = (rte_atomic64_read(&tsa1.ci_ts) >> (64 - MLX5_CQ_INDEX_WIDTH)) -
1282 (rte_atomic64_read(&tsa0.ci_ts) >> (64 - MLX5_CQ_INDEX_WIDTH));
1283 dci += 1 << MLX5_CQ_INDEX_WIDTH;
1285 return (dts > dci) ? dts - dci : dci - dts;
1289 * Routine to retrieve extended device statistics
1290 * for packet send scheduling. It appends the specific statistics
1291 * after the parts filled by preceding modules (eth stats, etc.)
1294 * Pointer to Ethernet device.
1296 * Pointer to rte extended stats table.
1298 * The size of the stats table.
1300 * Number of stats filled by preceding statistics modules.
1303 * Number of extended stats on success and stats is filled,
1304 * negative on error and rte_errno is set.
1307 mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1308 struct rte_eth_xstat *stats,
1309 unsigned int n, unsigned int n_used)
1311 unsigned int n_txpp = RTE_DIM(mlx5_txpp_stat_names);
1313 if (n >= n_used + n_txpp && stats) {
1314 struct mlx5_priv *priv = dev->data->dev_private;
1315 struct mlx5_dev_ctx_shared *sh = priv->sh;
1318 for (i = 0; i < n_txpp; ++i)
1319 stats[n_used + i].id = n_used + i;
1320 stats[n_used + 0].value =
1321 rte_atomic32_read(&sh->txpp.err_miss_int);
1322 stats[n_used + 1].value =
1323 rte_atomic32_read(&sh->txpp.err_rearm_queue);
1324 stats[n_used + 2].value =
1325 rte_atomic32_read(&sh->txpp.err_clock_queue);
1326 stats[n_used + 3].value =
1327 rte_atomic32_read(&sh->txpp.err_ts_past);
1328 stats[n_used + 4].value =
1329 rte_atomic32_read(&sh->txpp.err_ts_future);
1330 stats[n_used + 5].value = mlx5_txpp_xstats_jitter(&sh->txpp);
1331 stats[n_used + 6].value = mlx5_txpp_xstats_wander(&sh->txpp);
1332 stats[n_used + 7].value = sh->txpp.sync_lost;
1334 return n_used + n_txpp;