1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
8 #include <ethdev_driver.h>
9 #include <rte_interrupts.h>
10 #include <rte_alarm.h>
11 #include <rte_malloc.h>
12 #include <rte_cycles.h>
13 #include <rte_eal_paging.h>
15 #include <mlx5_malloc.h>
16 #include <mlx5_common_devx.h>
21 #include "mlx5_common_os.h"
23 static_assert(sizeof(struct mlx5_cqe_ts) == sizeof(rte_int128_t),
24 "Wrong timestamp CQE part size");
26 static const char * const mlx5_txpp_stat_names[] = {
27 "tx_pp_missed_interrupt_errors", /* Missed service interrupt. */
28 "tx_pp_rearm_queue_errors", /* Rearm Queue errors. */
29 "tx_pp_clock_queue_errors", /* Clock Queue errors. */
30 "tx_pp_timestamp_past_errors", /* Timestamp in the past. */
31 "tx_pp_timestamp_future_errors", /* Timestamp in the distant future. */
32 "tx_pp_jitter", /* Timestamp jitter (one Clock Queue completion). */
33 "tx_pp_wander", /* Timestamp wander (half of Clock Queue CQEs). */
34 "tx_pp_sync_lost", /* Scheduling synchronization lost. */
37 /* Destroy Event Queue Notification Channel. */
39 mlx5_txpp_destroy_event_channel(struct mlx5_dev_ctx_shared *sh)
42 mlx5_os_devx_destroy_event_channel(sh->txpp.echan);
43 sh->txpp.echan = NULL;
47 /* Create Event Queue Notification Channel. */
49 mlx5_txpp_create_event_channel(struct mlx5_dev_ctx_shared *sh)
51 MLX5_ASSERT(!sh->txpp.echan);
52 sh->txpp.echan = mlx5_os_devx_create_event_channel(sh->cdev->ctx,
53 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
54 if (!sh->txpp.echan) {
56 DRV_LOG(ERR, "Failed to create event channel %d.", rte_errno);
63 mlx5_txpp_free_pp_index(struct mlx5_dev_ctx_shared *sh)
65 #ifdef HAVE_MLX5DV_PP_ALLOC
67 mlx5_glue->dv_free_pp(sh->txpp.pp);
73 DRV_LOG(ERR, "Freeing pacing index is not supported.");
77 /* Allocate Packet Pacing index from kernel via mlx5dv call. */
79 mlx5_txpp_alloc_pp_index(struct mlx5_dev_ctx_shared *sh)
81 #ifdef HAVE_MLX5DV_PP_ALLOC
82 uint32_t pp[MLX5_ST_SZ_DW(set_pp_rate_limit_context)];
85 MLX5_ASSERT(!sh->txpp.pp);
86 memset(&pp, 0, sizeof(pp));
87 rate = NS_PER_S / sh->txpp.tick;
88 if (rate * sh->txpp.tick != NS_PER_S)
89 DRV_LOG(WARNING, "Packet pacing frequency is not precise.");
93 len = RTE_MAX(MLX5_TXPP_TEST_PKT_SIZE,
94 (size_t)RTE_ETHER_MIN_LEN);
95 MLX5_SET(set_pp_rate_limit_context, &pp,
96 burst_upper_bound, len);
97 MLX5_SET(set_pp_rate_limit_context, &pp,
98 typical_packet_size, len);
99 /* Convert packets per second into kilobits. */
100 rate = (rate * len) / (1000ul / CHAR_BIT);
101 DRV_LOG(INFO, "Packet pacing rate set to %" PRIu64, rate);
103 MLX5_SET(set_pp_rate_limit_context, &pp, rate_limit, rate);
104 MLX5_SET(set_pp_rate_limit_context, &pp, rate_mode,
105 sh->txpp.test ? MLX5_DATA_RATE : MLX5_WQE_RATE);
106 sh->txpp.pp = mlx5_glue->dv_alloc_pp
107 (sh->cdev->ctx, sizeof(pp), &pp,
108 MLX5DV_PP_ALLOC_FLAGS_DEDICATED_INDEX);
109 if (sh->txpp.pp == NULL) {
110 DRV_LOG(ERR, "Failed to allocate packet pacing index.");
114 if (!((struct mlx5dv_pp *)sh->txpp.pp)->index) {
115 DRV_LOG(ERR, "Zero packet pacing index allocated.");
116 mlx5_txpp_free_pp_index(sh);
120 sh->txpp.pp_id = ((struct mlx5dv_pp *)(sh->txpp.pp))->index;
124 DRV_LOG(ERR, "Allocating pacing index is not supported.");
131 mlx5_txpp_destroy_send_queue(struct mlx5_txpp_wq *wq)
133 mlx5_devx_sq_destroy(&wq->sq_obj);
134 mlx5_devx_cq_destroy(&wq->cq_obj);
135 memset(wq, 0, sizeof(*wq));
139 mlx5_txpp_destroy_rearm_queue(struct mlx5_dev_ctx_shared *sh)
141 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
143 mlx5_txpp_destroy_send_queue(wq);
147 mlx5_txpp_destroy_clock_queue(struct mlx5_dev_ctx_shared *sh)
149 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
151 mlx5_txpp_destroy_send_queue(wq);
153 mlx5_free(sh->txpp.tsa);
159 mlx5_txpp_doorbell_rearm_queue(struct mlx5_dev_ctx_shared *sh, uint16_t ci)
161 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
162 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes;
169 cs.w32[0] = rte_cpu_to_be_32(rte_be_to_cpu_32
170 (wqe[ci & (wq->sq_size - 1)].ctrl[0]) | (ci - 1) << 8);
171 cs.w32[1] = wqe[ci & (wq->sq_size - 1)].ctrl[1];
172 /* Update SQ doorbell record with new SQ ci. */
173 mlx5_doorbell_ring(&sh->tx_uar.bf_db, cs.w64, wq->sq_ci,
174 wq->sq_obj.db_rec, !sh->tx_uar.dbnc);
178 mlx5_txpp_fill_wqe_rearm_queue(struct mlx5_dev_ctx_shared *sh)
180 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
181 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes;
184 for (i = 0; i < wq->sq_size; i += 2) {
185 struct mlx5_wqe_cseg *cs;
186 struct mlx5_wqe_qseg *qs;
189 /* Build SEND_EN request with slave WQE index. */
190 cs = &wqe[i + 0].cseg;
191 cs->opcode = RTE_BE32(MLX5_OPCODE_SEND_EN | 0);
192 cs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) | 2);
193 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS <<
194 MLX5_COMP_MODE_OFFSET);
195 cs->misc = RTE_BE32(0);
196 qs = RTE_PTR_ADD(cs, sizeof(struct mlx5_wqe_cseg));
197 index = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM) &
198 ((1 << MLX5_WQ_INDEX_WIDTH) - 1);
199 qs->max_index = rte_cpu_to_be_32(index);
201 rte_cpu_to_be_32(sh->txpp.clock_queue.sq_obj.sq->id);
202 /* Build WAIT request with slave CQE index. */
203 cs = &wqe[i + 1].cseg;
204 cs->opcode = RTE_BE32(MLX5_OPCODE_WAIT | 0);
205 cs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) | 2);
206 cs->flags = RTE_BE32(MLX5_COMP_ONLY_ERR <<
207 MLX5_COMP_MODE_OFFSET);
208 cs->misc = RTE_BE32(0);
209 qs = RTE_PTR_ADD(cs, sizeof(struct mlx5_wqe_cseg));
210 index = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM / 2) &
211 ((1 << MLX5_CQ_INDEX_WIDTH) - 1);
212 qs->max_index = rte_cpu_to_be_32(index);
214 rte_cpu_to_be_32(sh->txpp.clock_queue.cq_obj.cq->id);
218 /* Creates the Rearm Queue to fire the requests to Clock Queue in realtime. */
220 mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)
222 struct mlx5_devx_create_sq_attr sq_attr = {
224 .state = MLX5_SQC_STATE_RST,
226 .tis_num = sh->tis[0]->id,
227 .wq_attr = (struct mlx5_devx_wq_attr){
230 mlx5_os_get_devx_uar_page_id(sh->tx_uar.obj),
232 .ts_format = mlx5_ts_format_conv
233 (sh->cdev->config.hca_attr.sq_ts_format),
235 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
236 struct mlx5_devx_cq_attr cq_attr = {
237 .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar.obj),
239 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
242 /* Create completion queue object for Rearm Queue. */
243 ret = mlx5_devx_cq_create(sh->cdev->ctx, &wq->cq_obj,
244 log2above(MLX5_TXPP_REARM_CQ_SIZE), &cq_attr,
247 DRV_LOG(ERR, "Failed to create CQ for Rearm Queue.");
252 wq->sq_size = MLX5_TXPP_REARM_SQ_SIZE;
253 MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));
254 /* Create send queue object for Rearm Queue. */
255 sq_attr.cqn = wq->cq_obj.cq->id;
256 /* There should be no WQE leftovers in the cyclic queue. */
257 ret = mlx5_devx_sq_create(sh->cdev->ctx, &wq->sq_obj,
258 log2above(MLX5_TXPP_REARM_SQ_SIZE), &sq_attr,
262 DRV_LOG(ERR, "Failed to create SQ for Rearm Queue.");
265 /* Build the WQEs in the Send Queue before goto Ready state. */
266 mlx5_txpp_fill_wqe_rearm_queue(sh);
267 /* Change queue state to ready. */
268 msq_attr.sq_state = MLX5_SQC_STATE_RST;
269 msq_attr.state = MLX5_SQC_STATE_RDY;
270 ret = mlx5_devx_cmd_modify_sq(wq->sq_obj.sq, &msq_attr);
272 DRV_LOG(ERR, "Failed to set SQ ready state Rearm Queue.");
278 mlx5_txpp_destroy_rearm_queue(sh);
284 mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh)
286 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
287 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes;
288 struct mlx5_wqe_cseg *cs = &wqe->cseg;
289 uint32_t wqe_size, opcode, i;
292 /* For test purposes fill the WQ with SEND inline packet. */
294 wqe_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
296 2 * MLX5_WQE_ESEG_SIZE -
297 MLX5_ESEG_MIN_INLINE_SIZE,
299 opcode = MLX5_OPCODE_SEND;
301 wqe_size = MLX5_WSEG_SIZE;
302 opcode = MLX5_OPCODE_NOP;
304 cs->opcode = rte_cpu_to_be_32(opcode | 0); /* Index is ignored. */
305 cs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) |
306 (wqe_size / MLX5_WSEG_SIZE));
307 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS << MLX5_COMP_MODE_OFFSET);
308 cs->misc = RTE_BE32(0);
309 wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE);
311 struct mlx5_wqe_eseg *es = &wqe->eseg;
312 struct rte_ether_hdr *eth_hdr;
313 struct rte_ipv4_hdr *ip_hdr;
314 struct rte_udp_hdr *udp_hdr;
316 /* Build the inline test packet pattern. */
317 MLX5_ASSERT(wqe_size <= MLX5_WQE_SIZE_MAX);
318 MLX5_ASSERT(MLX5_TXPP_TEST_PKT_SIZE >=
319 (sizeof(struct rte_ether_hdr) +
320 sizeof(struct rte_ipv4_hdr)));
322 es->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
327 es->inline_hdr_sz = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE);
328 /* Build test packet L2 header (Ethernet). */
329 dst = (uint8_t *)&es->inline_data;
330 eth_hdr = (struct rte_ether_hdr *)dst;
331 rte_eth_random_addr(ð_hdr->dst_addr.addr_bytes[0]);
332 rte_eth_random_addr(ð_hdr->src_addr.addr_bytes[0]);
333 eth_hdr->ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
334 /* Build test packet L3 header (IP v4). */
335 dst += sizeof(struct rte_ether_hdr);
336 ip_hdr = (struct rte_ipv4_hdr *)dst;
337 ip_hdr->version_ihl = RTE_IPV4_VHL_DEF;
338 ip_hdr->type_of_service = 0;
339 ip_hdr->fragment_offset = 0;
340 ip_hdr->time_to_live = 64;
341 ip_hdr->next_proto_id = IPPROTO_UDP;
342 ip_hdr->packet_id = 0;
343 ip_hdr->total_length = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE -
344 sizeof(struct rte_ether_hdr));
345 /* use RFC5735 / RFC2544 reserved network test addresses */
346 ip_hdr->src_addr = RTE_BE32((198U << 24) | (18 << 16) |
348 ip_hdr->dst_addr = RTE_BE32((198U << 24) | (18 << 16) |
350 if (MLX5_TXPP_TEST_PKT_SIZE <
351 (sizeof(struct rte_ether_hdr) +
352 sizeof(struct rte_ipv4_hdr) +
353 sizeof(struct rte_udp_hdr)))
355 /* Build test packet L4 header (UDP). */
356 dst += sizeof(struct rte_ipv4_hdr);
357 udp_hdr = (struct rte_udp_hdr *)dst;
358 udp_hdr->src_port = RTE_BE16(9); /* RFC863 Discard. */
359 udp_hdr->dst_port = RTE_BE16(9);
360 udp_hdr->dgram_len = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE -
361 sizeof(struct rte_ether_hdr) -
362 sizeof(struct rte_ipv4_hdr));
363 udp_hdr->dgram_cksum = 0;
364 /* Fill the test packet data. */
365 dst += sizeof(struct rte_udp_hdr);
366 for (i = sizeof(struct rte_ether_hdr) +
367 sizeof(struct rte_ipv4_hdr) +
368 sizeof(struct rte_udp_hdr);
369 i < MLX5_TXPP_TEST_PKT_SIZE; i++)
370 *dst++ = (uint8_t)(i & 0xFF);
373 /* Duplicate the pattern to the next WQEs. */
374 dst = (uint8_t *)(uintptr_t)wq->sq_obj.umem_buf;
375 for (i = 1; i < MLX5_TXPP_CLKQ_SIZE; i++) {
377 rte_memcpy(dst, (void *)(uintptr_t)wq->sq_obj.umem_buf,
382 /* Creates the Clock Queue for packet pacing, returns zero on success. */
384 mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)
386 struct mlx5_devx_create_sq_attr sq_attr = { 0 };
387 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
388 struct mlx5_devx_cq_attr cq_attr = {
391 .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar.obj),
393 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
396 sh->txpp.tsa = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
397 MLX5_TXPP_REARM_SQ_SIZE *
398 sizeof(struct mlx5_txpp_ts),
401 DRV_LOG(ERR, "Failed to allocate memory for CQ stats.");
406 /* Create completion queue object for Clock Queue. */
407 ret = mlx5_devx_cq_create(sh->cdev->ctx, &wq->cq_obj,
408 log2above(MLX5_TXPP_CLKQ_SIZE), &cq_attr,
411 DRV_LOG(ERR, "Failed to create CQ for Clock Queue.");
415 /* Allocate memory buffer for Send Queue WQEs. */
417 wq->sq_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
419 2 * MLX5_WQE_ESEG_SIZE -
420 MLX5_ESEG_MIN_INLINE_SIZE,
421 MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
422 wq->sq_size *= MLX5_TXPP_CLKQ_SIZE;
424 wq->sq_size = MLX5_TXPP_CLKQ_SIZE;
426 /* There should not be WQE leftovers in the cyclic queue. */
427 MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));
428 /* Create send queue object for Clock Queue. */
430 sq_attr.tis_lst_sz = 1;
431 sq_attr.tis_num = sh->tis[0]->id;
432 sq_attr.non_wire = 0;
433 sq_attr.static_sq_wq = 1;
435 sq_attr.non_wire = 1;
436 sq_attr.static_sq_wq = 1;
438 sq_attr.cqn = wq->cq_obj.cq->id;
439 sq_attr.packet_pacing_rate_limit_index = sh->txpp.pp_id;
440 sq_attr.wq_attr.cd_slave = 1;
441 sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar.obj);
442 sq_attr.wq_attr.pd = sh->cdev->pdn;
444 mlx5_ts_format_conv(sh->cdev->config.hca_attr.sq_ts_format);
445 ret = mlx5_devx_sq_create(sh->cdev->ctx, &wq->sq_obj,
446 log2above(wq->sq_size),
447 &sq_attr, sh->numa_node);
450 DRV_LOG(ERR, "Failed to create SQ for Clock Queue.");
453 /* Build the WQEs in the Send Queue before goto Ready state. */
454 mlx5_txpp_fill_wqe_clock_queue(sh);
455 /* Change queue state to ready. */
456 msq_attr.sq_state = MLX5_SQC_STATE_RST;
457 msq_attr.state = MLX5_SQC_STATE_RDY;
459 ret = mlx5_devx_cmd_modify_sq(wq->sq_obj.sq, &msq_attr);
461 DRV_LOG(ERR, "Failed to set SQ ready state Clock Queue.");
467 mlx5_txpp_destroy_clock_queue(sh);
472 /* Enable notification from the Rearm Queue CQ. */
474 mlx5_txpp_cq_arm(struct mlx5_dev_ctx_shared *sh)
476 struct mlx5_txpp_wq *aq = &sh->txpp.rearm_queue;
477 uint32_t arm_sn = aq->arm_sn << MLX5_CQ_SQN_OFFSET;
478 uint32_t db_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | aq->cq_ci;
480 rte_cpu_to_be_64(((uint64_t)db_hi << 32) | aq->cq_obj.cq->id);
482 mlx5_doorbell_ring(&sh->tx_uar.cq_db, db_be, db_hi,
483 &aq->cq_obj.db_rec[MLX5_CQ_ARM_DB], 0);
487 #if defined(RTE_ARCH_X86_64)
489 mlx5_atomic128_compare_exchange(rte_int128_t *dst,
491 const rte_int128_t *src)
495 asm volatile (MPLOCKED
498 : [dst] "=m" (dst->val[0]),
514 mlx5_atomic_read_cqe(rte_int128_t *from, rte_int128_t *ts)
517 * The only CQE of Clock Queue is being continuously
518 * updated by hardware with specified rate. We must
519 * read timestamp and WQE completion index atomically.
521 #if defined(RTE_ARCH_X86_64)
524 memset(&src, 0, sizeof(src));
526 /* if (*from == *ts) *from = *src else *ts = *from; */
527 mlx5_atomic128_compare_exchange(from, ts, &src);
529 uint64_t *cqe = (uint64_t *)from;
532 * Power architecture does not support 16B compare-and-swap.
533 * ARM implements it in software, code below is more relevant.
539 rte_compiler_barrier();
540 tm = __atomic_load_n(cqe + 0, __ATOMIC_RELAXED);
541 op = __atomic_load_n(cqe + 1, __ATOMIC_RELAXED);
542 rte_compiler_barrier();
543 if (tm != __atomic_load_n(cqe + 0, __ATOMIC_RELAXED))
545 if (op != __atomic_load_n(cqe + 1, __ATOMIC_RELAXED))
555 /* Stores timestamp in the cache structure to share data with datapath. */
557 mlx5_txpp_cache_timestamp(struct mlx5_dev_ctx_shared *sh,
558 uint64_t ts, uint64_t ci)
560 ci = ci << (64 - MLX5_CQ_INDEX_WIDTH);
561 ci |= (ts << MLX5_CQ_INDEX_WIDTH) >> MLX5_CQ_INDEX_WIDTH;
562 rte_compiler_barrier();
563 __atomic_store_n(&sh->txpp.ts.ts, ts, __ATOMIC_RELAXED);
564 __atomic_store_n(&sh->txpp.ts.ci_ts, ci, __ATOMIC_RELAXED);
568 /* Reads timestamp from Clock Queue CQE and stores in the cache. */
570 mlx5_txpp_update_timestamp(struct mlx5_dev_ctx_shared *sh)
572 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
573 struct mlx5_cqe *cqe = (struct mlx5_cqe *)(uintptr_t)wq->cq_obj.cqes;
576 struct mlx5_cqe_ts cts;
582 mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128);
583 opcode = MLX5_CQE_OPCODE(to.cts.op_own);
585 if (opcode != MLX5_CQE_INVALID) {
587 * Commit the error state if and only if
588 * we have got at least one actual completion.
591 "Clock Queue error sync lost (%X).", opcode);
592 __atomic_fetch_add(&sh->txpp.err_clock_queue,
593 1, __ATOMIC_RELAXED);
594 sh->txpp.sync_lost = 1;
598 ci = rte_be_to_cpu_16(to.cts.wqe_counter);
599 ts = rte_be_to_cpu_64(to.cts.timestamp);
600 ts = mlx5_txpp_convert_rx_ts(sh, ts);
601 wq->cq_ci += (ci - wq->sq_ci) & UINT16_MAX;
603 mlx5_txpp_cache_timestamp(sh, ts, wq->cq_ci);
606 /* Waits for the first completion on Clock Queue to init timestamp. */
608 mlx5_txpp_init_timestamp(struct mlx5_dev_ctx_shared *sh)
610 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
615 for (wait = 0; wait < MLX5_TXPP_WAIT_INIT_TS; wait++) {
616 mlx5_txpp_update_timestamp(sh);
619 /* Wait one millisecond and try again. */
620 rte_delay_us_sleep(US_PER_S / MS_PER_S);
622 DRV_LOG(ERR, "Unable to initialize timestamp.");
623 sh->txpp.sync_lost = 1;
626 #ifdef HAVE_IBV_DEVX_EVENT
627 /* Gather statistics for timestamp from Clock Queue CQE. */
629 mlx5_txpp_gather_timestamp(struct mlx5_dev_ctx_shared *sh)
631 /* Check whether we have a valid timestamp. */
632 if (!sh->txpp.clock_queue.sq_ci && !sh->txpp.ts_n)
634 MLX5_ASSERT(sh->txpp.ts_p < MLX5_TXPP_REARM_SQ_SIZE);
635 __atomic_store_n(&sh->txpp.tsa[sh->txpp.ts_p].ts,
636 sh->txpp.ts.ts, __ATOMIC_RELAXED);
637 __atomic_store_n(&sh->txpp.tsa[sh->txpp.ts_p].ci_ts,
638 sh->txpp.ts.ci_ts, __ATOMIC_RELAXED);
639 if (++sh->txpp.ts_p >= MLX5_TXPP_REARM_SQ_SIZE)
641 if (sh->txpp.ts_n < MLX5_TXPP_REARM_SQ_SIZE)
645 /* Handles Rearm Queue completions in periodic service. */
646 static __rte_always_inline void
647 mlx5_txpp_handle_rearm_queue(struct mlx5_dev_ctx_shared *sh)
649 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
650 uint32_t cq_ci = wq->cq_ci;
655 volatile struct mlx5_cqe *cqe;
657 cqe = &wq->cq_obj.cqes[cq_ci & (MLX5_TXPP_REARM_CQ_SIZE - 1)];
658 ret = check_cqe(cqe, MLX5_TXPP_REARM_CQ_SIZE, cq_ci);
660 case MLX5_CQE_STATUS_ERR:
664 case MLX5_CQE_STATUS_SW_OWN:
668 case MLX5_CQE_STATUS_HW_OWN:
674 } while (ret != MLX5_CQE_STATUS_HW_OWN);
675 if (likely(cq_ci != wq->cq_ci)) {
676 /* Check whether we have missed interrupts. */
677 if (cq_ci - wq->cq_ci != 1) {
678 DRV_LOG(DEBUG, "Rearm Queue missed interrupt.");
679 __atomic_fetch_add(&sh->txpp.err_miss_int,
680 1, __ATOMIC_RELAXED);
681 /* Check sync lost on wqe index. */
682 if (cq_ci - wq->cq_ci >=
683 (((1UL << MLX5_WQ_INDEX_WIDTH) /
684 MLX5_TXPP_REARM) - 1))
687 /* Update doorbell record to notify hardware. */
688 rte_compiler_barrier();
689 *wq->cq_obj.db_rec = rte_cpu_to_be_32(cq_ci);
692 /* Fire new requests to Rearm Queue. */
694 DRV_LOG(DEBUG, "Rearm Queue error sync lost.");
695 __atomic_fetch_add(&sh->txpp.err_rearm_queue,
696 1, __ATOMIC_RELAXED);
697 sh->txpp.sync_lost = 1;
702 /* Handles Clock Queue completions in periodic service. */
703 static __rte_always_inline void
704 mlx5_txpp_handle_clock_queue(struct mlx5_dev_ctx_shared *sh)
706 mlx5_txpp_update_timestamp(sh);
707 mlx5_txpp_gather_timestamp(sh);
711 /* Invoked periodically on Rearm Queue completions. */
713 mlx5_txpp_interrupt_handler(void *cb_arg)
715 #ifndef HAVE_IBV_DEVX_EVENT
716 RTE_SET_USED(cb_arg);
719 struct mlx5_dev_ctx_shared *sh = cb_arg;
721 struct mlx5dv_devx_async_event_hdr event_resp;
722 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
725 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
726 /* Process events in the loop. Only rearm completions are expected. */
727 while (mlx5_glue->devx_get_event
731 (ssize_t)sizeof(out.event_resp.cookie)) {
732 mlx5_txpp_handle_rearm_queue(sh);
733 mlx5_txpp_handle_clock_queue(sh);
734 mlx5_txpp_cq_arm(sh);
735 mlx5_txpp_doorbell_rearm_queue
736 (sh, sh->txpp.rearm_queue.sq_ci - 1);
738 #endif /* HAVE_IBV_DEVX_ASYNC */
742 mlx5_txpp_stop_service(struct mlx5_dev_ctx_shared *sh)
744 if (!rte_intr_fd_get(sh->txpp.intr_handle))
746 mlx5_intr_callback_unregister(sh->txpp.intr_handle,
747 mlx5_txpp_interrupt_handler, sh);
748 rte_intr_instance_free(sh->txpp.intr_handle);
751 /* Attach interrupt handler and fires first request to Rearm Queue. */
753 mlx5_txpp_start_service(struct mlx5_dev_ctx_shared *sh)
755 uint16_t event_nums[1] = {0};
759 sh->txpp.err_miss_int = 0;
760 sh->txpp.err_rearm_queue = 0;
761 sh->txpp.err_clock_queue = 0;
762 sh->txpp.err_ts_past = 0;
763 sh->txpp.err_ts_future = 0;
764 /* Attach interrupt handler to process Rearm Queue completions. */
765 fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan);
766 ret = mlx5_os_set_nonblock_channel_fd(fd);
768 DRV_LOG(ERR, "Failed to change event channel FD.");
772 sh->txpp.intr_handle =
773 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
774 if (sh->txpp.intr_handle == NULL) {
775 DRV_LOG(ERR, "Fail to allocate intr_handle");
778 fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan);
779 if (rte_intr_fd_set(sh->txpp.intr_handle, fd))
782 if (rte_intr_type_set(sh->txpp.intr_handle, RTE_INTR_HANDLE_EXT))
785 if (rte_intr_callback_register(sh->txpp.intr_handle,
786 mlx5_txpp_interrupt_handler, sh)) {
787 rte_intr_fd_set(sh->txpp.intr_handle, 0);
788 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
791 /* Subscribe CQ event to the event channel controlled by the driver. */
792 ret = mlx5_os_devx_subscribe_devx_event(sh->txpp.echan,
793 sh->txpp.rearm_queue.cq_obj.cq->obj,
794 sizeof(event_nums), event_nums, 0);
796 DRV_LOG(ERR, "Failed to subscribe CQE event.");
800 /* Enable interrupts in the CQ. */
801 mlx5_txpp_cq_arm(sh);
802 /* Fire the first request on Rearm Queue. */
803 mlx5_txpp_doorbell_rearm_queue(sh, sh->txpp.rearm_queue.sq_size - 1);
804 mlx5_txpp_init_timestamp(sh);
809 * The routine initializes the packet pacing infrastructure:
810 * - allocates PP context
813 * - attaches rearm interrupt handler
814 * - starts Clock Queue
816 * Returns 0 on success, negative otherwise
819 mlx5_txpp_create(struct mlx5_dev_ctx_shared *sh)
821 int tx_pp = sh->config.tx_pp;
824 /* Store the requested pacing parameters. */
825 sh->txpp.tick = tx_pp >= 0 ? tx_pp : -tx_pp;
826 sh->txpp.test = !!(tx_pp < 0);
827 sh->txpp.skew = sh->config.tx_skew;
828 sh->txpp.freq = sh->cdev->config.hca_attr.dev_freq_khz;
829 ret = mlx5_txpp_create_event_channel(sh);
832 ret = mlx5_txpp_alloc_pp_index(sh);
835 ret = mlx5_txpp_create_clock_queue(sh);
838 ret = mlx5_txpp_create_rearm_queue(sh);
841 ret = mlx5_txpp_start_service(sh);
846 mlx5_txpp_stop_service(sh);
847 mlx5_txpp_destroy_rearm_queue(sh);
848 mlx5_txpp_destroy_clock_queue(sh);
849 mlx5_txpp_free_pp_index(sh);
850 mlx5_txpp_destroy_event_channel(sh);
859 * The routine destroys the packet pacing infrastructure:
860 * - detaches rearm interrupt handler
866 mlx5_txpp_destroy(struct mlx5_dev_ctx_shared *sh)
868 mlx5_txpp_stop_service(sh);
869 mlx5_txpp_destroy_rearm_queue(sh);
870 mlx5_txpp_destroy_clock_queue(sh);
871 mlx5_txpp_free_pp_index(sh);
872 mlx5_txpp_destroy_event_channel(sh);
879 * Creates and starts packet pacing infrastructure on specified device.
882 * Pointer to Ethernet device structure.
885 * 0 on success, a negative errno value otherwise and rte_errno is set.
888 mlx5_txpp_start(struct rte_eth_dev *dev)
890 struct mlx5_priv *priv = dev->data->dev_private;
891 struct mlx5_dev_ctx_shared *sh = priv->sh;
894 if (!sh->config.tx_pp) {
895 /* Packet pacing is not requested for the device. */
896 MLX5_ASSERT(priv->txpp_en == 0);
900 /* Packet pacing is already enabled for the device. */
901 MLX5_ASSERT(sh->txpp.refcnt);
904 if (sh->config.tx_pp > 0) {
905 err = rte_mbuf_dynflag_lookup
906 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
907 /* No flag registered means no service needed. */
912 claim_zero(pthread_mutex_lock(&sh->txpp.mutex));
913 if (sh->txpp.refcnt) {
917 err = mlx5_txpp_create(sh);
919 MLX5_ASSERT(sh->txpp.tick);
926 claim_zero(pthread_mutex_unlock(&sh->txpp.mutex));
931 * Stops and destroys packet pacing infrastructure on specified device.
934 * Pointer to Ethernet device structure.
937 * 0 on success, a negative errno value otherwise and rte_errno is set.
940 mlx5_txpp_stop(struct rte_eth_dev *dev)
942 struct mlx5_priv *priv = dev->data->dev_private;
943 struct mlx5_dev_ctx_shared *sh = priv->sh;
945 if (!priv->txpp_en) {
946 /* Packet pacing is already disabled for the device. */
950 claim_zero(pthread_mutex_lock(&sh->txpp.mutex));
951 MLX5_ASSERT(sh->txpp.refcnt);
952 if (!sh->txpp.refcnt || --sh->txpp.refcnt) {
953 claim_zero(pthread_mutex_unlock(&sh->txpp.mutex));
956 /* No references any more, do actual destroy. */
957 mlx5_txpp_destroy(sh);
958 claim_zero(pthread_mutex_unlock(&sh->txpp.mutex));
962 * Read the current clock counter of an Ethernet device
964 * This returns the current raw clock value of an Ethernet device. It is
965 * a raw amount of ticks, with no given time reference.
966 * The value returned here is from the same clock than the one
967 * filling timestamp field of Rx/Tx packets when using hardware timestamp
968 * offload. Therefore it can be used to compute a precise conversion of
969 * the device clock to the real time.
972 * Pointer to Ethernet device structure.
974 * Pointer to the uint64_t that holds the raw clock value.
978 * - -ENOTSUP: The function is not supported in this mode. Requires
979 * packet pacing module configured and started (tx_pp devarg)
982 mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp)
984 struct mlx5_priv *priv = dev->data->dev_private;
985 struct mlx5_dev_ctx_shared *sh = priv->sh;
988 if (sh->txpp.refcnt) {
989 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
990 struct mlx5_cqe *cqe =
991 (struct mlx5_cqe *)(uintptr_t)wq->cq_obj.cqes;
994 struct mlx5_cqe_ts cts;
998 mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128);
999 if (to.cts.op_own >> 4) {
1000 DRV_LOG(DEBUG, "Clock Queue error sync lost.");
1001 __atomic_fetch_add(&sh->txpp.err_clock_queue,
1002 1, __ATOMIC_RELAXED);
1003 sh->txpp.sync_lost = 1;
1006 ts = rte_be_to_cpu_64(to.cts.timestamp);
1007 ts = mlx5_txpp_convert_rx_ts(sh, ts);
1011 /* Not supported in isolated mode - kernel does not see the CQEs. */
1012 if (priv->isolated || rte_eal_process_type() != RTE_PROC_PRIMARY)
1014 ret = mlx5_read_clock(dev, timestamp);
1019 * DPDK callback to clear device extended statistics.
1022 * Pointer to Ethernet device structure.
1025 * 0 on success and stats is reset, negative errno value otherwise and
1028 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev)
1030 struct mlx5_priv *priv = dev->data->dev_private;
1031 struct mlx5_dev_ctx_shared *sh = priv->sh;
1033 __atomic_store_n(&sh->txpp.err_miss_int, 0, __ATOMIC_RELAXED);
1034 __atomic_store_n(&sh->txpp.err_rearm_queue, 0, __ATOMIC_RELAXED);
1035 __atomic_store_n(&sh->txpp.err_clock_queue, 0, __ATOMIC_RELAXED);
1036 __atomic_store_n(&sh->txpp.err_ts_past, 0, __ATOMIC_RELAXED);
1037 __atomic_store_n(&sh->txpp.err_ts_future, 0, __ATOMIC_RELAXED);
1042 * Routine to retrieve names of extended device statistics
1043 * for packet send scheduling. It appends the specific stats names
1044 * after the parts filled by preceding modules (eth stats, etc.)
1047 * Pointer to Ethernet device structure.
1048 * @param[out] xstats_names
1049 * Buffer to insert names into.
1053 * Number of names filled by preceding statistics modules.
1056 * Number of xstats names.
1058 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1059 struct rte_eth_xstat_name *xstats_names,
1060 unsigned int n, unsigned int n_used)
1062 unsigned int n_txpp = RTE_DIM(mlx5_txpp_stat_names);
1065 if (n >= n_used + n_txpp && xstats_names) {
1066 for (i = 0; i < n_txpp; ++i) {
1067 strncpy(xstats_names[i + n_used].name,
1068 mlx5_txpp_stat_names[i],
1069 RTE_ETH_XSTATS_NAME_SIZE);
1070 xstats_names[i + n_used].name
1071 [RTE_ETH_XSTATS_NAME_SIZE - 1] = 0;
1074 return n_used + n_txpp;
1078 mlx5_txpp_read_tsa(struct mlx5_dev_txpp *txpp,
1079 struct mlx5_txpp_ts *tsa, uint16_t idx)
1084 ts = __atomic_load_n(&txpp->tsa[idx].ts, __ATOMIC_RELAXED);
1085 ci = __atomic_load_n(&txpp->tsa[idx].ci_ts, __ATOMIC_RELAXED);
1086 rte_compiler_barrier();
1087 if ((ci ^ ts) << MLX5_CQ_INDEX_WIDTH != 0)
1089 if (__atomic_load_n(&txpp->tsa[idx].ts,
1090 __ATOMIC_RELAXED) != ts)
1092 if (__atomic_load_n(&txpp->tsa[idx].ci_ts,
1093 __ATOMIC_RELAXED) != ci)
1102 * Jitter reflects the clock change between
1103 * neighbours Clock Queue completions.
1106 mlx5_txpp_xstats_jitter(struct mlx5_dev_txpp *txpp)
1108 struct mlx5_txpp_ts tsa0, tsa1;
1112 if (txpp->ts_n < 2) {
1113 /* No gathered enough reports yet. */
1120 rte_compiler_barrier();
1123 ts_0 += MLX5_TXPP_REARM_SQ_SIZE;
1126 ts_1 += MLX5_TXPP_REARM_SQ_SIZE;
1127 mlx5_txpp_read_tsa(txpp, &tsa0, ts_0);
1128 mlx5_txpp_read_tsa(txpp, &tsa1, ts_1);
1129 rte_compiler_barrier();
1130 } while (ts_p != txpp->ts_p);
1131 /* We have two neighbor reports, calculate the jitter. */
1132 dts = tsa1.ts - tsa0.ts;
1133 dci = (tsa1.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH)) -
1134 (tsa0.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH));
1136 dci += 1 << MLX5_CQ_INDEX_WIDTH;
1138 return (dts > dci) ? dts - dci : dci - dts;
1142 * Wander reflects the long-term clock change
1143 * over the entire length of all Clock Queue completions.
1146 mlx5_txpp_xstats_wander(struct mlx5_dev_txpp *txpp)
1148 struct mlx5_txpp_ts tsa0, tsa1;
1152 if (txpp->ts_n < MLX5_TXPP_REARM_SQ_SIZE) {
1153 /* No gathered enough reports yet. */
1160 rte_compiler_barrier();
1161 ts_0 = ts_p - MLX5_TXPP_REARM_SQ_SIZE / 2 - 1;
1163 ts_0 += MLX5_TXPP_REARM_SQ_SIZE;
1166 ts_1 += MLX5_TXPP_REARM_SQ_SIZE;
1167 mlx5_txpp_read_tsa(txpp, &tsa0, ts_0);
1168 mlx5_txpp_read_tsa(txpp, &tsa1, ts_1);
1169 rte_compiler_barrier();
1170 } while (ts_p != txpp->ts_p);
1171 /* We have two neighbor reports, calculate the jitter. */
1172 dts = tsa1.ts - tsa0.ts;
1173 dci = (tsa1.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH)) -
1174 (tsa0.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH));
1175 dci += 1 << MLX5_CQ_INDEX_WIDTH;
1177 return (dts > dci) ? dts - dci : dci - dts;
1181 * Routine to retrieve extended device statistics
1182 * for packet send scheduling. It appends the specific statistics
1183 * after the parts filled by preceding modules (eth stats, etc.)
1186 * Pointer to Ethernet device.
1188 * Pointer to rte extended stats table.
1190 * The size of the stats table.
1192 * Number of stats filled by preceding statistics modules.
1195 * Number of extended stats on success and stats is filled,
1196 * negative on error and rte_errno is set.
1199 mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1200 struct rte_eth_xstat *stats,
1201 unsigned int n, unsigned int n_used)
1203 unsigned int n_txpp = RTE_DIM(mlx5_txpp_stat_names);
1205 if (n >= n_used + n_txpp && stats) {
1206 struct mlx5_priv *priv = dev->data->dev_private;
1207 struct mlx5_dev_ctx_shared *sh = priv->sh;
1210 for (i = 0; i < n_txpp; ++i)
1211 stats[n_used + i].id = n_used + i;
1212 stats[n_used + 0].value =
1213 __atomic_load_n(&sh->txpp.err_miss_int,
1215 stats[n_used + 1].value =
1216 __atomic_load_n(&sh->txpp.err_rearm_queue,
1218 stats[n_used + 2].value =
1219 __atomic_load_n(&sh->txpp.err_clock_queue,
1221 stats[n_used + 3].value =
1222 __atomic_load_n(&sh->txpp.err_ts_past,
1224 stats[n_used + 4].value =
1225 __atomic_load_n(&sh->txpp.err_ts_future,
1227 stats[n_used + 5].value = mlx5_txpp_xstats_jitter(&sh->txpp);
1228 stats[n_used + 6].value = mlx5_txpp_xstats_wander(&sh->txpp);
1229 stats[n_used + 7].value = sh->txpp.sync_lost;
1231 return n_used + n_txpp;