4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
47 #pragma GCC diagnostic error "-Wpedantic"
50 /* DPDK headers don't like -pedantic. */
52 #pragma GCC diagnostic ignored "-Wpedantic"
55 #include <rte_malloc.h>
56 #include <rte_ethdev.h>
57 #include <rte_common.h>
59 #pragma GCC diagnostic error "-Wpedantic"
62 #include "mlx5_utils.h"
63 #include "mlx5_defs.h"
65 #include "mlx5_rxtx.h"
66 #include "mlx5_autoconf.h"
67 #include "mlx5_defs.h"
70 * Allocate TX queue elements.
73 * Pointer to TX queue structure.
75 * Number of elements to allocate.
78 txq_alloc_elts(struct txq_ctrl *txq_ctrl, unsigned int elts_n)
82 for (i = 0; (i != elts_n); ++i)
83 (*txq_ctrl->txq.elts)[i] = NULL;
84 for (i = 0; (i != (1u << txq_ctrl->txq.wqe_n)); ++i) {
85 volatile struct mlx5_wqe64 *wqe =
86 (volatile struct mlx5_wqe64 *)
87 txq_ctrl->txq.wqes + i;
89 memset((void *)(uintptr_t)wqe, 0x0, sizeof(*wqe));
91 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
92 txq_ctrl->txq.elts_head = 0;
93 txq_ctrl->txq.elts_tail = 0;
94 txq_ctrl->txq.elts_comp = 0;
98 * Free TX queue elements.
101 * Pointer to TX queue structure.
104 txq_free_elts(struct txq_ctrl *txq_ctrl)
106 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
107 const uint16_t elts_m = elts_n - 1;
108 uint16_t elts_head = txq_ctrl->txq.elts_head;
109 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
110 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
112 DEBUG("%p: freeing WRs", (void *)txq_ctrl);
113 txq_ctrl->txq.elts_head = 0;
114 txq_ctrl->txq.elts_tail = 0;
115 txq_ctrl->txq.elts_comp = 0;
117 while (elts_tail != elts_head) {
118 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
121 rte_pktmbuf_free_seg(elt);
124 memset(&(*elts)[elts_tail & elts_m],
126 sizeof((*elts)[elts_tail & elts_m]));
133 * Clean up a TX queue.
135 * Destroy objects, free allocated memory and reset the structure for reuse.
138 * Pointer to TX queue structure.
141 txq_cleanup(struct txq_ctrl *txq_ctrl)
145 DEBUG("cleaning up %p", (void *)txq_ctrl);
146 txq_free_elts(txq_ctrl);
147 if (txq_ctrl->qp != NULL)
148 claim_zero(ibv_destroy_qp(txq_ctrl->qp));
149 if (txq_ctrl->cq != NULL)
150 claim_zero(ibv_destroy_cq(txq_ctrl->cq));
151 for (i = 0; (i != RTE_DIM(txq_ctrl->txq.mp2mr)); ++i) {
152 if (txq_ctrl->txq.mp2mr[i].mr == NULL)
154 claim_zero(ibv_dereg_mr(txq_ctrl->txq.mp2mr[i].mr));
156 memset(txq_ctrl, 0, sizeof(*txq_ctrl));
160 * Initialize TX queue.
163 * Pointer to TX queue control template.
165 * Pointer to TX queue control.
168 * 0 on success, errno value on failure.
171 txq_setup(struct txq_ctrl *tmpl, struct txq_ctrl *txq_ctrl)
173 struct mlx5_qp *qp = to_mqp(tmpl->qp);
174 struct ibv_cq *ibcq = tmpl->cq;
175 struct ibv_mlx5_cq_info cq_info;
177 if (ibv_mlx5_exp_get_cq_info(ibcq, &cq_info)) {
178 ERROR("Unable to query CQ info. check your OFED.");
181 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
182 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
183 "it should be set to %u", RTE_CACHE_LINE_SIZE);
186 tmpl->txq.cqe_n = log2above(cq_info.cqe_cnt);
187 tmpl->txq.qp_num_8s = qp->ctrl_seg.qp_num << 8;
188 tmpl->txq.wqes = qp->gen_data.sqstart;
189 tmpl->txq.wqe_n = log2above(qp->sq.wqe_cnt);
190 tmpl->txq.qp_db = &qp->gen_data.db[MLX5_SND_DBR];
191 tmpl->txq.bf_reg = qp->gen_data.bf->reg;
192 tmpl->txq.cq_db = cq_info.dbrec;
194 (volatile struct mlx5_cqe (*)[])
195 (uintptr_t)cq_info.buf;
197 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])
198 ((uintptr_t)txq_ctrl + sizeof(*txq_ctrl));
203 * Configure a TX queue.
206 * Pointer to Ethernet device structure.
208 * Pointer to TX queue structure.
210 * Number of descriptors to configure in queue.
212 * NUMA socket on which memory must be allocated.
214 * Thresholds parameters.
217 * 0 on success, errno value on failure.
220 txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,
221 uint16_t desc, unsigned int socket,
222 const struct rte_eth_txconf *conf)
224 struct priv *priv = mlx5_get_priv(dev);
225 struct txq_ctrl tmpl = {
230 struct ibv_exp_qp_init_attr init;
231 struct ibv_exp_cq_init_attr cq;
232 struct ibv_exp_qp_attr mod;
233 struct ibv_exp_cq_attr cq_attr;
236 const unsigned int max_tso_inline = ((MLX5_MAX_TSO_HEADER +
237 (RTE_CACHE_LINE_SIZE - 1)) /
238 RTE_CACHE_LINE_SIZE);
241 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
243 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set");
246 (void)conf; /* Thresholds configuration (ignored). */
247 assert(desc > MLX5_TX_COMP_THRESH);
248 tmpl.txq.elts_n = log2above(desc);
249 if (priv->mps == MLX5_MPW_ENHANCED)
250 tmpl.txq.mpw_hdr_dseg = priv->mpw_hdr_dseg;
251 /* MRs will be registered in mp2mr[] later. */
252 attr.cq = (struct ibv_exp_cq_init_attr){
255 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
256 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
257 if (priv->mps == MLX5_MPW_ENHANCED)
258 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
259 tmpl.cq = ibv_exp_create_cq(priv->ctx,
261 NULL, NULL, 0, &attr.cq);
262 if (tmpl.cq == NULL) {
264 ERROR("%p: CQ creation failure: %s",
265 (void *)dev, strerror(ret));
268 DEBUG("priv->device_attr.max_qp_wr is %d",
269 priv->device_attr.max_qp_wr);
270 DEBUG("priv->device_attr.max_sge is %d",
271 priv->device_attr.max_sge);
272 attr.init = (struct ibv_exp_qp_init_attr){
273 /* CQ to be associated with the send queue. */
275 /* CQ to be associated with the receive queue. */
278 /* Max number of outstanding WRs. */
279 .max_send_wr = ((priv->device_attr.max_qp_wr < desc) ?
280 priv->device_attr.max_qp_wr :
283 * Max number of scatter/gather elements in a WR,
284 * must be 1 to prevent libmlx5 from trying to affect
285 * too much memory. TX gather is not impacted by the
286 * priv->device_attr.max_sge limit and will still work
291 .qp_type = IBV_QPT_RAW_PACKET,
292 /* Do *NOT* enable this, completions events are managed per
296 .comp_mask = IBV_EXP_QP_INIT_ATTR_PD,
298 if (priv->txq_inline && (priv->txqs_n >= priv->txqs_inline)) {
299 tmpl.txq.max_inline =
300 ((priv->txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
301 RTE_CACHE_LINE_SIZE);
302 tmpl.txq.inline_en = 1;
303 /* TSO and MPS can't be enabled concurrently. */
304 assert(!priv->tso || !priv->mps);
305 if (priv->mps == MLX5_MPW_ENHANCED) {
306 tmpl.txq.inline_max_packet_sz =
307 priv->inline_max_packet_sz;
308 /* To minimize the size of data set, avoid requesting
311 attr.init.cap.max_inline_data =
312 ((RTE_MIN(priv->txq_inline,
313 priv->inline_max_packet_sz) +
314 (RTE_CACHE_LINE_SIZE - 1)) /
315 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
316 } else if (priv->tso) {
317 int inline_diff = tmpl.txq.max_inline - max_tso_inline;
320 * Adjust inline value as Verbs aggregates
321 * tso_inline and txq_inline fields.
323 attr.init.cap.max_inline_data = inline_diff > 0 ?
325 RTE_CACHE_LINE_SIZE :
328 attr.init.cap.max_inline_data =
329 tmpl.txq.max_inline * RTE_CACHE_LINE_SIZE;
333 attr.init.max_tso_header =
334 max_tso_inline * RTE_CACHE_LINE_SIZE;
335 attr.init.comp_mask |= IBV_EXP_QP_INIT_ATTR_MAX_TSO_HEADER;
336 tmpl.txq.max_inline = RTE_MAX(tmpl.txq.max_inline,
341 tmpl.txq.tunnel_en = 1;
342 tmpl.qp = ibv_exp_create_qp(priv->ctx, &attr.init);
343 if (tmpl.qp == NULL) {
344 ret = (errno ? errno : EINVAL);
345 ERROR("%p: QP creation failure: %s",
346 (void *)dev, strerror(ret));
349 DEBUG("TX queue capabilities: max_send_wr=%u, max_send_sge=%u,"
350 " max_inline_data=%u",
351 attr.init.cap.max_send_wr,
352 attr.init.cap.max_send_sge,
353 attr.init.cap.max_inline_data);
354 attr.mod = (struct ibv_exp_qp_attr){
355 /* Move the QP to this state. */
356 .qp_state = IBV_QPS_INIT,
357 /* Primary port number. */
358 .port_num = priv->port
360 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod,
361 (IBV_EXP_QP_STATE | IBV_EXP_QP_PORT));
363 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
364 (void *)dev, strerror(ret));
367 ret = txq_setup(&tmpl, txq_ctrl);
369 ERROR("%p: cannot initialize TX queue structure: %s",
370 (void *)dev, strerror(ret));
373 txq_alloc_elts(&tmpl, desc);
374 attr.mod = (struct ibv_exp_qp_attr){
375 .qp_state = IBV_QPS_RTR
377 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
379 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
380 (void *)dev, strerror(ret));
383 attr.mod.qp_state = IBV_QPS_RTS;
384 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
386 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
387 (void *)dev, strerror(ret));
390 /* Clean up txq in case we're reinitializing it. */
391 DEBUG("%p: cleaning-up old txq just in case", (void *)txq_ctrl);
392 txq_cleanup(txq_ctrl);
394 DEBUG("%p: txq updated with %p", (void *)txq_ctrl, (void *)&tmpl);
395 /* Pre-register known mempools. */
396 rte_mempool_walk(txq_mp2mr_iter, txq_ctrl);
406 * DPDK callback to configure a TX queue.
409 * Pointer to Ethernet device structure.
413 * Number of descriptors to configure in queue.
415 * NUMA socket on which memory must be allocated.
417 * Thresholds parameters.
420 * 0 on success, negative errno value on failure.
423 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
424 unsigned int socket, const struct rte_eth_txconf *conf)
426 struct priv *priv = dev->data->dev_private;
427 struct txq *txq = (*priv->txqs)[idx];
428 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
431 if (mlx5_is_secondary())
432 return -E_RTE_SECONDARY;
435 if (desc <= MLX5_TX_COMP_THRESH) {
436 WARN("%p: number of descriptors requested for TX queue %u"
437 " must be higher than MLX5_TX_COMP_THRESH, using"
439 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
440 desc = MLX5_TX_COMP_THRESH + 1;
442 if (!rte_is_power_of_2(desc)) {
443 desc = 1 << log2above(desc);
444 WARN("%p: increased number of descriptors in TX queue %u"
445 " to the next power of two (%d)",
446 (void *)dev, idx, desc);
448 DEBUG("%p: configuring queue %u for %u descriptors",
449 (void *)dev, idx, desc);
450 if (idx >= priv->txqs_n) {
451 ERROR("%p: queue index out of range (%u >= %u)",
452 (void *)dev, idx, priv->txqs_n);
457 DEBUG("%p: reusing already allocated queue index %u (%p)",
458 (void *)dev, idx, (void *)txq);
463 (*priv->txqs)[idx] = NULL;
464 txq_cleanup(txq_ctrl);
465 /* Resize if txq size is changed. */
466 if (txq_ctrl->txq.elts_n != log2above(desc)) {
467 txq_ctrl = rte_realloc(txq_ctrl,
469 desc * sizeof(struct rte_mbuf *),
470 RTE_CACHE_LINE_SIZE);
472 ERROR("%p: unable to reallocate queue index %u",
480 rte_calloc_socket("TXQ", 1,
482 desc * sizeof(struct rte_mbuf *),
484 if (txq_ctrl == NULL) {
485 ERROR("%p: unable to allocate queue index %u",
491 ret = txq_ctrl_setup(dev, txq_ctrl, desc, socket, conf);
495 txq_ctrl->txq.stats.idx = idx;
496 DEBUG("%p: adding TX queue %p to list",
497 (void *)dev, (void *)txq_ctrl);
498 (*priv->txqs)[idx] = &txq_ctrl->txq;
505 * DPDK callback to release a TX queue.
508 * Generic TX queue pointer.
511 mlx5_tx_queue_release(void *dpdk_txq)
513 struct txq *txq = (struct txq *)dpdk_txq;
514 struct txq_ctrl *txq_ctrl;
518 if (mlx5_is_secondary())
523 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
524 priv = txq_ctrl->priv;
526 for (i = 0; (i != priv->txqs_n); ++i)
527 if ((*priv->txqs)[i] == txq) {
528 DEBUG("%p: removing TX queue %p from list",
529 (void *)priv->dev, (void *)txq_ctrl);
530 (*priv->txqs)[i] = NULL;
533 txq_cleanup(txq_ctrl);
539 * DPDK callback for TX in secondary processes.
541 * This function configures all queues from primary process information
542 * if necessary before reverting to the normal TX burst callback.
545 * Generic pointer to TX queue structure.
547 * Packets to transmit.
549 * Number of packets in array.
552 * Number of packets successfully transmitted (<= pkts_n).
555 mlx5_tx_burst_secondary_setup(void *dpdk_txq, struct rte_mbuf **pkts,
558 struct txq *txq = dpdk_txq;
559 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
560 struct priv *priv = mlx5_secondary_data_setup(txq_ctrl->priv);
561 struct priv *primary_priv;
567 mlx5_secondary_data[priv->dev->data->port_id].primary_priv;
568 /* Look for queue index in both private structures. */
569 for (index = 0; index != priv->txqs_n; ++index)
570 if (((*primary_priv->txqs)[index] == txq) ||
571 ((*priv->txqs)[index] == txq))
573 if (index == priv->txqs_n)
575 txq = (*priv->txqs)[index];
576 return priv->dev->tx_pkt_burst(txq, pkts, pkts_n);