1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <rte_malloc.h>
15 #include <ethdev_driver.h>
16 #include <rte_bus_pci.h>
17 #include <rte_common.h>
18 #include <rte_eal_paging.h>
20 #include <mlx5_common.h>
21 #include <mlx5_common_mr.h>
22 #include <mlx5_malloc.h>
24 #include "mlx5_defs.h"
25 #include "mlx5_utils.h"
28 #include "mlx5_rxtx.h"
29 #include "mlx5_autoconf.h"
32 * Allocate TX queue elements.
35 * Pointer to TX queue structure.
38 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
40 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
43 for (i = 0; (i != elts_n); ++i)
44 txq_ctrl->txq.elts[i] = NULL;
45 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
46 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx, elts_n);
47 txq_ctrl->txq.elts_head = 0;
48 txq_ctrl->txq.elts_tail = 0;
49 txq_ctrl->txq.elts_comp = 0;
53 * Free TX queue elements.
56 * Pointer to TX queue structure.
59 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
61 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
62 const uint16_t elts_m = elts_n - 1;
63 uint16_t elts_head = txq_ctrl->txq.elts_head;
64 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
65 struct rte_mbuf *(*elts)[elts_n] = &txq_ctrl->txq.elts;
67 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs",
68 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx);
69 txq_ctrl->txq.elts_head = 0;
70 txq_ctrl->txq.elts_tail = 0;
71 txq_ctrl->txq.elts_comp = 0;
73 while (elts_tail != elts_head) {
74 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
76 MLX5_ASSERT(elt != NULL);
77 rte_pktmbuf_free_seg(elt);
78 #ifdef RTE_LIBRTE_MLX5_DEBUG
80 memset(&(*elts)[elts_tail & elts_m],
82 sizeof((*elts)[elts_tail & elts_m]));
89 * Returns the per-port supported offloads.
92 * Pointer to Ethernet device.
95 * Supported Tx offloads.
98 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
100 struct mlx5_priv *priv = dev->data->dev_private;
101 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
102 DEV_TX_OFFLOAD_VLAN_INSERT);
103 struct mlx5_dev_config *config = &priv->config;
106 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
107 DEV_TX_OFFLOAD_UDP_CKSUM |
108 DEV_TX_OFFLOAD_TCP_CKSUM);
110 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
112 offloads |= DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP;
114 if (config->swp & MLX5_SW_PARSING_CSUM_CAP)
115 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
116 if (config->swp & MLX5_SW_PARSING_TSO_CAP)
117 offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
118 DEV_TX_OFFLOAD_UDP_TNL_TSO);
120 if (config->tunnel_en) {
122 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
124 if (config->tunnel_en &
125 MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)
126 offloads |= DEV_TX_OFFLOAD_VXLAN_TNL_TSO;
127 if (config->tunnel_en &
128 MLX5_TUNNELED_OFFLOADS_GRE_CAP)
129 offloads |= DEV_TX_OFFLOAD_GRE_TNL_TSO;
130 if (config->tunnel_en &
131 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)
132 offloads |= DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
135 if (!config->mprq.enabled)
136 offloads |= DEV_TX_OFFLOAD_MBUF_FAST_FREE;
140 /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */
142 txq_sync_cq(struct mlx5_txq_data *txq)
144 volatile struct mlx5_cqe *cqe;
149 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
150 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
151 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
152 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
153 /* No new CQEs in completion queue. */
154 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
160 /* Move all CQEs to HW ownership. */
161 for (i = 0; i < txq->cqe_s; i++) {
163 cqe->op_own = MLX5_CQE_INVALIDATE;
165 /* Resync CQE and WQE (WQ in reset state). */
167 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
168 txq->cq_pi = txq->cq_ci;
173 * Tx queue stop. Device queue goes to the idle state,
174 * all involved mbufs are freed from elts/WQ.
177 * Pointer to Ethernet device structure.
182 * 0 on success, a negative errno value otherwise and rte_errno is set.
185 mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t idx)
187 struct mlx5_priv *priv = dev->data->dev_private;
188 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
189 struct mlx5_txq_ctrl *txq_ctrl =
190 container_of(txq, struct mlx5_txq_ctrl, txq);
193 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
194 /* Move QP to RESET state. */
195 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj, MLX5_TXQ_MOD_RDY2RST,
196 (uint8_t)priv->dev_port);
199 /* Handle all send completions. */
201 /* Free elts stored in the SQ. */
202 txq_free_elts(txq_ctrl);
203 /* Prevent writing new pkts to SQ by setting no free WQE.*/
204 txq->wqe_ci = txq->wqe_s;
207 /* Set the actual queue state. */
208 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
213 * Tx queue stop. Device queue goes to the idle state,
214 * all involved mbufs are freed from elts/WQ.
217 * Pointer to Ethernet device structure.
222 * 0 on success, a negative errno value otherwise and rte_errno is set.
225 mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t idx)
229 if (rte_eth_dev_is_tx_hairpin_queue(dev, idx)) {
230 DRV_LOG(ERR, "Hairpin queue can't be stopped");
234 if (dev->data->tx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STOPPED)
236 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
237 ret = mlx5_mp_os_req_queue_control(dev, idx,
238 MLX5_MP_REQ_QUEUE_TX_STOP);
240 ret = mlx5_tx_queue_stop_primary(dev, idx);
246 * Rx queue start. Device queue goes to the ready state,
247 * all required mbufs are allocated and WQ is replenished.
250 * Pointer to Ethernet device structure.
255 * 0 on success, a negative errno value otherwise and rte_errno is set.
258 mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t idx)
260 struct mlx5_priv *priv = dev->data->dev_private;
261 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
262 struct mlx5_txq_ctrl *txq_ctrl =
263 container_of(txq, struct mlx5_txq_ctrl, txq);
266 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
267 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj,
268 MLX5_TXQ_MOD_RST2RDY,
269 (uint8_t)priv->dev_port);
272 txq_ctrl->txq.wqe_ci = 0;
273 txq_ctrl->txq.wqe_pi = 0;
274 txq_ctrl->txq.elts_comp = 0;
275 /* Set the actual queue state. */
276 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
281 * Rx queue start. Device queue goes to the ready state,
282 * all required mbufs are allocated and WQ is replenished.
285 * Pointer to Ethernet device structure.
290 * 0 on success, a negative errno value otherwise and rte_errno is set.
293 mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t idx)
297 if (rte_eth_dev_is_tx_hairpin_queue(dev, idx)) {
298 DRV_LOG(ERR, "Hairpin queue can't be started");
302 if (dev->data->tx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STARTED)
304 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
305 ret = mlx5_mp_os_req_queue_control(dev, idx,
306 MLX5_MP_REQ_QUEUE_TX_START);
308 ret = mlx5_tx_queue_start_primary(dev, idx);
314 * Tx queue presetup checks.
317 * Pointer to Ethernet device structure.
321 * Number of descriptors to configure in queue.
324 * 0 on success, a negative errno value otherwise and rte_errno is set.
327 mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
329 struct mlx5_priv *priv = dev->data->dev_private;
331 if (*desc <= MLX5_TX_COMP_THRESH) {
333 "port %u number of descriptors requested for Tx queue"
334 " %u must be higher than MLX5_TX_COMP_THRESH, using %u"
335 " instead of %u", dev->data->port_id, idx,
336 MLX5_TX_COMP_THRESH + 1, *desc);
337 *desc = MLX5_TX_COMP_THRESH + 1;
339 if (!rte_is_power_of_2(*desc)) {
340 *desc = 1 << log2above(*desc);
342 "port %u increased number of descriptors in Tx queue"
343 " %u to the next power of two (%d)",
344 dev->data->port_id, idx, *desc);
346 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors",
347 dev->data->port_id, idx, *desc);
348 if (idx >= priv->txqs_n) {
349 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)",
350 dev->data->port_id, idx, priv->txqs_n);
351 rte_errno = EOVERFLOW;
354 if (!mlx5_txq_releasable(dev, idx)) {
356 DRV_LOG(ERR, "port %u unable to release queue index %u",
357 dev->data->port_id, idx);
360 mlx5_txq_release(dev, idx);
365 * DPDK callback to configure a TX queue.
368 * Pointer to Ethernet device structure.
372 * Number of descriptors to configure in queue.
374 * NUMA socket on which memory must be allocated.
376 * Thresholds parameters.
379 * 0 on success, a negative errno value otherwise and rte_errno is set.
382 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
383 unsigned int socket, const struct rte_eth_txconf *conf)
385 struct mlx5_priv *priv = dev->data->dev_private;
386 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
387 struct mlx5_txq_ctrl *txq_ctrl =
388 container_of(txq, struct mlx5_txq_ctrl, txq);
391 res = mlx5_tx_queue_pre_setup(dev, idx, &desc);
394 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
396 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
397 dev->data->port_id, idx);
400 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
401 dev->data->port_id, idx);
402 (*priv->txqs)[idx] = &txq_ctrl->txq;
407 * DPDK callback to configure a TX hairpin queue.
410 * Pointer to Ethernet device structure.
414 * Number of descriptors to configure in queue.
415 * @param[in] hairpin_conf
416 * The hairpin binding configuration.
419 * 0 on success, a negative errno value otherwise and rte_errno is set.
422 mlx5_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
424 const struct rte_eth_hairpin_conf *hairpin_conf)
426 struct mlx5_priv *priv = dev->data->dev_private;
427 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
428 struct mlx5_txq_ctrl *txq_ctrl =
429 container_of(txq, struct mlx5_txq_ctrl, txq);
432 res = mlx5_tx_queue_pre_setup(dev, idx, &desc);
435 if (hairpin_conf->peer_count != 1) {
437 DRV_LOG(ERR, "port %u unable to setup Tx hairpin queue index %u"
438 " peer count is %u", dev->data->port_id,
439 idx, hairpin_conf->peer_count);
442 if (hairpin_conf->peers[0].port == dev->data->port_id) {
443 if (hairpin_conf->peers[0].queue >= priv->rxqs_n) {
445 DRV_LOG(ERR, "port %u unable to setup Tx hairpin queue"
446 " index %u, Rx %u is larger than %u",
447 dev->data->port_id, idx,
448 hairpin_conf->peers[0].queue, priv->txqs_n);
452 if (hairpin_conf->manual_bind == 0 ||
453 hairpin_conf->tx_explicit == 0) {
455 DRV_LOG(ERR, "port %u unable to setup Tx hairpin queue"
456 " index %u peer port %u with attributes %u %u",
457 dev->data->port_id, idx,
458 hairpin_conf->peers[0].port,
459 hairpin_conf->manual_bind,
460 hairpin_conf->tx_explicit);
464 txq_ctrl = mlx5_txq_hairpin_new(dev, idx, desc, hairpin_conf);
466 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
467 dev->data->port_id, idx);
470 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
471 dev->data->port_id, idx);
472 (*priv->txqs)[idx] = &txq_ctrl->txq;
473 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;
478 * DPDK callback to release a TX queue.
481 * Pointer to Ethernet device structure.
483 * Transmit queue index.
486 mlx5_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
488 struct mlx5_txq_data *txq = dev->data->tx_queues[qid];
492 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
493 dev->data->port_id, qid);
494 mlx5_txq_release(dev, qid);
498 * Configure the doorbell register non-cached attribute.
501 * Pointer to Tx queue control structure.
506 txq_uar_ncattr_init(struct mlx5_txq_ctrl *txq_ctrl, size_t page_size)
508 struct mlx5_priv *priv = txq_ctrl->priv;
511 txq_ctrl->txq.db_heu = priv->config.dbnc == MLX5_TXDB_HEURISTIC;
512 txq_ctrl->txq.db_nc = 0;
513 /* Check the doorbell register mapping type. */
514 cmd = txq_ctrl->uar_mmap_offset / page_size;
515 cmd >>= MLX5_UAR_MMAP_CMD_SHIFT;
516 cmd &= MLX5_UAR_MMAP_CMD_MASK;
517 if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD)
518 txq_ctrl->txq.db_nc = 1;
522 * Initialize Tx UAR registers for primary process.
525 * Pointer to Tx queue control structure.
528 txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
530 struct mlx5_priv *priv = txq_ctrl->priv;
531 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
533 unsigned int lock_idx;
535 const size_t page_size = rte_mem_page_size();
536 if (page_size == (size_t)-1) {
537 DRV_LOG(ERR, "Failed to get mem page size");
541 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
543 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
545 ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
546 txq_uar_ncattr_init(txq_ctrl, page_size);
548 /* Assign an UAR lock according to UAR page number */
549 lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
550 MLX5_UAR_PAGE_NUM_MASK;
551 txq_ctrl->txq.uar_lock = &priv->sh->uar_lock[lock_idx];
556 * Remap UAR register of a Tx queue for secondary process.
558 * Remapped address is stored at the table in the process private structure of
559 * the device, indexed by queue index.
562 * Pointer to Tx queue control structure.
564 * Verbs file descriptor to map UAR pages.
567 * 0 on success, a negative errno value otherwise and rte_errno is set.
570 txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)
572 struct mlx5_priv *priv = txq_ctrl->priv;
573 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
574 struct mlx5_txq_data *txq = &txq_ctrl->txq;
578 const size_t page_size = rte_mem_page_size();
579 if (page_size == (size_t)-1) {
580 DRV_LOG(ERR, "Failed to get mem page size");
585 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
589 * As rdma-core, UARs are mapped in size of OS page
590 * size. Ref to libmlx5 function: mlx5_init_context()
592 uar_va = (uintptr_t)txq_ctrl->bf_reg;
593 offset = uar_va & (page_size - 1); /* Offset in page. */
594 addr = rte_mem_map(NULL, page_size, RTE_PROT_WRITE, RTE_MAP_SHARED,
595 fd, txq_ctrl->uar_mmap_offset);
598 "port %u mmap failed for BF reg of txq %u",
599 txq->port_id, txq->idx);
603 addr = RTE_PTR_ADD(addr, offset);
604 ppriv->uar_table[txq->idx] = addr;
605 txq_uar_ncattr_init(txq_ctrl, page_size);
610 * Unmap UAR register of a Tx queue for secondary process.
613 * Pointer to Tx queue control structure.
616 txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl)
618 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(txq_ctrl->priv));
620 const size_t page_size = rte_mem_page_size();
621 if (page_size == (size_t)-1) {
622 DRV_LOG(ERR, "Failed to get mem page size");
626 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
628 addr = ppriv->uar_table[txq_ctrl->txq.idx];
629 rte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
633 * Deinitialize Tx UAR registers for secondary process.
636 * Pointer to Ethernet device.
639 mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev)
641 struct mlx5_proc_priv *ppriv = (struct mlx5_proc_priv *)
642 dev->process_private;
643 const size_t page_size = rte_mem_page_size();
647 if (page_size == (size_t)-1) {
648 DRV_LOG(ERR, "Failed to get mem page size");
651 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);
652 for (i = 0; i != ppriv->uar_table_sz; ++i) {
653 if (!ppriv->uar_table[i])
655 addr = ppriv->uar_table[i];
656 rte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
662 * Initialize Tx UAR registers for secondary process.
665 * Pointer to Ethernet device.
667 * Verbs file descriptor to map UAR pages.
670 * 0 on success, a negative errno value otherwise and rte_errno is set.
673 mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd)
675 struct mlx5_priv *priv = dev->data->dev_private;
676 struct mlx5_txq_data *txq;
677 struct mlx5_txq_ctrl *txq_ctrl;
681 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);
682 for (i = 0; i != priv->txqs_n; ++i) {
683 if (!(*priv->txqs)[i])
685 txq = (*priv->txqs)[i];
686 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
687 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
689 MLX5_ASSERT(txq->idx == (uint16_t)i);
690 ret = txq_uar_init_secondary(txq_ctrl, fd);
698 if (!(*priv->txqs)[i])
700 txq = (*priv->txqs)[i];
701 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
702 txq_uar_uninit_secondary(txq_ctrl);
708 * Verify the Verbs Tx queue list is empty
711 * Pointer to Ethernet device.
714 * The number of object not released.
717 mlx5_txq_obj_verify(struct rte_eth_dev *dev)
719 struct mlx5_priv *priv = dev->data->dev_private;
721 struct mlx5_txq_obj *txq_obj;
723 LIST_FOREACH(txq_obj, &priv->txqsobj, next) {
724 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced",
725 dev->data->port_id, txq_obj->txq_ctrl->txq.idx);
732 * Calculate the total number of WQEBB for Tx queue.
734 * Simplified version of calc_sq_size() in rdma-core.
737 * Pointer to Tx queue control structure.
740 * The number of WQEBB.
743 txq_calc_wqebb_cnt(struct mlx5_txq_ctrl *txq_ctrl)
745 unsigned int wqe_size;
746 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
748 wqe_size = MLX5_WQE_CSEG_SIZE +
751 MLX5_ESEG_MIN_INLINE_SIZE +
752 txq_ctrl->max_inline_data;
753 return rte_align32pow2(wqe_size * desc) / MLX5_WQE_SIZE;
757 * Calculate the maximal inline data size for Tx queue.
760 * Pointer to Tx queue control structure.
763 * The maximal inline data size.
766 txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl)
768 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
769 struct mlx5_priv *priv = txq_ctrl->priv;
770 unsigned int wqe_size;
772 wqe_size = priv->sh->device_attr.max_qp_wr / desc;
776 * This calculation is derived from tthe source of
777 * mlx5_calc_send_wqe() in rdma_core library.
779 wqe_size = wqe_size * MLX5_WQE_SIZE -
784 MLX5_DSEG_MIN_INLINE_SIZE;
789 * Set Tx queue parameters from device configuration.
792 * Pointer to Tx queue control structure.
795 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
797 struct mlx5_priv *priv = txq_ctrl->priv;
798 struct mlx5_dev_config *config = &priv->config;
799 unsigned int inlen_send; /* Inline data for ordinary SEND.*/
800 unsigned int inlen_empw; /* Inline data for enhanced MPW. */
801 unsigned int inlen_mode; /* Minimal required Inline data. */
802 unsigned int txqs_inline; /* Min Tx queues to enable inline. */
803 uint64_t dev_txoff = priv->dev_data->dev_conf.txmode.offloads;
804 bool tso = txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO |
805 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
806 DEV_TX_OFFLOAD_GRE_TNL_TSO |
807 DEV_TX_OFFLOAD_IP_TNL_TSO |
808 DEV_TX_OFFLOAD_UDP_TNL_TSO);
812 txq_ctrl->txq.fast_free =
813 !!((txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
814 !(txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_MULTI_SEGS) &&
815 !config->mprq.enabled);
816 if (config->txqs_inline == MLX5_ARG_UNSET)
818 #if defined(RTE_ARCH_ARM64)
819 (priv->pci_dev && priv->pci_dev->id.device_id ==
820 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) ?
821 MLX5_INLINE_MAX_TXQS_BLUEFIELD :
823 MLX5_INLINE_MAX_TXQS;
825 txqs_inline = (unsigned int)config->txqs_inline;
826 inlen_send = (config->txq_inline_max == MLX5_ARG_UNSET) ?
827 MLX5_SEND_DEF_INLINE_LEN :
828 (unsigned int)config->txq_inline_max;
829 inlen_empw = (config->txq_inline_mpw == MLX5_ARG_UNSET) ?
830 MLX5_EMPW_DEF_INLINE_LEN :
831 (unsigned int)config->txq_inline_mpw;
832 inlen_mode = (config->txq_inline_min == MLX5_ARG_UNSET) ?
833 0 : (unsigned int)config->txq_inline_min;
834 if (config->mps != MLX5_MPW_ENHANCED && config->mps != MLX5_MPW)
837 * If there is requested minimal amount of data to inline
838 * we MUST enable inlining. This is a case for ConnectX-4
839 * which usually requires L2 inlined for correct operating
840 * and ConnectX-4 Lx which requires L2-L4 inlined to
841 * support E-Switch Flows.
844 if (inlen_mode <= MLX5_ESEG_MIN_INLINE_SIZE) {
846 * Optimize minimal inlining for single
847 * segment packets to fill one WQEBB
850 temp = MLX5_ESEG_MIN_INLINE_SIZE;
852 temp = inlen_mode - MLX5_ESEG_MIN_INLINE_SIZE;
853 temp = RTE_ALIGN(temp, MLX5_WSEG_SIZE) +
854 MLX5_ESEG_MIN_INLINE_SIZE;
855 temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN);
857 if (temp != inlen_mode) {
859 "port %u minimal required inline setting"
860 " aligned from %u to %u",
861 PORT_ID(priv), inlen_mode, temp);
866 * If port is configured to support VLAN insertion and device
867 * does not support this feature by HW (for NICs before ConnectX-5
868 * or in case of wqe_vlan_insert flag is not set) we must enable
869 * data inline on all queues because it is supported by single
872 txq_ctrl->txq.vlan_en = config->hw_vlan_insert;
873 vlan_inline = (dev_txoff & DEV_TX_OFFLOAD_VLAN_INSERT) &&
874 !config->hw_vlan_insert;
876 * If there are few Tx queues it is prioritized
877 * to save CPU cycles and disable data inlining at all.
879 if (inlen_send && priv->txqs_n >= txqs_inline) {
881 * The data sent with ordinal MLX5_OPCODE_SEND
882 * may be inlined in Ethernet Segment, align the
883 * length accordingly to fit entire WQEBBs.
885 temp = RTE_MAX(inlen_send,
886 MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE);
887 temp -= MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE;
888 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE);
889 temp += MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE;
890 temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX +
891 MLX5_ESEG_MIN_INLINE_SIZE -
894 MLX5_WQE_DSEG_SIZE * 2);
895 temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN);
896 temp = RTE_MAX(temp, inlen_mode);
897 if (temp != inlen_send) {
899 "port %u ordinary send inline setting"
900 " aligned from %u to %u",
901 PORT_ID(priv), inlen_send, temp);
905 * Not aligned to cache lines, but to WQEs.
906 * First bytes of data (initial alignment)
907 * is going to be copied explicitly at the
908 * beginning of inlining buffer in Ethernet
911 MLX5_ASSERT(inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
912 MLX5_ASSERT(inlen_send <= MLX5_WQE_SIZE_MAX +
913 MLX5_ESEG_MIN_INLINE_SIZE -
916 MLX5_WQE_DSEG_SIZE * 2);
917 } else if (inlen_mode) {
919 * If minimal inlining is requested we must
920 * enable inlining in general, despite the
921 * number of configured queues. Ignore the
922 * txq_inline_max devarg, this is not
923 * full-featured inline.
925 inlen_send = inlen_mode;
927 } else if (vlan_inline) {
929 * Hardware does not report offload for
930 * VLAN insertion, we must enable data inline
931 * to implement feature by software.
933 inlen_send = MLX5_ESEG_MIN_INLINE_SIZE;
939 txq_ctrl->txq.inlen_send = inlen_send;
940 txq_ctrl->txq.inlen_mode = inlen_mode;
941 txq_ctrl->txq.inlen_empw = 0;
942 if (inlen_send && inlen_empw && priv->txqs_n >= txqs_inline) {
944 * The data sent with MLX5_OPCODE_ENHANCED_MPSW
945 * may be inlined in Data Segment, align the
946 * length accordingly to fit entire WQEBBs.
948 temp = RTE_MAX(inlen_empw,
949 MLX5_WQE_SIZE + MLX5_DSEG_MIN_INLINE_SIZE);
950 temp -= MLX5_DSEG_MIN_INLINE_SIZE;
951 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE);
952 temp += MLX5_DSEG_MIN_INLINE_SIZE;
953 temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX +
954 MLX5_DSEG_MIN_INLINE_SIZE -
958 temp = RTE_MIN(temp, MLX5_EMPW_MAX_INLINE_LEN);
959 if (temp != inlen_empw) {
961 "port %u enhanced empw inline setting"
962 " aligned from %u to %u",
963 PORT_ID(priv), inlen_empw, temp);
966 MLX5_ASSERT(inlen_empw >= MLX5_ESEG_MIN_INLINE_SIZE);
967 MLX5_ASSERT(inlen_empw <= MLX5_WQE_SIZE_MAX +
968 MLX5_DSEG_MIN_INLINE_SIZE -
972 txq_ctrl->txq.inlen_empw = inlen_empw;
974 txq_ctrl->max_inline_data = RTE_MAX(inlen_send, inlen_empw);
976 txq_ctrl->max_tso_header = MLX5_MAX_TSO_HEADER;
977 txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->max_inline_data,
978 MLX5_MAX_TSO_HEADER);
979 txq_ctrl->txq.tso_en = 1;
981 if (((DEV_TX_OFFLOAD_VXLAN_TNL_TSO & txq_ctrl->txq.offloads) &&
982 (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)) |
983 ((DEV_TX_OFFLOAD_GRE_TNL_TSO & txq_ctrl->txq.offloads) &&
984 (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GRE_CAP)) |
985 ((DEV_TX_OFFLOAD_GENEVE_TNL_TSO & txq_ctrl->txq.offloads) &&
986 (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)) |
987 (config->swp & MLX5_SW_PARSING_TSO_CAP))
988 txq_ctrl->txq.tunnel_en = 1;
989 txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO |
990 DEV_TX_OFFLOAD_UDP_TNL_TSO) &
991 txq_ctrl->txq.offloads) && (config->swp &
992 MLX5_SW_PARSING_TSO_CAP)) |
993 ((DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM &
994 txq_ctrl->txq.offloads) && (config->swp &
995 MLX5_SW_PARSING_CSUM_CAP));
999 * Adjust Tx queue data inline parameters for large queue sizes.
1000 * The data inline feature requires multiple WQEs to fit the packets,
1001 * and if the large amount of Tx descriptors is requested by application
1002 * the total WQE amount may exceed the hardware capabilities. If the
1003 * default inline setting are used we can try to adjust these ones and
1004 * meet the hardware requirements and not exceed the queue size.
1007 * Pointer to Tx queue control structure.
1010 * Zero on success, otherwise the parameters can not be adjusted.
1013 txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)
1015 struct mlx5_priv *priv = txq_ctrl->priv;
1016 struct mlx5_dev_config *config = &priv->config;
1017 unsigned int max_inline;
1019 max_inline = txq_calc_inline_max(txq_ctrl);
1020 if (!txq_ctrl->txq.inlen_send) {
1022 * Inline data feature is not engaged at all.
1023 * There is nothing to adjust.
1027 if (txq_ctrl->max_inline_data <= max_inline) {
1029 * The requested inline data length does not
1030 * exceed queue capabilities.
1034 if (txq_ctrl->txq.inlen_mode > max_inline) {
1036 "minimal data inline requirements (%u) are not"
1037 " satisfied (%u) on port %u, try the smaller"
1038 " Tx queue size (%d)",
1039 txq_ctrl->txq.inlen_mode, max_inline,
1040 priv->dev_data->port_id,
1041 priv->sh->device_attr.max_qp_wr);
1044 if (txq_ctrl->txq.inlen_send > max_inline &&
1045 config->txq_inline_max != MLX5_ARG_UNSET &&
1046 config->txq_inline_max > (int)max_inline) {
1048 "txq_inline_max requirements (%u) are not"
1049 " satisfied (%u) on port %u, try the smaller"
1050 " Tx queue size (%d)",
1051 txq_ctrl->txq.inlen_send, max_inline,
1052 priv->dev_data->port_id,
1053 priv->sh->device_attr.max_qp_wr);
1056 if (txq_ctrl->txq.inlen_empw > max_inline &&
1057 config->txq_inline_mpw != MLX5_ARG_UNSET &&
1058 config->txq_inline_mpw > (int)max_inline) {
1060 "txq_inline_mpw requirements (%u) are not"
1061 " satisfied (%u) on port %u, try the smaller"
1062 " Tx queue size (%d)",
1063 txq_ctrl->txq.inlen_empw, max_inline,
1064 priv->dev_data->port_id,
1065 priv->sh->device_attr.max_qp_wr);
1068 if (txq_ctrl->txq.tso_en && max_inline < MLX5_MAX_TSO_HEADER) {
1070 "tso header inline requirements (%u) are not"
1071 " satisfied (%u) on port %u, try the smaller"
1072 " Tx queue size (%d)",
1073 MLX5_MAX_TSO_HEADER, max_inline,
1074 priv->dev_data->port_id,
1075 priv->sh->device_attr.max_qp_wr);
1078 if (txq_ctrl->txq.inlen_send > max_inline) {
1080 "adjust txq_inline_max (%u->%u)"
1081 " due to large Tx queue on port %u",
1082 txq_ctrl->txq.inlen_send, max_inline,
1083 priv->dev_data->port_id);
1084 txq_ctrl->txq.inlen_send = max_inline;
1086 if (txq_ctrl->txq.inlen_empw > max_inline) {
1088 "adjust txq_inline_mpw (%u->%u)"
1089 "due to large Tx queue on port %u",
1090 txq_ctrl->txq.inlen_empw, max_inline,
1091 priv->dev_data->port_id);
1092 txq_ctrl->txq.inlen_empw = max_inline;
1094 txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->txq.inlen_send,
1095 txq_ctrl->txq.inlen_empw);
1096 MLX5_ASSERT(txq_ctrl->max_inline_data <= max_inline);
1097 MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= max_inline);
1098 MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send);
1099 MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw ||
1100 !txq_ctrl->txq.inlen_empw);
1108 * Create a DPDK Tx queue.
1111 * Pointer to Ethernet device.
1115 * Number of descriptors to configure in queue.
1117 * NUMA socket on which memory must be allocated.
1119 * Thresholds parameters.
1122 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1124 struct mlx5_txq_ctrl *
1125 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1126 unsigned int socket, const struct rte_eth_txconf *conf)
1128 struct mlx5_priv *priv = dev->data->dev_private;
1129 struct mlx5_txq_ctrl *tmpl;
1131 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) +
1132 desc * sizeof(struct rte_mbuf *), 0, socket);
1137 if (mlx5_mr_btree_init(&tmpl->txq.mr_ctrl.cache_bh,
1138 MLX5_MR_BTREE_CACHE_N, socket)) {
1139 /* rte_errno is already set. */
1142 /* Save pointer of global generation number to check memory event. */
1143 tmpl->txq.mr_ctrl.dev_gen_ptr = &priv->sh->share_cache.dev_gen;
1144 MLX5_ASSERT(desc > MLX5_TX_COMP_THRESH);
1145 tmpl->txq.offloads = conf->offloads |
1146 dev->data->dev_conf.txmode.offloads;
1148 tmpl->socket = socket;
1149 tmpl->txq.elts_n = log2above(desc);
1150 tmpl->txq.elts_s = desc;
1151 tmpl->txq.elts_m = desc - 1;
1152 tmpl->txq.port_id = dev->data->port_id;
1153 tmpl->txq.idx = idx;
1154 txq_set_params(tmpl);
1155 if (txq_adjust_params(tmpl))
1157 if (txq_calc_wqebb_cnt(tmpl) >
1158 priv->sh->device_attr.max_qp_wr) {
1160 "port %u Tx WQEBB count (%d) exceeds the limit (%d),"
1161 " try smaller queue size",
1162 dev->data->port_id, txq_calc_wqebb_cnt(tmpl),
1163 priv->sh->device_attr.max_qp_wr);
1167 __atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);
1168 tmpl->type = MLX5_TXQ_TYPE_STANDARD;
1169 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
1172 mlx5_mr_btree_free(&tmpl->txq.mr_ctrl.cache_bh);
1178 * Create a DPDK Tx hairpin queue.
1181 * Pointer to Ethernet device.
1185 * Number of descriptors to configure in queue.
1186 * @param hairpin_conf
1187 * The hairpin configuration.
1190 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1192 struct mlx5_txq_ctrl *
1193 mlx5_txq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1194 const struct rte_eth_hairpin_conf *hairpin_conf)
1196 struct mlx5_priv *priv = dev->data->dev_private;
1197 struct mlx5_txq_ctrl *tmpl;
1199 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1206 tmpl->socket = SOCKET_ID_ANY;
1207 tmpl->txq.elts_n = log2above(desc);
1208 tmpl->txq.port_id = dev->data->port_id;
1209 tmpl->txq.idx = idx;
1210 tmpl->hairpin_conf = *hairpin_conf;
1211 tmpl->type = MLX5_TXQ_TYPE_HAIRPIN;
1212 __atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);
1213 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
1221 * Pointer to Ethernet device.
1226 * A pointer to the queue if it exists.
1228 struct mlx5_txq_ctrl *
1229 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
1231 struct mlx5_priv *priv = dev->data->dev_private;
1232 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1233 struct mlx5_txq_ctrl *ctrl = NULL;
1236 ctrl = container_of(txq_data, struct mlx5_txq_ctrl, txq);
1237 __atomic_fetch_add(&ctrl->refcnt, 1, __ATOMIC_RELAXED);
1243 * Release a Tx queue.
1246 * Pointer to Ethernet device.
1251 * 1 while a reference on it exists, 0 when freed.
1254 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
1256 struct mlx5_priv *priv = dev->data->dev_private;
1257 struct mlx5_txq_ctrl *txq_ctrl;
1259 if (priv->txqs == NULL || (*priv->txqs)[idx] == NULL)
1261 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
1262 if (__atomic_sub_fetch(&txq_ctrl->refcnt, 1, __ATOMIC_RELAXED) > 1)
1264 if (txq_ctrl->obj) {
1265 priv->obj_ops.txq_obj_release(txq_ctrl->obj);
1266 LIST_REMOVE(txq_ctrl->obj, next);
1267 mlx5_free(txq_ctrl->obj);
1268 txq_ctrl->obj = NULL;
1270 if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD) {
1271 if (txq_ctrl->txq.fcqs) {
1272 mlx5_free(txq_ctrl->txq.fcqs);
1273 txq_ctrl->txq.fcqs = NULL;
1275 txq_free_elts(txq_ctrl);
1276 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
1278 if (!__atomic_load_n(&txq_ctrl->refcnt, __ATOMIC_RELAXED)) {
1279 if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD)
1280 mlx5_mr_btree_free(&txq_ctrl->txq.mr_ctrl.cache_bh);
1281 LIST_REMOVE(txq_ctrl, next);
1282 mlx5_free(txq_ctrl);
1283 (*priv->txqs)[idx] = NULL;
1289 * Verify if the queue can be released.
1292 * Pointer to Ethernet device.
1297 * 1 if the queue can be released.
1300 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
1302 struct mlx5_priv *priv = dev->data->dev_private;
1303 struct mlx5_txq_ctrl *txq;
1305 if (!(*priv->txqs)[idx])
1307 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
1308 return (__atomic_load_n(&txq->refcnt, __ATOMIC_RELAXED) == 1);
1312 * Verify the Tx Queue list is empty
1315 * Pointer to Ethernet device.
1318 * The number of object not released.
1321 mlx5_txq_verify(struct rte_eth_dev *dev)
1323 struct mlx5_priv *priv = dev->data->dev_private;
1324 struct mlx5_txq_ctrl *txq_ctrl;
1327 LIST_FOREACH(txq_ctrl, &priv->txqsctrl, next) {
1328 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced",
1329 dev->data->port_id, txq_ctrl->txq.idx);
1336 * Set the Tx queue dynamic timestamp (mask and offset)
1339 * Pointer to the Ethernet device structure.
1342 mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev)
1344 struct mlx5_priv *priv = dev->data->dev_private;
1345 struct mlx5_dev_ctx_shared *sh = priv->sh;
1346 struct mlx5_txq_data *data;
1351 nbit = rte_mbuf_dynflag_lookup
1352 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
1353 off = rte_mbuf_dynfield_lookup
1354 (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL);
1355 if (nbit >= 0 && off >= 0 && sh->txpp.refcnt)
1356 mask = 1ULL << nbit;
1357 for (i = 0; i != priv->txqs_n; ++i) {
1358 data = (*priv->txqs)[i];
1362 data->ts_mask = mask;
1363 data->ts_offset = off;