1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <rte_malloc.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_common.h>
17 #include <rte_eal_paging.h>
19 #include <mlx5_glue.h>
20 #include <mlx5_devx_cmds.h>
21 #include <mlx5_common.h>
22 #include <mlx5_common_mr.h>
23 #include <mlx5_common_os.h>
24 #include <mlx5_malloc.h>
26 #include "mlx5_defs.h"
27 #include "mlx5_utils.h"
29 #include "mlx5_rxtx.h"
30 #include "mlx5_autoconf.h"
33 * Allocate TX queue elements.
36 * Pointer to TX queue structure.
39 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
41 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
44 for (i = 0; (i != elts_n); ++i)
45 txq_ctrl->txq.elts[i] = NULL;
46 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
47 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx, elts_n);
48 txq_ctrl->txq.elts_head = 0;
49 txq_ctrl->txq.elts_tail = 0;
50 txq_ctrl->txq.elts_comp = 0;
54 * Free TX queue elements.
57 * Pointer to TX queue structure.
60 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
62 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
63 const uint16_t elts_m = elts_n - 1;
64 uint16_t elts_head = txq_ctrl->txq.elts_head;
65 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
66 struct rte_mbuf *(*elts)[elts_n] = &txq_ctrl->txq.elts;
68 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs",
69 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx);
70 txq_ctrl->txq.elts_head = 0;
71 txq_ctrl->txq.elts_tail = 0;
72 txq_ctrl->txq.elts_comp = 0;
74 while (elts_tail != elts_head) {
75 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
77 MLX5_ASSERT(elt != NULL);
78 rte_pktmbuf_free_seg(elt);
79 #ifdef RTE_LIBRTE_MLX5_DEBUG
81 memset(&(*elts)[elts_tail & elts_m],
83 sizeof((*elts)[elts_tail & elts_m]));
90 * Returns the per-port supported offloads.
93 * Pointer to Ethernet device.
96 * Supported Tx offloads.
99 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
101 struct mlx5_priv *priv = dev->data->dev_private;
102 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
103 DEV_TX_OFFLOAD_VLAN_INSERT);
104 struct mlx5_dev_config *config = &priv->config;
107 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
108 DEV_TX_OFFLOAD_UDP_CKSUM |
109 DEV_TX_OFFLOAD_TCP_CKSUM);
111 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
113 offloads |= DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP;
116 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
118 offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
119 DEV_TX_OFFLOAD_UDP_TNL_TSO);
121 if (config->tunnel_en) {
123 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
125 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
126 DEV_TX_OFFLOAD_GRE_TNL_TSO |
127 DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
132 /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */
134 txq_sync_cq(struct mlx5_txq_data *txq)
136 volatile struct mlx5_cqe *cqe;
141 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
142 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
143 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
144 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
145 /* No new CQEs in completion queue. */
146 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
152 /* Move all CQEs to HW ownership. */
153 for (i = 0; i < txq->cqe_s; i++) {
155 cqe->op_own = MLX5_CQE_INVALIDATE;
157 /* Resync CQE and WQE (WQ in reset state). */
159 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
164 * Tx queue stop. Device queue goes to the idle state,
165 * all involved mbufs are freed from elts/WQ.
168 * Pointer to Ethernet device structure.
173 * 0 on success, a negative errno value otherwise and rte_errno is set.
176 mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t idx)
178 struct mlx5_priv *priv = dev->data->dev_private;
179 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
180 struct mlx5_txq_ctrl *txq_ctrl =
181 container_of(txq, struct mlx5_txq_ctrl, txq);
184 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
185 /* Move QP to RESET state. */
186 if (txq_ctrl->obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_SQ) {
187 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
189 /* Change queue state to reset with DevX. */
190 msq_attr.sq_state = MLX5_SQC_STATE_RDY;
191 msq_attr.state = MLX5_SQC_STATE_RST;
192 ret = mlx5_devx_cmd_modify_sq(txq_ctrl->obj->sq_devx,
195 DRV_LOG(ERR, "Cannot change the "
196 "Tx QP state to RESET %s",
202 struct ibv_qp_attr mod = {
203 .qp_state = IBV_QPS_RESET,
204 .port_num = (uint8_t)priv->dev_port,
206 struct ibv_qp *qp = txq_ctrl->obj->qp;
208 /* Change queue state to reset with Verbs. */
209 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
211 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET "
212 "%s", strerror(errno));
217 /* Handle all send completions. */
219 /* Free elts stored in the SQ. */
220 txq_free_elts(txq_ctrl);
221 /* Prevent writing new pkts to SQ by setting no free WQE.*/
222 txq->wqe_ci = txq->wqe_s;
225 /* Set the actual queue state. */
226 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
231 * Tx queue stop. Device queue goes to the idle state,
232 * all involved mbufs are freed from elts/WQ.
235 * Pointer to Ethernet device structure.
240 * 0 on success, a negative errno value otherwise and rte_errno is set.
243 mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t idx)
247 if (dev->data->tx_queue_state[idx] == RTE_ETH_QUEUE_STATE_HAIRPIN) {
248 DRV_LOG(ERR, "Hairpin queue can't be stopped");
252 if (dev->data->tx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STOPPED)
254 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
255 ret = mlx5_mp_os_req_queue_control(dev, idx,
256 MLX5_MP_REQ_QUEUE_TX_STOP);
258 ret = mlx5_tx_queue_stop_primary(dev, idx);
264 * Rx queue start. Device queue goes to the ready state,
265 * all required mbufs are allocated and WQ is replenished.
268 * Pointer to Ethernet device structure.
273 * 0 on success, a negative errno value otherwise and rte_errno is set.
276 mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t idx)
278 struct mlx5_priv *priv = dev->data->dev_private;
279 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
280 struct mlx5_txq_ctrl *txq_ctrl =
281 container_of(txq, struct mlx5_txq_ctrl, txq);
284 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
285 if (txq_ctrl->obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_SQ) {
286 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
287 struct mlx5_txq_obj *obj = txq_ctrl->obj;
289 msq_attr.sq_state = MLX5_SQC_STATE_RDY;
290 msq_attr.state = MLX5_SQC_STATE_RST;
291 ret = mlx5_devx_cmd_modify_sq(obj->sq_devx, &msq_attr);
295 "Cannot change the Tx QP state to RESET "
296 "%s", strerror(errno));
299 msq_attr.sq_state = MLX5_SQC_STATE_RST;
300 msq_attr.state = MLX5_SQC_STATE_RDY;
301 ret = mlx5_devx_cmd_modify_sq(obj->sq_devx, &msq_attr);
305 "Cannot change the Tx QP state to READY "
306 "%s", strerror(errno));
310 struct ibv_qp_attr mod = {
311 .qp_state = IBV_QPS_RESET,
312 .port_num = (uint8_t)priv->dev_port,
314 struct ibv_qp *qp = txq_ctrl->obj->qp;
316 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
318 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET "
319 "%s", strerror(errno));
323 mod.qp_state = IBV_QPS_INIT;
324 ret = mlx5_glue->modify_qp(qp, &mod,
325 (IBV_QP_STATE | IBV_QP_PORT));
327 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s",
332 mod.qp_state = IBV_QPS_RTR;
333 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
335 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s",
340 mod.qp_state = IBV_QPS_RTS;
341 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
343 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s",
349 txq_ctrl->txq.wqe_ci = 0;
350 txq_ctrl->txq.wqe_pi = 0;
351 txq_ctrl->txq.elts_comp = 0;
352 /* Set the actual queue state. */
353 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
358 * Rx queue start. Device queue goes to the ready state,
359 * all required mbufs are allocated and WQ is replenished.
362 * Pointer to Ethernet device structure.
367 * 0 on success, a negative errno value otherwise and rte_errno is set.
370 mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t idx)
374 if (dev->data->tx_queue_state[idx] == RTE_ETH_QUEUE_STATE_HAIRPIN) {
375 DRV_LOG(ERR, "Hairpin queue can't be started");
379 if (dev->data->tx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STARTED)
381 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
382 ret = mlx5_mp_os_req_queue_control(dev, idx,
383 MLX5_MP_REQ_QUEUE_TX_START);
385 ret = mlx5_tx_queue_start_primary(dev, idx);
391 * Tx queue presetup checks.
394 * Pointer to Ethernet device structure.
398 * Number of descriptors to configure in queue.
401 * 0 on success, a negative errno value otherwise and rte_errno is set.
404 mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
406 struct mlx5_priv *priv = dev->data->dev_private;
408 if (*desc <= MLX5_TX_COMP_THRESH) {
410 "port %u number of descriptors requested for Tx queue"
411 " %u must be higher than MLX5_TX_COMP_THRESH, using %u"
412 " instead of %u", dev->data->port_id, idx,
413 MLX5_TX_COMP_THRESH + 1, *desc);
414 *desc = MLX5_TX_COMP_THRESH + 1;
416 if (!rte_is_power_of_2(*desc)) {
417 *desc = 1 << log2above(*desc);
419 "port %u increased number of descriptors in Tx queue"
420 " %u to the next power of two (%d)",
421 dev->data->port_id, idx, *desc);
423 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors",
424 dev->data->port_id, idx, *desc);
425 if (idx >= priv->txqs_n) {
426 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)",
427 dev->data->port_id, idx, priv->txqs_n);
428 rte_errno = EOVERFLOW;
431 if (!mlx5_txq_releasable(dev, idx)) {
433 DRV_LOG(ERR, "port %u unable to release queue index %u",
434 dev->data->port_id, idx);
437 mlx5_txq_release(dev, idx);
441 * DPDK callback to configure a TX queue.
444 * Pointer to Ethernet device structure.
448 * Number of descriptors to configure in queue.
450 * NUMA socket on which memory must be allocated.
452 * Thresholds parameters.
455 * 0 on success, a negative errno value otherwise and rte_errno is set.
458 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
459 unsigned int socket, const struct rte_eth_txconf *conf)
461 struct mlx5_priv *priv = dev->data->dev_private;
462 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
463 struct mlx5_txq_ctrl *txq_ctrl =
464 container_of(txq, struct mlx5_txq_ctrl, txq);
467 res = mlx5_tx_queue_pre_setup(dev, idx, &desc);
470 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
472 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
473 dev->data->port_id, idx);
476 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
477 dev->data->port_id, idx);
478 (*priv->txqs)[idx] = &txq_ctrl->txq;
479 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
484 * DPDK callback to configure a TX hairpin queue.
487 * Pointer to Ethernet device structure.
491 * Number of descriptors to configure in queue.
492 * @param[in] hairpin_conf
493 * The hairpin binding configuration.
496 * 0 on success, a negative errno value otherwise and rte_errno is set.
499 mlx5_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
501 const struct rte_eth_hairpin_conf *hairpin_conf)
503 struct mlx5_priv *priv = dev->data->dev_private;
504 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
505 struct mlx5_txq_ctrl *txq_ctrl =
506 container_of(txq, struct mlx5_txq_ctrl, txq);
509 res = mlx5_tx_queue_pre_setup(dev, idx, &desc);
512 if (hairpin_conf->peer_count != 1 ||
513 hairpin_conf->peers[0].port != dev->data->port_id ||
514 hairpin_conf->peers[0].queue >= priv->rxqs_n) {
515 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
516 " invalid hairpind configuration", dev->data->port_id,
521 txq_ctrl = mlx5_txq_hairpin_new(dev, idx, desc, hairpin_conf);
523 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
524 dev->data->port_id, idx);
527 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
528 dev->data->port_id, idx);
529 (*priv->txqs)[idx] = &txq_ctrl->txq;
530 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;
535 * DPDK callback to release a TX queue.
538 * Generic TX queue pointer.
541 mlx5_tx_queue_release(void *dpdk_txq)
543 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
544 struct mlx5_txq_ctrl *txq_ctrl;
545 struct mlx5_priv *priv;
550 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
551 priv = txq_ctrl->priv;
552 for (i = 0; (i != priv->txqs_n); ++i)
553 if ((*priv->txqs)[i] == txq) {
554 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
555 PORT_ID(priv), txq->idx);
556 mlx5_txq_release(ETH_DEV(priv), i);
562 * Configure the doorbell register non-cached attribute.
565 * Pointer to Tx queue control structure.
570 txq_uar_ncattr_init(struct mlx5_txq_ctrl *txq_ctrl, size_t page_size)
572 struct mlx5_priv *priv = txq_ctrl->priv;
575 txq_ctrl->txq.db_heu = priv->config.dbnc == MLX5_TXDB_HEURISTIC;
576 txq_ctrl->txq.db_nc = 0;
577 /* Check the doorbell register mapping type. */
578 cmd = txq_ctrl->uar_mmap_offset / page_size;
579 cmd >>= MLX5_UAR_MMAP_CMD_SHIFT;
580 cmd &= MLX5_UAR_MMAP_CMD_MASK;
581 if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD)
582 txq_ctrl->txq.db_nc = 1;
586 * Initialize Tx UAR registers for primary process.
589 * Pointer to Tx queue control structure.
592 txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
594 struct mlx5_priv *priv = txq_ctrl->priv;
595 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
597 unsigned int lock_idx;
599 const size_t page_size = rte_mem_page_size();
600 if (page_size == (size_t)-1) {
601 DRV_LOG(ERR, "Failed to get mem page size");
605 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
607 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
609 ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
610 txq_uar_ncattr_init(txq_ctrl, page_size);
612 /* Assign an UAR lock according to UAR page number */
613 lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
614 MLX5_UAR_PAGE_NUM_MASK;
615 txq_ctrl->txq.uar_lock = &priv->sh->uar_lock[lock_idx];
620 * Remap UAR register of a Tx queue for secondary process.
622 * Remapped address is stored at the table in the process private structure of
623 * the device, indexed by queue index.
626 * Pointer to Tx queue control structure.
628 * Verbs file descriptor to map UAR pages.
631 * 0 on success, a negative errno value otherwise and rte_errno is set.
634 txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)
636 struct mlx5_priv *priv = txq_ctrl->priv;
637 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
638 struct mlx5_txq_data *txq = &txq_ctrl->txq;
642 const size_t page_size = rte_mem_page_size();
643 if (page_size == (size_t)-1) {
644 DRV_LOG(ERR, "Failed to get mem page size");
649 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
653 * As rdma-core, UARs are mapped in size of OS page
654 * size. Ref to libmlx5 function: mlx5_init_context()
656 uar_va = (uintptr_t)txq_ctrl->bf_reg;
657 offset = uar_va & (page_size - 1); /* Offset in page. */
658 addr = rte_mem_map(NULL, page_size, RTE_PROT_WRITE, RTE_MAP_SHARED,
659 fd, txq_ctrl->uar_mmap_offset);
662 "port %u mmap failed for BF reg of txq %u",
663 txq->port_id, txq->idx);
667 addr = RTE_PTR_ADD(addr, offset);
668 ppriv->uar_table[txq->idx] = addr;
669 txq_uar_ncattr_init(txq_ctrl, page_size);
674 * Unmap UAR register of a Tx queue for secondary process.
677 * Pointer to Tx queue control structure.
680 txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl)
682 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(txq_ctrl->priv));
684 const size_t page_size = rte_mem_page_size();
685 if (page_size == (size_t)-1) {
686 DRV_LOG(ERR, "Failed to get mem page size");
690 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
692 addr = ppriv->uar_table[txq_ctrl->txq.idx];
693 rte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
697 * Deinitialize Tx UAR registers for secondary process.
700 * Pointer to Ethernet device.
703 mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev)
705 struct mlx5_priv *priv = dev->data->dev_private;
706 struct mlx5_txq_data *txq;
707 struct mlx5_txq_ctrl *txq_ctrl;
710 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);
711 for (i = 0; i != priv->txqs_n; ++i) {
712 if (!(*priv->txqs)[i])
714 txq = (*priv->txqs)[i];
715 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
716 txq_uar_uninit_secondary(txq_ctrl);
721 * Initialize Tx UAR registers for secondary process.
724 * Pointer to Ethernet device.
726 * Verbs file descriptor to map UAR pages.
729 * 0 on success, a negative errno value otherwise and rte_errno is set.
732 mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd)
734 struct mlx5_priv *priv = dev->data->dev_private;
735 struct mlx5_txq_data *txq;
736 struct mlx5_txq_ctrl *txq_ctrl;
740 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);
741 for (i = 0; i != priv->txqs_n; ++i) {
742 if (!(*priv->txqs)[i])
744 txq = (*priv->txqs)[i];
745 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
746 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
748 MLX5_ASSERT(txq->idx == (uint16_t)i);
749 ret = txq_uar_init_secondary(txq_ctrl, fd);
757 if (!(*priv->txqs)[i])
759 txq = (*priv->txqs)[i];
760 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
761 txq_uar_uninit_secondary(txq_ctrl);
767 * Create the Tx hairpin queue object.
770 * Pointer to Ethernet device.
772 * Queue index in DPDK Tx queue array
775 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
777 static struct mlx5_txq_obj *
778 mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
780 struct mlx5_priv *priv = dev->data->dev_private;
781 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
782 struct mlx5_txq_ctrl *txq_ctrl =
783 container_of(txq_data, struct mlx5_txq_ctrl, txq);
784 struct mlx5_devx_create_sq_attr attr = { 0 };
785 struct mlx5_txq_obj *tmpl = NULL;
786 uint32_t max_wq_data;
788 MLX5_ASSERT(txq_data);
789 MLX5_ASSERT(!txq_ctrl->obj);
790 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
794 "port %u Tx queue %u cannot allocate memory resources",
795 dev->data->port_id, txq_data->idx);
799 tmpl->type = MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN;
800 tmpl->txq_ctrl = txq_ctrl;
803 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
804 /* Jumbo frames > 9KB should be supported, and more packets. */
805 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
806 if (priv->config.log_hp_size > max_wq_data) {
807 DRV_LOG(ERR, "total data size %u power of 2 is "
808 "too large for hairpin",
809 priv->config.log_hp_size);
814 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
816 attr.wq_attr.log_hairpin_data_sz =
817 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
818 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
820 /* Set the packets number to the maximum value for performance. */
821 attr.wq_attr.log_hairpin_num_packets =
822 attr.wq_attr.log_hairpin_data_sz -
823 MLX5_HAIRPIN_QUEUE_STRIDE;
824 attr.tis_num = priv->sh->tis->id;
825 tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->ctx, &attr);
828 "port %u tx hairpin queue %u can't create sq object",
829 dev->data->port_id, idx);
834 DRV_LOG(DEBUG, "port %u sxq %u updated with %p", dev->data->port_id,
836 rte_atomic32_inc(&tmpl->refcnt);
837 LIST_INSERT_HEAD(&priv->txqsobj, tmpl, next);
842 * Destroy the Tx queue DevX object.
845 * Txq object to destroy
848 txq_release_sq_resources(struct mlx5_txq_obj *txq_obj)
850 MLX5_ASSERT(txq_obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_SQ);
852 if (txq_obj->sq_devx)
853 claim_zero(mlx5_devx_cmd_destroy(txq_obj->sq_devx));
854 if (txq_obj->sq_dbrec_page)
855 claim_zero(mlx5_release_dbr
856 (&txq_obj->txq_ctrl->priv->dbrpgs,
858 (txq_obj->sq_dbrec_page->umem),
859 txq_obj->sq_dbrec_offset));
860 if (txq_obj->sq_umem)
861 claim_zero(mlx5_glue->devx_umem_dereg(txq_obj->sq_umem));
863 mlx5_free(txq_obj->sq_buf);
864 if (txq_obj->cq_devx)
865 claim_zero(mlx5_devx_cmd_destroy(txq_obj->cq_devx));
866 if (txq_obj->cq_dbrec_page)
867 claim_zero(mlx5_release_dbr
868 (&txq_obj->txq_ctrl->priv->dbrpgs,
870 (txq_obj->cq_dbrec_page->umem),
871 txq_obj->cq_dbrec_offset));
872 if (txq_obj->cq_umem)
873 claim_zero(mlx5_glue->devx_umem_dereg(txq_obj->cq_umem));
875 mlx5_free(txq_obj->cq_buf);
879 * Create the Tx queue DevX object.
882 * Pointer to Ethernet device.
884 * Queue index in DPDK Tx queue array
887 * The DevX object initialised, NULL otherwise and rte_errno is set.
889 static struct mlx5_txq_obj *
890 mlx5_txq_obj_devx_new(struct rte_eth_dev *dev, uint16_t idx)
892 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET
893 DRV_LOG(ERR, "port %u Tx queue %u cannot create with DevX, no UAR",
894 dev->data->port_id, idx);
898 struct mlx5_priv *priv = dev->data->dev_private;
899 struct mlx5_dev_ctx_shared *sh = priv->sh;
900 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
901 struct mlx5_txq_ctrl *txq_ctrl =
902 container_of(txq_data, struct mlx5_txq_ctrl, txq);
903 struct mlx5_devx_create_sq_attr sq_attr = { 0 };
904 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
905 struct mlx5_devx_cq_attr cq_attr = { 0 };
906 struct mlx5_txq_obj *txq_obj = NULL;
908 struct mlx5_cqe *cqe;
910 size_t alignment = (size_t)-1;
913 MLX5_ASSERT(txq_data);
914 MLX5_ASSERT(!txq_ctrl->obj);
915 page_size = rte_mem_page_size();
916 if (page_size == (size_t)-1) {
917 DRV_LOG(ERR, "Failed to get mem page size");
921 txq_obj = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
922 sizeof(struct mlx5_txq_obj), 0,
926 "port %u Tx queue %u cannot allocate memory resources",
927 dev->data->port_id, txq_data->idx);
931 txq_obj->type = MLX5_TXQ_OBJ_TYPE_DEVX_SQ;
932 txq_obj->txq_ctrl = txq_ctrl;
934 /* Create the Completion Queue. */
935 nqe = (1UL << txq_data->elts_n) / MLX5_TX_COMP_THRESH +
936 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
937 nqe = 1UL << log2above(nqe);
938 if (nqe > UINT16_MAX) {
940 "port %u Tx queue %u requests to many CQEs %u",
941 dev->data->port_id, txq_data->idx, nqe);
945 /* Allocate memory buffer for CQEs. */
946 alignment = MLX5_CQE_BUF_ALIGNMENT;
947 if (alignment == (size_t)-1) {
948 DRV_LOG(ERR, "Failed to get mem page size");
952 txq_obj->cq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
953 nqe * sizeof(struct mlx5_cqe),
956 if (!txq_obj->cq_buf) {
958 "port %u Tx queue %u cannot allocate memory (CQ)",
959 dev->data->port_id, txq_data->idx);
963 txq_data->cqe_n = log2above(nqe);
964 txq_data->cqe_s = 1 << txq_data->cqe_n;
965 txq_data->cqe_m = txq_data->cqe_s - 1;
966 txq_data->cqes = (volatile struct mlx5_cqe *)txq_obj->cq_buf;
969 /* Register allocated buffer in user space with DevX. */
970 txq_obj->cq_umem = mlx5_glue->devx_umem_reg
972 (void *)txq_obj->cq_buf,
973 nqe * sizeof(struct mlx5_cqe),
974 IBV_ACCESS_LOCAL_WRITE);
975 if (!txq_obj->cq_umem) {
978 "port %u Tx queue %u cannot register memory (CQ)",
979 dev->data->port_id, txq_data->idx);
982 /* Allocate doorbell record for completion queue. */
983 txq_obj->cq_dbrec_offset = mlx5_get_dbr(sh->ctx,
985 &txq_obj->cq_dbrec_page);
986 if (txq_obj->cq_dbrec_offset < 0)
988 txq_data->cq_db = (volatile uint32_t *)(txq_obj->cq_dbrec_page->dbrs +
989 txq_obj->cq_dbrec_offset);
990 *txq_data->cq_db = 0;
991 /* Create completion queue object with DevX. */
992 cq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?
993 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;
994 cq_attr.uar_page_id = sh->tx_uar->page_id;
995 cq_attr.eqn = sh->txpp.eqn;
996 cq_attr.q_umem_valid = 1;
997 cq_attr.q_umem_offset = (uintptr_t)txq_obj->cq_buf % page_size;
998 cq_attr.q_umem_id = txq_obj->cq_umem->umem_id;
999 cq_attr.db_umem_valid = 1;
1000 cq_attr.db_umem_offset = txq_obj->cq_dbrec_offset;
1001 cq_attr.db_umem_id = mlx5_os_get_umem_id(txq_obj->cq_dbrec_page->umem);
1002 cq_attr.log_cq_size = rte_log2_u32(nqe);
1003 cq_attr.log_page_size = rte_log2_u32(page_size);
1004 txq_obj->cq_devx = mlx5_devx_cmd_create_cq(sh->ctx, &cq_attr);
1005 if (!txq_obj->cq_devx) {
1007 DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
1008 dev->data->port_id, idx);
1011 /* Initial fill CQ buffer with invalid CQE opcode. */
1012 cqe = (struct mlx5_cqe *)txq_obj->cq_buf;
1013 for (i = 0; i < txq_data->cqe_s; i++) {
1014 cqe->op_own = (MLX5_CQE_INVALID << 4) | MLX5_CQE_OWNER_MASK;
1017 /* Create the Work Queue. */
1018 nqe = RTE_MIN(1UL << txq_data->elts_n,
1019 (uint32_t)sh->device_attr.max_qp_wr);
1020 txq_obj->sq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
1021 nqe * sizeof(struct mlx5_wqe),
1022 page_size, sh->numa_node);
1023 if (!txq_obj->sq_buf) {
1025 "port %u Tx queue %u cannot allocate memory (SQ)",
1026 dev->data->port_id, txq_data->idx);
1030 txq_data->wqe_n = log2above(nqe);
1031 txq_data->wqe_s = 1 << txq_data->wqe_n;
1032 txq_data->wqe_m = txq_data->wqe_s - 1;
1033 txq_data->wqes = (struct mlx5_wqe *)txq_obj->sq_buf;
1034 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
1035 txq_data->wqe_ci = 0;
1036 txq_data->wqe_pi = 0;
1037 txq_data->wqe_comp = 0;
1038 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
1039 /* Register allocated buffer in user space with DevX. */
1040 txq_obj->sq_umem = mlx5_glue->devx_umem_reg
1042 (void *)txq_obj->sq_buf,
1043 nqe * sizeof(struct mlx5_wqe),
1044 IBV_ACCESS_LOCAL_WRITE);
1045 if (!txq_obj->sq_umem) {
1048 "port %u Tx queue %u cannot register memory (SQ)",
1049 dev->data->port_id, txq_data->idx);
1052 /* Allocate doorbell record for completion queue. */
1053 txq_obj->cq_dbrec_offset = mlx5_get_dbr(sh->ctx,
1055 &txq_obj->sq_dbrec_page);
1056 if (txq_obj->sq_dbrec_offset < 0)
1058 txq_data->qp_db = (volatile uint32_t *)
1059 (txq_obj->sq_dbrec_page->dbrs +
1060 txq_obj->sq_dbrec_offset +
1061 MLX5_SND_DBR * sizeof(uint32_t));
1062 *txq_data->qp_db = 0;
1063 /* Create Send Queue object with DevX. */
1064 sq_attr.tis_lst_sz = 1;
1065 sq_attr.tis_num = sh->tis->id;
1066 sq_attr.state = MLX5_SQC_STATE_RST;
1067 sq_attr.cqn = txq_obj->cq_devx->id;
1068 sq_attr.flush_in_error_en = 1;
1069 sq_attr.allow_multi_pkt_send_wqe = !!priv->config.mps;
1070 sq_attr.allow_swp = !!priv->config.swp;
1071 sq_attr.min_wqe_inline_mode = priv->config.hca_attr.vport_inline_mode;
1072 sq_attr.wq_attr.uar_page = sh->tx_uar->page_id;
1073 sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1074 sq_attr.wq_attr.pd = sh->pdn;
1075 sq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);
1076 sq_attr.wq_attr.log_wq_sz = txq_data->wqe_n;
1077 sq_attr.wq_attr.dbr_umem_valid = 1;
1078 sq_attr.wq_attr.dbr_addr = txq_obj->cq_dbrec_offset;
1079 sq_attr.wq_attr.dbr_umem_id =
1080 mlx5_os_get_umem_id(txq_obj->cq_dbrec_page->umem);
1081 sq_attr.wq_attr.wq_umem_valid = 1;
1082 sq_attr.wq_attr.wq_umem_id = txq_obj->sq_umem->umem_id;
1083 sq_attr.wq_attr.wq_umem_offset = (uintptr_t)txq_obj->sq_buf % page_size;
1084 txq_obj->sq_devx = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr);
1085 if (!txq_obj->sq_devx) {
1087 DRV_LOG(ERR, "port %u Tx queue %u SQ creation failure",
1088 dev->data->port_id, idx);
1091 txq_data->qp_num_8s = txq_obj->sq_devx->id << 8;
1092 /* Change Send Queue state to Ready-to-Send. */
1093 msq_attr.sq_state = MLX5_SQC_STATE_RST;
1094 msq_attr.state = MLX5_SQC_STATE_RDY;
1095 ret = mlx5_devx_cmd_modify_sq(txq_obj->sq_devx, &msq_attr);
1099 "port %u Tx queue %u SP state to SQC_STATE_RDY failed",
1100 dev->data->port_id, idx);
1103 txq_data->fcqs = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
1104 txq_data->cqe_s * sizeof(*txq_data->fcqs),
1105 RTE_CACHE_LINE_SIZE,
1107 if (!txq_data->fcqs) {
1108 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory (FCQ)",
1109 dev->data->port_id, idx);
1113 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1115 * If using DevX need to query and store TIS transport domain value.
1116 * This is done once per port.
1117 * Will use this value on Rx, when creating matching TIR.
1119 if (priv->config.devx && !priv->sh->tdn)
1120 priv->sh->tdn = priv->sh->td->id;
1122 MLX5_ASSERT(sh->tx_uar);
1123 MLX5_ASSERT(sh->tx_uar->reg_addr);
1124 txq_ctrl->bf_reg = sh->tx_uar->reg_addr;
1125 txq_ctrl->uar_mmap_offset = sh->tx_uar->mmap_off;
1126 rte_atomic32_set(&txq_obj->refcnt, 1);
1127 txq_uar_init(txq_ctrl);
1128 LIST_INSERT_HEAD(&priv->txqsobj, txq_obj, next);
1131 ret = rte_errno; /* Save rte_errno before cleanup. */
1132 txq_release_sq_resources(txq_obj);
1133 if (txq_data->fcqs) {
1134 mlx5_free(txq_data->fcqs);
1135 txq_data->fcqs = NULL;
1138 rte_errno = ret; /* Restore rte_errno. */
1144 * Create the Tx queue Verbs object.
1147 * Pointer to Ethernet device.
1149 * Queue index in DPDK Tx queue array.
1151 * Type of the Tx queue object to create.
1154 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1156 struct mlx5_txq_obj *
1157 mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1158 enum mlx5_txq_obj_type type)
1160 struct mlx5_priv *priv = dev->data->dev_private;
1161 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1162 struct mlx5_txq_ctrl *txq_ctrl =
1163 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1164 struct mlx5_txq_obj tmpl;
1165 struct mlx5_txq_obj *txq_obj = NULL;
1167 struct ibv_qp_init_attr_ex init;
1168 struct ibv_cq_init_attr_ex cq;
1169 struct ibv_qp_attr mod;
1172 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
1173 struct mlx5dv_cq cq_info;
1174 struct mlx5dv_obj obj;
1175 const int desc = 1 << txq_data->elts_n;
1178 if (type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN)
1179 return mlx5_txq_obj_hairpin_new(dev, idx);
1180 if (type == MLX5_TXQ_OBJ_TYPE_DEVX_SQ)
1181 return mlx5_txq_obj_devx_new(dev, idx);
1182 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1183 /* If using DevX, need additional mask to read tisn value. */
1184 if (priv->config.devx && !priv->sh->tdn)
1185 qp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;
1187 MLX5_ASSERT(txq_data);
1188 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
1189 priv->verbs_alloc_ctx.obj = txq_ctrl;
1190 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
1192 "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set",
1193 dev->data->port_id);
1197 memset(&tmpl, 0, sizeof(struct mlx5_txq_obj));
1198 attr.cq = (struct ibv_cq_init_attr_ex){
1201 cqe_n = desc / MLX5_TX_COMP_THRESH +
1202 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
1203 tmpl.cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);
1204 if (tmpl.cq == NULL) {
1205 DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
1206 dev->data->port_id, idx);
1210 attr.init = (struct ibv_qp_init_attr_ex){
1211 /* CQ to be associated with the send queue. */
1213 /* CQ to be associated with the receive queue. */
1216 /* Max number of outstanding WRs. */
1218 ((priv->sh->device_attr.max_qp_wr <
1220 priv->sh->device_attr.max_qp_wr :
1223 * Max number of scatter/gather elements in a WR,
1224 * must be 1 to prevent libmlx5 from trying to affect
1225 * too much memory. TX gather is not impacted by the
1226 * device_attr.max_sge limit and will still work
1231 .qp_type = IBV_QPT_RAW_PACKET,
1233 * Do *NOT* enable this, completions events are managed per
1238 .comp_mask = IBV_QP_INIT_ATTR_PD,
1240 if (txq_data->inlen_send)
1241 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
1242 if (txq_data->tso_en) {
1243 attr.init.max_tso_header = txq_ctrl->max_tso_header;
1244 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
1246 tmpl.qp = mlx5_glue->create_qp_ex(priv->sh->ctx, &attr.init);
1247 if (tmpl.qp == NULL) {
1248 DRV_LOG(ERR, "port %u Tx queue %u QP creation failure",
1249 dev->data->port_id, idx);
1253 attr.mod = (struct ibv_qp_attr){
1254 /* Move the QP to this state. */
1255 .qp_state = IBV_QPS_INIT,
1256 /* IB device port number. */
1257 .port_num = (uint8_t)priv->dev_port,
1259 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
1260 (IBV_QP_STATE | IBV_QP_PORT));
1263 "port %u Tx queue %u QP state to IBV_QPS_INIT failed",
1264 dev->data->port_id, idx);
1268 attr.mod = (struct ibv_qp_attr){
1269 .qp_state = IBV_QPS_RTR
1271 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
1274 "port %u Tx queue %u QP state to IBV_QPS_RTR failed",
1275 dev->data->port_id, idx);
1279 attr.mod.qp_state = IBV_QPS_RTS;
1280 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
1283 "port %u Tx queue %u QP state to IBV_QPS_RTS failed",
1284 dev->data->port_id, idx);
1288 txq_obj = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
1289 sizeof(struct mlx5_txq_obj), 0,
1292 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory",
1293 dev->data->port_id, idx);
1297 obj.cq.in = tmpl.cq;
1298 obj.cq.out = &cq_info;
1299 obj.qp.in = tmpl.qp;
1301 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
1306 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1308 "port %u wrong MLX5_CQE_SIZE environment variable"
1309 " value: it should be set to %u",
1310 dev->data->port_id, RTE_CACHE_LINE_SIZE);
1314 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
1315 txq_data->cqe_s = 1 << txq_data->cqe_n;
1316 txq_data->cqe_m = txq_data->cqe_s - 1;
1317 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
1318 txq_data->wqes = qp.sq.buf;
1319 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
1320 txq_data->wqe_s = 1 << txq_data->wqe_n;
1321 txq_data->wqe_m = txq_data->wqe_s - 1;
1322 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
1323 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
1324 txq_data->cq_db = cq_info.dbrec;
1325 txq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf;
1326 txq_data->cq_ci = 0;
1327 txq_data->cq_pi = 0;
1328 txq_data->wqe_ci = 0;
1329 txq_data->wqe_pi = 0;
1330 txq_data->wqe_comp = 0;
1331 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
1332 txq_data->fcqs = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
1333 txq_data->cqe_s * sizeof(*txq_data->fcqs),
1334 RTE_CACHE_LINE_SIZE, txq_ctrl->socket);
1335 if (!txq_data->fcqs) {
1336 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory (FCQ)",
1337 dev->data->port_id, idx);
1341 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1343 * If using DevX need to query and store TIS transport domain value.
1344 * This is done once per port.
1345 * Will use this value on Rx, when creating matching TIR.
1347 if (priv->config.devx && !priv->sh->tdn) {
1348 ret = mlx5_devx_cmd_qp_query_tis_td(tmpl.qp, qp.tisn,
1351 DRV_LOG(ERR, "Fail to query port %u Tx queue %u QP TIS "
1352 "transport domain", dev->data->port_id, idx);
1356 DRV_LOG(DEBUG, "port %u Tx queue %u TIS number %d "
1357 "transport domain %d", dev->data->port_id,
1358 idx, qp.tisn, priv->sh->tdn);
1362 txq_obj->qp = tmpl.qp;
1363 txq_obj->cq = tmpl.cq;
1364 rte_atomic32_inc(&txq_obj->refcnt);
1365 txq_ctrl->bf_reg = qp.bf.reg;
1366 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
1367 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
1368 DRV_LOG(DEBUG, "port %u: uar_mmap_offset 0x%"PRIx64,
1369 dev->data->port_id, txq_ctrl->uar_mmap_offset);
1372 "port %u failed to retrieve UAR info, invalid"
1374 dev->data->port_id);
1378 txq_uar_init(txq_ctrl);
1379 LIST_INSERT_HEAD(&priv->txqsobj, txq_obj, next);
1380 txq_obj->txq_ctrl = txq_ctrl;
1381 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1384 ret = rte_errno; /* Save rte_errno before cleanup. */
1386 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
1388 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
1389 if (txq_data && txq_data->fcqs) {
1390 mlx5_free(txq_data->fcqs);
1391 txq_data->fcqs = NULL;
1395 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1396 rte_errno = ret; /* Restore rte_errno. */
1401 * Get an Tx queue Verbs object.
1404 * Pointer to Ethernet device.
1406 * Queue index in DPDK Tx queue array.
1409 * The Verbs object if it exists.
1411 struct mlx5_txq_obj *
1412 mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
1414 struct mlx5_priv *priv = dev->data->dev_private;
1415 struct mlx5_txq_ctrl *txq_ctrl;
1417 if (idx >= priv->txqs_n)
1419 if (!(*priv->txqs)[idx])
1421 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
1423 rte_atomic32_inc(&txq_ctrl->obj->refcnt);
1424 return txq_ctrl->obj;
1428 * Release an Tx verbs queue object.
1431 * Verbs Tx queue object.
1434 * 1 while a reference on it exists, 0 when freed.
1437 mlx5_txq_obj_release(struct mlx5_txq_obj *txq_obj)
1439 MLX5_ASSERT(txq_obj);
1440 if (rte_atomic32_dec_and_test(&txq_obj->refcnt)) {
1441 if (txq_obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN) {
1443 claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));
1444 } else if (txq_obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_SQ) {
1445 txq_release_sq_resources(txq_obj);
1447 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
1448 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
1450 if (txq_obj->txq_ctrl->txq.fcqs) {
1451 mlx5_free(txq_obj->txq_ctrl->txq.fcqs);
1452 txq_obj->txq_ctrl->txq.fcqs = NULL;
1454 LIST_REMOVE(txq_obj, next);
1462 * Verify the Verbs Tx queue list is empty
1465 * Pointer to Ethernet device.
1468 * The number of object not released.
1471 mlx5_txq_obj_verify(struct rte_eth_dev *dev)
1473 struct mlx5_priv *priv = dev->data->dev_private;
1475 struct mlx5_txq_obj *txq_obj;
1477 LIST_FOREACH(txq_obj, &priv->txqsobj, next) {
1478 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced",
1479 dev->data->port_id, txq_obj->txq_ctrl->txq.idx);
1486 * Calculate the total number of WQEBB for Tx queue.
1488 * Simplified version of calc_sq_size() in rdma-core.
1491 * Pointer to Tx queue control structure.
1494 * The number of WQEBB.
1497 txq_calc_wqebb_cnt(struct mlx5_txq_ctrl *txq_ctrl)
1499 unsigned int wqe_size;
1500 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
1502 wqe_size = MLX5_WQE_CSEG_SIZE +
1503 MLX5_WQE_ESEG_SIZE +
1505 MLX5_ESEG_MIN_INLINE_SIZE +
1506 txq_ctrl->max_inline_data;
1507 return rte_align32pow2(wqe_size * desc) / MLX5_WQE_SIZE;
1511 * Calculate the maximal inline data size for Tx queue.
1514 * Pointer to Tx queue control structure.
1517 * The maximal inline data size.
1520 txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl)
1522 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
1523 struct mlx5_priv *priv = txq_ctrl->priv;
1524 unsigned int wqe_size;
1526 wqe_size = priv->sh->device_attr.max_qp_wr / desc;
1530 * This calculation is derived from tthe source of
1531 * mlx5_calc_send_wqe() in rdma_core library.
1533 wqe_size = wqe_size * MLX5_WQE_SIZE -
1534 MLX5_WQE_CSEG_SIZE -
1535 MLX5_WQE_ESEG_SIZE -
1538 MLX5_DSEG_MIN_INLINE_SIZE;
1543 * Set Tx queue parameters from device configuration.
1546 * Pointer to Tx queue control structure.
1549 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
1551 struct mlx5_priv *priv = txq_ctrl->priv;
1552 struct mlx5_dev_config *config = &priv->config;
1553 unsigned int inlen_send; /* Inline data for ordinary SEND.*/
1554 unsigned int inlen_empw; /* Inline data for enhanced MPW. */
1555 unsigned int inlen_mode; /* Minimal required Inline data. */
1556 unsigned int txqs_inline; /* Min Tx queues to enable inline. */
1557 uint64_t dev_txoff = priv->dev_data->dev_conf.txmode.offloads;
1558 bool tso = txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO |
1559 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1560 DEV_TX_OFFLOAD_GRE_TNL_TSO |
1561 DEV_TX_OFFLOAD_IP_TNL_TSO |
1562 DEV_TX_OFFLOAD_UDP_TNL_TSO);
1566 if (config->txqs_inline == MLX5_ARG_UNSET)
1568 #if defined(RTE_ARCH_ARM64)
1569 (priv->pci_dev->id.device_id ==
1570 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) ?
1571 MLX5_INLINE_MAX_TXQS_BLUEFIELD :
1573 MLX5_INLINE_MAX_TXQS;
1575 txqs_inline = (unsigned int)config->txqs_inline;
1576 inlen_send = (config->txq_inline_max == MLX5_ARG_UNSET) ?
1577 MLX5_SEND_DEF_INLINE_LEN :
1578 (unsigned int)config->txq_inline_max;
1579 inlen_empw = (config->txq_inline_mpw == MLX5_ARG_UNSET) ?
1580 MLX5_EMPW_DEF_INLINE_LEN :
1581 (unsigned int)config->txq_inline_mpw;
1582 inlen_mode = (config->txq_inline_min == MLX5_ARG_UNSET) ?
1583 0 : (unsigned int)config->txq_inline_min;
1584 if (config->mps != MLX5_MPW_ENHANCED && config->mps != MLX5_MPW)
1587 * If there is requested minimal amount of data to inline
1588 * we MUST enable inlining. This is a case for ConnectX-4
1589 * which usually requires L2 inlined for correct operating
1590 * and ConnectX-4 Lx which requires L2-L4 inlined to
1591 * support E-Switch Flows.
1594 if (inlen_mode <= MLX5_ESEG_MIN_INLINE_SIZE) {
1596 * Optimize minimal inlining for single
1597 * segment packets to fill one WQEBB
1600 temp = MLX5_ESEG_MIN_INLINE_SIZE;
1602 temp = inlen_mode - MLX5_ESEG_MIN_INLINE_SIZE;
1603 temp = RTE_ALIGN(temp, MLX5_WSEG_SIZE) +
1604 MLX5_ESEG_MIN_INLINE_SIZE;
1605 temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN);
1607 if (temp != inlen_mode) {
1609 "port %u minimal required inline setting"
1610 " aligned from %u to %u",
1611 PORT_ID(priv), inlen_mode, temp);
1616 * If port is configured to support VLAN insertion and device
1617 * does not support this feature by HW (for NICs before ConnectX-5
1618 * or in case of wqe_vlan_insert flag is not set) we must enable
1619 * data inline on all queues because it is supported by single
1622 txq_ctrl->txq.vlan_en = config->hw_vlan_insert;
1623 vlan_inline = (dev_txoff & DEV_TX_OFFLOAD_VLAN_INSERT) &&
1624 !config->hw_vlan_insert;
1626 * If there are few Tx queues it is prioritized
1627 * to save CPU cycles and disable data inlining at all.
1629 if (inlen_send && priv->txqs_n >= txqs_inline) {
1631 * The data sent with ordinal MLX5_OPCODE_SEND
1632 * may be inlined in Ethernet Segment, align the
1633 * length accordingly to fit entire WQEBBs.
1635 temp = RTE_MAX(inlen_send,
1636 MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE);
1637 temp -= MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE;
1638 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE);
1639 temp += MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE;
1640 temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX +
1641 MLX5_ESEG_MIN_INLINE_SIZE -
1642 MLX5_WQE_CSEG_SIZE -
1643 MLX5_WQE_ESEG_SIZE -
1644 MLX5_WQE_DSEG_SIZE * 2);
1645 temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN);
1646 temp = RTE_MAX(temp, inlen_mode);
1647 if (temp != inlen_send) {
1649 "port %u ordinary send inline setting"
1650 " aligned from %u to %u",
1651 PORT_ID(priv), inlen_send, temp);
1655 * Not aligned to cache lines, but to WQEs.
1656 * First bytes of data (initial alignment)
1657 * is going to be copied explicitly at the
1658 * beginning of inlining buffer in Ethernet
1661 MLX5_ASSERT(inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
1662 MLX5_ASSERT(inlen_send <= MLX5_WQE_SIZE_MAX +
1663 MLX5_ESEG_MIN_INLINE_SIZE -
1664 MLX5_WQE_CSEG_SIZE -
1665 MLX5_WQE_ESEG_SIZE -
1666 MLX5_WQE_DSEG_SIZE * 2);
1667 } else if (inlen_mode) {
1669 * If minimal inlining is requested we must
1670 * enable inlining in general, despite the
1671 * number of configured queues. Ignore the
1672 * txq_inline_max devarg, this is not
1673 * full-featured inline.
1675 inlen_send = inlen_mode;
1677 } else if (vlan_inline) {
1679 * Hardware does not report offload for
1680 * VLAN insertion, we must enable data inline
1681 * to implement feature by software.
1683 inlen_send = MLX5_ESEG_MIN_INLINE_SIZE;
1689 txq_ctrl->txq.inlen_send = inlen_send;
1690 txq_ctrl->txq.inlen_mode = inlen_mode;
1691 txq_ctrl->txq.inlen_empw = 0;
1692 if (inlen_send && inlen_empw && priv->txqs_n >= txqs_inline) {
1694 * The data sent with MLX5_OPCODE_ENHANCED_MPSW
1695 * may be inlined in Data Segment, align the
1696 * length accordingly to fit entire WQEBBs.
1698 temp = RTE_MAX(inlen_empw,
1699 MLX5_WQE_SIZE + MLX5_DSEG_MIN_INLINE_SIZE);
1700 temp -= MLX5_DSEG_MIN_INLINE_SIZE;
1701 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE);
1702 temp += MLX5_DSEG_MIN_INLINE_SIZE;
1703 temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX +
1704 MLX5_DSEG_MIN_INLINE_SIZE -
1705 MLX5_WQE_CSEG_SIZE -
1706 MLX5_WQE_ESEG_SIZE -
1707 MLX5_WQE_DSEG_SIZE);
1708 temp = RTE_MIN(temp, MLX5_EMPW_MAX_INLINE_LEN);
1709 if (temp != inlen_empw) {
1711 "port %u enhanced empw inline setting"
1712 " aligned from %u to %u",
1713 PORT_ID(priv), inlen_empw, temp);
1716 MLX5_ASSERT(inlen_empw >= MLX5_ESEG_MIN_INLINE_SIZE);
1717 MLX5_ASSERT(inlen_empw <= MLX5_WQE_SIZE_MAX +
1718 MLX5_DSEG_MIN_INLINE_SIZE -
1719 MLX5_WQE_CSEG_SIZE -
1720 MLX5_WQE_ESEG_SIZE -
1721 MLX5_WQE_DSEG_SIZE);
1722 txq_ctrl->txq.inlen_empw = inlen_empw;
1724 txq_ctrl->max_inline_data = RTE_MAX(inlen_send, inlen_empw);
1726 txq_ctrl->max_tso_header = MLX5_MAX_TSO_HEADER;
1727 txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->max_inline_data,
1728 MLX5_MAX_TSO_HEADER);
1729 txq_ctrl->txq.tso_en = 1;
1731 txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
1732 txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
1733 DEV_TX_OFFLOAD_UDP_TNL_TSO |
1734 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
1735 txq_ctrl->txq.offloads) && config->swp;
1739 * Adjust Tx queue data inline parameters for large queue sizes.
1740 * The data inline feature requires multiple WQEs to fit the packets,
1741 * and if the large amount of Tx descriptors is requested by application
1742 * the total WQE amount may exceed the hardware capabilities. If the
1743 * default inline setting are used we can try to adjust these ones and
1744 * meet the hardware requirements and not exceed the queue size.
1747 * Pointer to Tx queue control structure.
1750 * Zero on success, otherwise the parameters can not be adjusted.
1753 txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)
1755 struct mlx5_priv *priv = txq_ctrl->priv;
1756 struct mlx5_dev_config *config = &priv->config;
1757 unsigned int max_inline;
1759 max_inline = txq_calc_inline_max(txq_ctrl);
1760 if (!txq_ctrl->txq.inlen_send) {
1762 * Inline data feature is not engaged at all.
1763 * There is nothing to adjust.
1767 if (txq_ctrl->max_inline_data <= max_inline) {
1769 * The requested inline data length does not
1770 * exceed queue capabilities.
1774 if (txq_ctrl->txq.inlen_mode > max_inline) {
1776 "minimal data inline requirements (%u) are not"
1777 " satisfied (%u) on port %u, try the smaller"
1778 " Tx queue size (%d)",
1779 txq_ctrl->txq.inlen_mode, max_inline,
1780 priv->dev_data->port_id,
1781 priv->sh->device_attr.max_qp_wr);
1784 if (txq_ctrl->txq.inlen_send > max_inline &&
1785 config->txq_inline_max != MLX5_ARG_UNSET &&
1786 config->txq_inline_max > (int)max_inline) {
1788 "txq_inline_max requirements (%u) are not"
1789 " satisfied (%u) on port %u, try the smaller"
1790 " Tx queue size (%d)",
1791 txq_ctrl->txq.inlen_send, max_inline,
1792 priv->dev_data->port_id,
1793 priv->sh->device_attr.max_qp_wr);
1796 if (txq_ctrl->txq.inlen_empw > max_inline &&
1797 config->txq_inline_mpw != MLX5_ARG_UNSET &&
1798 config->txq_inline_mpw > (int)max_inline) {
1800 "txq_inline_mpw requirements (%u) are not"
1801 " satisfied (%u) on port %u, try the smaller"
1802 " Tx queue size (%d)",
1803 txq_ctrl->txq.inlen_empw, max_inline,
1804 priv->dev_data->port_id,
1805 priv->sh->device_attr.max_qp_wr);
1808 if (txq_ctrl->txq.tso_en && max_inline < MLX5_MAX_TSO_HEADER) {
1810 "tso header inline requirements (%u) are not"
1811 " satisfied (%u) on port %u, try the smaller"
1812 " Tx queue size (%d)",
1813 MLX5_MAX_TSO_HEADER, max_inline,
1814 priv->dev_data->port_id,
1815 priv->sh->device_attr.max_qp_wr);
1818 if (txq_ctrl->txq.inlen_send > max_inline) {
1820 "adjust txq_inline_max (%u->%u)"
1821 " due to large Tx queue on port %u",
1822 txq_ctrl->txq.inlen_send, max_inline,
1823 priv->dev_data->port_id);
1824 txq_ctrl->txq.inlen_send = max_inline;
1826 if (txq_ctrl->txq.inlen_empw > max_inline) {
1828 "adjust txq_inline_mpw (%u->%u)"
1829 "due to large Tx queue on port %u",
1830 txq_ctrl->txq.inlen_empw, max_inline,
1831 priv->dev_data->port_id);
1832 txq_ctrl->txq.inlen_empw = max_inline;
1834 txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->txq.inlen_send,
1835 txq_ctrl->txq.inlen_empw);
1836 MLX5_ASSERT(txq_ctrl->max_inline_data <= max_inline);
1837 MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= max_inline);
1838 MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send);
1839 MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw ||
1840 !txq_ctrl->txq.inlen_empw);
1848 * Create a DPDK Tx queue.
1851 * Pointer to Ethernet device.
1855 * Number of descriptors to configure in queue.
1857 * NUMA socket on which memory must be allocated.
1859 * Thresholds parameters.
1862 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1864 struct mlx5_txq_ctrl *
1865 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1866 unsigned int socket, const struct rte_eth_txconf *conf)
1868 struct mlx5_priv *priv = dev->data->dev_private;
1869 struct mlx5_txq_ctrl *tmpl;
1871 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) +
1872 desc * sizeof(struct rte_mbuf *), 0, socket);
1877 if (mlx5_mr_btree_init(&tmpl->txq.mr_ctrl.cache_bh,
1878 MLX5_MR_BTREE_CACHE_N, socket)) {
1879 /* rte_errno is already set. */
1882 /* Save pointer of global generation number to check memory event. */
1883 tmpl->txq.mr_ctrl.dev_gen_ptr = &priv->sh->share_cache.dev_gen;
1884 MLX5_ASSERT(desc > MLX5_TX_COMP_THRESH);
1885 tmpl->txq.offloads = conf->offloads |
1886 dev->data->dev_conf.txmode.offloads;
1888 tmpl->socket = socket;
1889 tmpl->txq.elts_n = log2above(desc);
1890 tmpl->txq.elts_s = desc;
1891 tmpl->txq.elts_m = desc - 1;
1892 tmpl->txq.port_id = dev->data->port_id;
1893 tmpl->txq.idx = idx;
1894 txq_set_params(tmpl);
1895 if (txq_adjust_params(tmpl))
1897 if (txq_calc_wqebb_cnt(tmpl) >
1898 priv->sh->device_attr.max_qp_wr) {
1900 "port %u Tx WQEBB count (%d) exceeds the limit (%d),"
1901 " try smaller queue size",
1902 dev->data->port_id, txq_calc_wqebb_cnt(tmpl),
1903 priv->sh->device_attr.max_qp_wr);
1907 rte_atomic32_inc(&tmpl->refcnt);
1908 tmpl->type = MLX5_TXQ_TYPE_STANDARD;
1909 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
1917 * Create a DPDK Tx hairpin queue.
1920 * Pointer to Ethernet device.
1924 * Number of descriptors to configure in queue.
1925 * @param hairpin_conf
1926 * The hairpin configuration.
1929 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1931 struct mlx5_txq_ctrl *
1932 mlx5_txq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1933 const struct rte_eth_hairpin_conf *hairpin_conf)
1935 struct mlx5_priv *priv = dev->data->dev_private;
1936 struct mlx5_txq_ctrl *tmpl;
1938 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1945 tmpl->socket = SOCKET_ID_ANY;
1946 tmpl->txq.elts_n = log2above(desc);
1947 tmpl->txq.port_id = dev->data->port_id;
1948 tmpl->txq.idx = idx;
1949 tmpl->hairpin_conf = *hairpin_conf;
1950 tmpl->type = MLX5_TXQ_TYPE_HAIRPIN;
1951 rte_atomic32_inc(&tmpl->refcnt);
1952 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
1960 * Pointer to Ethernet device.
1965 * A pointer to the queue if it exists.
1967 struct mlx5_txq_ctrl *
1968 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
1970 struct mlx5_priv *priv = dev->data->dev_private;
1971 struct mlx5_txq_ctrl *ctrl = NULL;
1973 if ((*priv->txqs)[idx]) {
1974 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
1976 mlx5_txq_obj_get(dev, idx);
1977 rte_atomic32_inc(&ctrl->refcnt);
1983 * Release a Tx queue.
1986 * Pointer to Ethernet device.
1991 * 1 while a reference on it exists, 0 when freed.
1994 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
1996 struct mlx5_priv *priv = dev->data->dev_private;
1997 struct mlx5_txq_ctrl *txq;
1999 if (!(*priv->txqs)[idx])
2001 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
2002 if (txq->obj && !mlx5_txq_obj_release(txq->obj))
2004 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
2006 mlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh);
2007 LIST_REMOVE(txq, next);
2009 (*priv->txqs)[idx] = NULL;
2010 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
2017 * Verify if the queue can be released.
2020 * Pointer to Ethernet device.
2025 * 1 if the queue can be released.
2028 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
2030 struct mlx5_priv *priv = dev->data->dev_private;
2031 struct mlx5_txq_ctrl *txq;
2033 if (!(*priv->txqs)[idx])
2035 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
2036 return (rte_atomic32_read(&txq->refcnt) == 1);
2040 * Verify the Tx Queue list is empty
2043 * Pointer to Ethernet device.
2046 * The number of object not released.
2049 mlx5_txq_verify(struct rte_eth_dev *dev)
2051 struct mlx5_priv *priv = dev->data->dev_private;
2052 struct mlx5_txq_ctrl *txq_ctrl;
2055 LIST_FOREACH(txq_ctrl, &priv->txqsctrl, next) {
2056 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced",
2057 dev->data->port_id, txq_ctrl->txq.idx);
2064 * Set the Tx queue dynamic timestamp (mask and offset)
2067 * Pointer to the Ethernet device structure.
2070 mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev)
2072 struct mlx5_priv *priv = dev->data->dev_private;
2073 struct mlx5_dev_ctx_shared *sh = priv->sh;
2074 struct mlx5_txq_data *data;
2079 nbit = rte_mbuf_dynflag_lookup
2080 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
2081 off = rte_mbuf_dynfield_lookup
2082 (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL);
2083 if (nbit > 0 && off >= 0 && sh->txpp.refcnt)
2084 mask = 1ULL << nbit;
2085 for (i = 0; i != priv->txqs_n; ++i) {
2086 data = (*priv->txqs)[i];
2090 data->ts_mask = mask;
2091 data->ts_offset = off;