4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
45 #pragma GCC diagnostic ignored "-Wpedantic"
47 #include <infiniband/verbs.h>
49 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_malloc.h>
54 #include <rte_ethdev.h>
55 #include <rte_common.h>
57 #include "mlx5_utils.h"
58 #include "mlx5_defs.h"
60 #include "mlx5_rxtx.h"
61 #include "mlx5_autoconf.h"
64 * Allocate TX queue elements.
67 * Pointer to TX queue structure.
70 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
72 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
75 for (i = 0; (i != elts_n); ++i)
76 (*txq_ctrl->txq.elts)[i] = NULL;
77 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
78 txq_ctrl->txq.elts_head = 0;
79 txq_ctrl->txq.elts_tail = 0;
80 txq_ctrl->txq.elts_comp = 0;
84 * Free TX queue elements.
87 * Pointer to TX queue structure.
90 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
92 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
93 const uint16_t elts_m = elts_n - 1;
94 uint16_t elts_head = txq_ctrl->txq.elts_head;
95 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
96 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
98 DEBUG("%p: freeing WRs", (void *)txq_ctrl);
99 txq_ctrl->txq.elts_head = 0;
100 txq_ctrl->txq.elts_tail = 0;
101 txq_ctrl->txq.elts_comp = 0;
103 while (elts_tail != elts_head) {
104 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
107 rte_pktmbuf_free_seg(elt);
110 memset(&(*elts)[elts_tail & elts_m],
112 sizeof((*elts)[elts_tail & elts_m]));
119 * Returns the per-port supported offloads.
122 * Pointer to private structure.
125 * Supported Tx offloads.
128 mlx5_priv_get_tx_port_offloads(struct priv *priv)
130 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
131 DEV_TX_OFFLOAD_VLAN_INSERT);
132 struct mlx5_dev_config *config = &priv->config;
135 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
136 DEV_TX_OFFLOAD_UDP_CKSUM |
137 DEV_TX_OFFLOAD_TCP_CKSUM);
139 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
140 if (config->tunnel_en) {
142 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
144 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
145 DEV_TX_OFFLOAD_GRE_TNL_TSO);
151 * Checks if the per-queue offload configuration is valid.
154 * Pointer to private structure.
156 * Per-queue offloads configuration.
159 * 1 if the configuration is valid, 0 otherwise.
162 priv_is_tx_queue_offloads_allowed(struct priv *priv, uint64_t offloads)
164 uint64_t port_offloads = priv->dev->data->dev_conf.txmode.offloads;
165 uint64_t port_supp_offloads = mlx5_priv_get_tx_port_offloads(priv);
167 /* There are no Tx offloads which are per queue. */
168 if ((offloads & port_supp_offloads) != offloads)
170 if ((port_offloads ^ offloads) & port_supp_offloads)
176 * DPDK callback to configure a TX queue.
179 * Pointer to Ethernet device structure.
183 * Number of descriptors to configure in queue.
185 * NUMA socket on which memory must be allocated.
187 * Thresholds parameters.
190 * 0 on success, negative errno value on failure.
193 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
194 unsigned int socket, const struct rte_eth_txconf *conf)
196 struct priv *priv = dev->data->dev_private;
197 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
198 struct mlx5_txq_ctrl *txq_ctrl =
199 container_of(txq, struct mlx5_txq_ctrl, txq);
204 * Don't verify port offloads for application which
207 if (!!(conf->txq_flags & ETH_TXQ_FLAGS_IGNORE) &&
208 !priv_is_tx_queue_offloads_allowed(priv, conf->offloads)) {
210 ERROR("%p: Tx queue offloads 0x%" PRIx64 " don't match port "
211 "offloads 0x%" PRIx64 " or supported offloads 0x%" PRIx64,
212 (void *)dev, conf->offloads,
213 dev->data->dev_conf.txmode.offloads,
214 mlx5_priv_get_tx_port_offloads(priv));
217 if (desc <= MLX5_TX_COMP_THRESH) {
218 WARN("%p: number of descriptors requested for TX queue %u"
219 " must be higher than MLX5_TX_COMP_THRESH, using"
221 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
222 desc = MLX5_TX_COMP_THRESH + 1;
224 if (!rte_is_power_of_2(desc)) {
225 desc = 1 << log2above(desc);
226 WARN("%p: increased number of descriptors in TX queue %u"
227 " to the next power of two (%d)",
228 (void *)dev, idx, desc);
230 DEBUG("%p: configuring queue %u for %u descriptors",
231 (void *)dev, idx, desc);
232 if (idx >= priv->txqs_n) {
233 ERROR("%p: queue index out of range (%u >= %u)",
234 (void *)dev, idx, priv->txqs_n);
238 if (!mlx5_priv_txq_releasable(priv, idx)) {
240 ERROR("%p: unable to release queue index %u",
244 mlx5_priv_txq_release(priv, idx);
245 txq_ctrl = mlx5_priv_txq_new(priv, idx, desc, socket, conf);
247 ERROR("%p: unable to allocate queue index %u",
252 DEBUG("%p: adding TX queue %p to list",
253 (void *)dev, (void *)txq_ctrl);
254 (*priv->txqs)[idx] = &txq_ctrl->txq;
261 * DPDK callback to release a TX queue.
264 * Generic TX queue pointer.
267 mlx5_tx_queue_release(void *dpdk_txq)
269 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
270 struct mlx5_txq_ctrl *txq_ctrl;
276 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
277 priv = txq_ctrl->priv;
279 for (i = 0; (i != priv->txqs_n); ++i)
280 if ((*priv->txqs)[i] == txq) {
281 DEBUG("%p: removing TX queue %p from list",
282 (void *)priv->dev, (void *)txq_ctrl);
283 mlx5_priv_txq_release(priv, i);
291 * Map locally UAR used in Tx queues for BlueFlame doorbell.
294 * Pointer to private structure.
296 * Verbs file descriptor to map UAR pages.
299 * 0 on success, errno value on failure.
302 priv_tx_uar_remap(struct priv *priv, int fd)
305 uintptr_t pages[priv->txqs_n];
306 unsigned int pages_n = 0;
309 struct mlx5_txq_data *txq;
310 struct mlx5_txq_ctrl *txq_ctrl;
312 size_t page_size = sysconf(_SC_PAGESIZE);
314 memset(pages, 0, priv->txqs_n * sizeof(uintptr_t));
316 * As rdma-core, UARs are mapped in size of OS page size.
317 * Use aligned address to avoid duplicate mmap.
318 * Ref to libmlx5 function: mlx5_init_context()
320 for (i = 0; i != priv->txqs_n; ++i) {
321 txq = (*priv->txqs)[i];
322 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
323 uar_va = (uintptr_t)txq_ctrl->txq.bf_reg;
324 uar_va = RTE_ALIGN_FLOOR(uar_va, page_size);
326 for (j = 0; j != pages_n; ++j) {
327 if (pages[j] == uar_va) {
334 pages[pages_n++] = uar_va;
335 addr = mmap((void *)uar_va, page_size,
336 PROT_WRITE, MAP_FIXED | MAP_SHARED, fd,
337 txq_ctrl->uar_mmap_offset);
338 if (addr != (void *)uar_va) {
339 ERROR("call to mmap failed on UAR for txq %d\n", i);
347 * Check if the burst function is using eMPW.
349 * @param tx_pkt_burst
350 * Tx burst function pointer.
353 * 1 if the burst function is using eMPW, 0 otherwise.
356 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst)
358 if (tx_pkt_burst == mlx5_tx_burst_raw_vec ||
359 tx_pkt_burst == mlx5_tx_burst_vec ||
360 tx_pkt_burst == mlx5_tx_burst_empw)
366 * Create the Tx queue Verbs object.
369 * Pointer to private structure.
371 * Queue index in DPDK Rx queue array
374 * The Verbs object initialised if it can be created.
377 mlx5_priv_txq_ibv_new(struct priv *priv, uint16_t idx)
379 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
380 struct mlx5_txq_ctrl *txq_ctrl =
381 container_of(txq_data, struct mlx5_txq_ctrl, txq);
382 struct mlx5_txq_ibv tmpl;
383 struct mlx5_txq_ibv *txq_ibv;
385 struct ibv_qp_init_attr_ex init;
386 struct ibv_cq_init_attr_ex cq;
387 struct ibv_qp_attr mod;
388 struct ibv_cq_ex cq_attr;
391 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
392 struct mlx5dv_cq cq_info;
393 struct mlx5dv_obj obj;
394 const int desc = 1 << txq_data->elts_n;
395 eth_tx_burst_t tx_pkt_burst = priv_select_tx_function(priv, priv->dev);
399 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
400 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set");
403 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));
404 /* MRs will be registered in mp2mr[] later. */
405 attr.cq = (struct ibv_cq_init_attr_ex){
408 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
409 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
410 if (is_empw_burst_func(tx_pkt_burst))
411 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
412 tmpl.cq = ibv_create_cq(priv->ctx, cqe_n, NULL, NULL, 0);
413 if (tmpl.cq == NULL) {
414 ERROR("%p: CQ creation failure", (void *)txq_ctrl);
417 attr.init = (struct ibv_qp_init_attr_ex){
418 /* CQ to be associated with the send queue. */
420 /* CQ to be associated with the receive queue. */
423 /* Max number of outstanding WRs. */
425 ((priv->device_attr.orig_attr.max_qp_wr <
427 priv->device_attr.orig_attr.max_qp_wr :
430 * Max number of scatter/gather elements in a WR,
431 * must be 1 to prevent libmlx5 from trying to affect
432 * too much memory. TX gather is not impacted by the
433 * priv->device_attr.max_sge limit and will still work
438 .qp_type = IBV_QPT_RAW_PACKET,
440 * Do *NOT* enable this, completions events are managed per
445 .comp_mask = IBV_QP_INIT_ATTR_PD,
447 if (txq_data->max_inline)
448 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
449 if (txq_data->tso_en) {
450 attr.init.max_tso_header = txq_ctrl->max_tso_header;
451 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
453 tmpl.qp = ibv_create_qp_ex(priv->ctx, &attr.init);
454 if (tmpl.qp == NULL) {
455 ERROR("%p: QP creation failure", (void *)txq_ctrl);
458 attr.mod = (struct ibv_qp_attr){
459 /* Move the QP to this state. */
460 .qp_state = IBV_QPS_INIT,
461 /* Primary port number. */
462 .port_num = priv->port
464 ret = ibv_modify_qp(tmpl.qp, &attr.mod, (IBV_QP_STATE | IBV_QP_PORT));
466 ERROR("%p: QP state to IBV_QPS_INIT failed", (void *)txq_ctrl);
469 attr.mod = (struct ibv_qp_attr){
470 .qp_state = IBV_QPS_RTR
472 ret = ibv_modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
474 ERROR("%p: QP state to IBV_QPS_RTR failed", (void *)txq_ctrl);
477 attr.mod.qp_state = IBV_QPS_RTS;
478 ret = ibv_modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
480 ERROR("%p: QP state to IBV_QPS_RTS failed", (void *)txq_ctrl);
483 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,
486 ERROR("%p: cannot allocate memory", (void *)txq_ctrl);
490 obj.cq.out = &cq_info;
493 ret = mlx5dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
496 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
497 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
498 "it should be set to %u", RTE_CACHE_LINE_SIZE);
501 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
502 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
503 txq_data->wqes = qp.sq.buf;
504 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
505 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
506 txq_data->bf_reg = qp.bf.reg;
507 txq_data->cq_db = cq_info.dbrec;
509 (volatile struct mlx5_cqe (*)[])
510 (uintptr_t)cq_info.buf;
515 txq_data->wqe_ci = 0;
516 txq_data->wqe_pi = 0;
517 txq_ibv->qp = tmpl.qp;
518 txq_ibv->cq = tmpl.cq;
519 rte_atomic32_inc(&txq_ibv->refcnt);
520 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
521 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
523 ERROR("Failed to retrieve UAR info, invalid libmlx5.so version");
526 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv,
527 (void *)txq_ibv, rte_atomic32_read(&txq_ibv->refcnt));
528 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
532 claim_zero(ibv_destroy_cq(tmpl.cq));
534 claim_zero(ibv_destroy_qp(tmpl.qp));
539 * Get an Tx queue Verbs object.
542 * Pointer to private structure.
544 * Queue index in DPDK Rx queue array
547 * The Verbs object if it exists.
550 mlx5_priv_txq_ibv_get(struct priv *priv, uint16_t idx)
552 struct mlx5_txq_ctrl *txq_ctrl;
554 if (idx >= priv->txqs_n)
556 if (!(*priv->txqs)[idx])
558 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
560 rte_atomic32_inc(&txq_ctrl->ibv->refcnt);
561 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv,
562 (void *)txq_ctrl->ibv,
563 rte_atomic32_read(&txq_ctrl->ibv->refcnt));
565 return txq_ctrl->ibv;
569 * Release an Tx verbs queue object.
572 * Pointer to private structure.
574 * Verbs Tx queue object.
577 * 0 on success, errno on failure.
580 mlx5_priv_txq_ibv_release(struct priv *priv, struct mlx5_txq_ibv *txq_ibv)
584 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv,
585 (void *)txq_ibv, rte_atomic32_read(&txq_ibv->refcnt));
586 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {
587 claim_zero(ibv_destroy_qp(txq_ibv->qp));
588 claim_zero(ibv_destroy_cq(txq_ibv->cq));
589 LIST_REMOVE(txq_ibv, next);
597 * Return true if a single reference exists on the object.
600 * Pointer to private structure.
602 * Verbs Tx queue object.
605 mlx5_priv_txq_ibv_releasable(struct priv *priv, struct mlx5_txq_ibv *txq_ibv)
609 return (rte_atomic32_read(&txq_ibv->refcnt) == 1);
613 * Verify the Verbs Tx queue list is empty
616 * Pointer to private structure.
618 * @return the number of object not released.
621 mlx5_priv_txq_ibv_verify(struct priv *priv)
624 struct mlx5_txq_ibv *txq_ibv;
626 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) {
627 DEBUG("%p: Verbs Tx queue %p still referenced", (void *)priv,
635 * Set Tx queue parameters from device configuration.
638 * Pointer to Tx queue control structure.
641 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
643 struct priv *priv = txq_ctrl->priv;
644 struct mlx5_dev_config *config = &priv->config;
645 const unsigned int max_tso_inline =
646 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) /
647 RTE_CACHE_LINE_SIZE);
648 unsigned int txq_inline;
649 unsigned int txqs_inline;
650 unsigned int inline_max_packet_sz;
651 eth_tx_burst_t tx_pkt_burst = priv_select_tx_function(priv, priv->dev);
652 int is_empw_func = is_empw_burst_func(tx_pkt_burst);
653 int tso = !!(txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_TCP_TSO);
655 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ?
656 0 : config->txq_inline;
657 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ?
658 0 : config->txqs_inline;
659 inline_max_packet_sz =
660 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ?
661 0 : config->inline_max_packet_sz;
663 if (config->txq_inline == MLX5_ARG_UNSET)
664 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;
665 if (config->txqs_inline == MLX5_ARG_UNSET)
666 txqs_inline = MLX5_EMPW_MIN_TXQS;
667 if (config->inline_max_packet_sz == MLX5_ARG_UNSET)
668 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN;
669 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg;
670 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz;
672 if (txq_inline && priv->txqs_n >= txqs_inline) {
675 txq_ctrl->txq.max_inline =
676 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
677 RTE_CACHE_LINE_SIZE);
679 /* To minimize the size of data set, avoid requesting
682 txq_ctrl->max_inline_data =
683 ((RTE_MIN(txq_inline,
684 inline_max_packet_sz) +
685 (RTE_CACHE_LINE_SIZE - 1)) /
686 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
688 int inline_diff = txq_ctrl->txq.max_inline -
692 * Adjust inline value as Verbs aggregates
693 * tso_inline and txq_inline fields.
695 txq_ctrl->max_inline_data = inline_diff > 0 ?
697 RTE_CACHE_LINE_SIZE :
700 txq_ctrl->max_inline_data =
701 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE;
704 * Check if the inline size is too large in a way which
705 * can make the WQE DS to overflow.
706 * Considering in calculation:
711 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE);
712 if (ds_cnt > MLX5_DSEG_MAX) {
713 unsigned int max_inline = (MLX5_DSEG_MAX - 2) *
716 max_inline = max_inline - (max_inline %
717 RTE_CACHE_LINE_SIZE);
718 WARN("txq inline is too large (%d) setting it to "
719 "the maximum possible: %d\n",
720 txq_inline, max_inline);
721 txq_ctrl->txq.max_inline = max_inline /
726 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE;
727 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline,
729 txq_ctrl->txq.tso_en = 1;
731 txq_ctrl->txq.tunnel_en = config->tunnel_en;
735 * Create a DPDK Tx queue.
738 * Pointer to private structure.
742 * Number of descriptors to configure in queue.
744 * NUMA socket on which memory must be allocated.
746 * Thresholds parameters.
749 * A DPDK queue object on success.
751 struct mlx5_txq_ctrl*
752 mlx5_priv_txq_new(struct priv *priv, uint16_t idx, uint16_t desc,
754 const struct rte_eth_txconf *conf)
756 struct mlx5_txq_ctrl *tmpl;
758 tmpl = rte_calloc_socket("TXQ", 1,
760 desc * sizeof(struct rte_mbuf *),
764 assert(desc > MLX5_TX_COMP_THRESH);
765 tmpl->txq.offloads = conf->offloads;
767 tmpl->socket = socket;
768 tmpl->txq.elts_n = log2above(desc);
769 txq_set_params(tmpl);
770 /* MRs will be registered in mp2mr[] later. */
771 DEBUG("priv->device_attr.max_qp_wr is %d",
772 priv->device_attr.orig_attr.max_qp_wr);
773 DEBUG("priv->device_attr.max_sge is %d",
774 priv->device_attr.orig_attr.max_sge);
776 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1);
777 tmpl->txq.stats.idx = idx;
778 rte_atomic32_inc(&tmpl->refcnt);
779 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv,
780 (void *)tmpl, rte_atomic32_read(&tmpl->refcnt));
781 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
789 * Pointer to private structure.
794 * A pointer to the queue if it exists.
796 struct mlx5_txq_ctrl*
797 mlx5_priv_txq_get(struct priv *priv, uint16_t idx)
799 struct mlx5_txq_ctrl *ctrl = NULL;
801 if ((*priv->txqs)[idx]) {
802 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
806 mlx5_priv_txq_ibv_get(priv, idx);
807 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
808 struct mlx5_mr *mr = NULL;
811 if (ctrl->txq.mp2mr[i]) {
812 mr = priv_mr_get(priv, ctrl->txq.mp2mr[i]->mp);
816 rte_atomic32_inc(&ctrl->refcnt);
817 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv,
818 (void *)ctrl, rte_atomic32_read(&ctrl->refcnt));
824 * Release a Tx queue.
827 * Pointer to private structure.
832 * 0 on success, errno on failure.
835 mlx5_priv_txq_release(struct priv *priv, uint16_t idx)
838 struct mlx5_txq_ctrl *txq;
840 if (!(*priv->txqs)[idx])
842 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
843 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv,
844 (void *)txq, rte_atomic32_read(&txq->refcnt));
848 ret = mlx5_priv_txq_ibv_release(priv, txq->ibv);
852 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
853 if (txq->txq.mp2mr[i]) {
854 priv_mr_release(priv, txq->txq.mp2mr[i]);
855 txq->txq.mp2mr[i] = NULL;
858 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
860 LIST_REMOVE(txq, next);
862 (*priv->txqs)[idx] = NULL;
869 * Verify if the queue can be released.
872 * Pointer to private structure.
877 * 1 if the queue can be released.
880 mlx5_priv_txq_releasable(struct priv *priv, uint16_t idx)
882 struct mlx5_txq_ctrl *txq;
884 if (!(*priv->txqs)[idx])
886 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
887 return (rte_atomic32_read(&txq->refcnt) == 1);
891 * Verify the Tx Queue list is empty
894 * Pointer to private structure.
896 * @return the number of object not released.
899 mlx5_priv_txq_verify(struct priv *priv)
901 struct mlx5_txq_ctrl *txq;
904 LIST_FOREACH(txq, &priv->txqsctrl, next) {
905 DEBUG("%p: Tx Queue %p still referenced", (void *)priv,