4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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43 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
45 #pragma GCC diagnostic ignored "-Wpedantic"
47 #include <infiniband/verbs.h>
49 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_malloc.h>
54 #include <rte_ethdev.h>
55 #include <rte_common.h>
57 #include "mlx5_utils.h"
58 #include "mlx5_defs.h"
60 #include "mlx5_rxtx.h"
61 #include "mlx5_autoconf.h"
64 * Allocate TX queue elements.
67 * Pointer to TX queue structure.
70 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
72 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
75 for (i = 0; (i != elts_n); ++i)
76 (*txq_ctrl->txq.elts)[i] = NULL;
77 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
78 txq_ctrl->txq.elts_head = 0;
79 txq_ctrl->txq.elts_tail = 0;
80 txq_ctrl->txq.elts_comp = 0;
84 * Free TX queue elements.
87 * Pointer to TX queue structure.
90 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
92 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
93 const uint16_t elts_m = elts_n - 1;
94 uint16_t elts_head = txq_ctrl->txq.elts_head;
95 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
96 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
98 DEBUG("%p: freeing WRs", (void *)txq_ctrl);
99 txq_ctrl->txq.elts_head = 0;
100 txq_ctrl->txq.elts_tail = 0;
101 txq_ctrl->txq.elts_comp = 0;
103 while (elts_tail != elts_head) {
104 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
107 rte_pktmbuf_free_seg(elt);
110 memset(&(*elts)[elts_tail & elts_m],
112 sizeof((*elts)[elts_tail & elts_m]));
119 * DPDK callback to configure a TX queue.
122 * Pointer to Ethernet device structure.
126 * Number of descriptors to configure in queue.
128 * NUMA socket on which memory must be allocated.
130 * Thresholds parameters.
133 * 0 on success, negative errno value on failure.
136 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
137 unsigned int socket, const struct rte_eth_txconf *conf)
139 struct priv *priv = dev->data->dev_private;
140 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
141 struct mlx5_txq_ctrl *txq_ctrl =
142 container_of(txq, struct mlx5_txq_ctrl, txq);
146 if (desc <= MLX5_TX_COMP_THRESH) {
147 WARN("%p: number of descriptors requested for TX queue %u"
148 " must be higher than MLX5_TX_COMP_THRESH, using"
150 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
151 desc = MLX5_TX_COMP_THRESH + 1;
153 if (!rte_is_power_of_2(desc)) {
154 desc = 1 << log2above(desc);
155 WARN("%p: increased number of descriptors in TX queue %u"
156 " to the next power of two (%d)",
157 (void *)dev, idx, desc);
159 DEBUG("%p: configuring queue %u for %u descriptors",
160 (void *)dev, idx, desc);
161 if (idx >= priv->txqs_n) {
162 ERROR("%p: queue index out of range (%u >= %u)",
163 (void *)dev, idx, priv->txqs_n);
167 if (!mlx5_priv_txq_releasable(priv, idx)) {
169 ERROR("%p: unable to release queue index %u",
173 mlx5_priv_txq_release(priv, idx);
174 txq_ctrl = mlx5_priv_txq_new(priv, idx, desc, socket, conf);
176 ERROR("%p: unable to allocate queue index %u",
181 DEBUG("%p: adding TX queue %p to list",
182 (void *)dev, (void *)txq_ctrl);
183 (*priv->txqs)[idx] = &txq_ctrl->txq;
190 * DPDK callback to release a TX queue.
193 * Generic TX queue pointer.
196 mlx5_tx_queue_release(void *dpdk_txq)
198 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
199 struct mlx5_txq_ctrl *txq_ctrl;
205 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
206 priv = txq_ctrl->priv;
208 for (i = 0; (i != priv->txqs_n); ++i)
209 if ((*priv->txqs)[i] == txq) {
210 DEBUG("%p: removing TX queue %p from list",
211 (void *)priv->dev, (void *)txq_ctrl);
212 mlx5_priv_txq_release(priv, i);
220 * Map locally UAR used in Tx queues for BlueFlame doorbell.
223 * Pointer to private structure.
225 * Verbs file descriptor to map UAR pages.
228 * 0 on success, errno value on failure.
231 priv_tx_uar_remap(struct priv *priv, int fd)
234 uintptr_t pages[priv->txqs_n];
235 unsigned int pages_n = 0;
238 struct mlx5_txq_data *txq;
239 struct mlx5_txq_ctrl *txq_ctrl;
241 size_t page_size = sysconf(_SC_PAGESIZE);
243 memset(pages, 0, priv->txqs_n * sizeof(uintptr_t));
245 * As rdma-core, UARs are mapped in size of OS page size.
246 * Use aligned address to avoid duplicate mmap.
247 * Ref to libmlx5 function: mlx5_init_context()
249 for (i = 0; i != priv->txqs_n; ++i) {
250 txq = (*priv->txqs)[i];
251 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
252 uar_va = (uintptr_t)txq_ctrl->txq.bf_reg;
253 uar_va = RTE_ALIGN_FLOOR(uar_va, page_size);
255 for (j = 0; j != pages_n; ++j) {
256 if (pages[j] == uar_va) {
263 pages[pages_n++] = uar_va;
264 addr = mmap((void *)uar_va, page_size,
265 PROT_WRITE, MAP_FIXED | MAP_SHARED, fd,
266 txq_ctrl->uar_mmap_offset);
267 if (addr != (void *)uar_va) {
268 ERROR("call to mmap failed on UAR for txq %d\n", i);
276 * Check if the burst function is using eMPW.
278 * @param tx_pkt_burst
279 * Tx burst function pointer.
282 * 1 if the burst function is using eMPW, 0 otherwise.
285 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst)
287 if (tx_pkt_burst == mlx5_tx_burst_raw_vec ||
288 tx_pkt_burst == mlx5_tx_burst_vec ||
289 tx_pkt_burst == mlx5_tx_burst_empw)
295 * Create the Tx queue Verbs object.
298 * Pointer to private structure.
300 * Queue index in DPDK Rx queue array
303 * The Verbs object initialised if it can be created.
306 mlx5_priv_txq_ibv_new(struct priv *priv, uint16_t idx)
308 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
309 struct mlx5_txq_ctrl *txq_ctrl =
310 container_of(txq_data, struct mlx5_txq_ctrl, txq);
311 struct mlx5_txq_ibv tmpl;
312 struct mlx5_txq_ibv *txq_ibv;
314 struct ibv_qp_init_attr_ex init;
315 struct ibv_cq_init_attr_ex cq;
316 struct ibv_qp_attr mod;
317 struct ibv_cq_ex cq_attr;
320 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
321 struct mlx5dv_cq cq_info;
322 struct mlx5dv_obj obj;
323 const int desc = 1 << txq_data->elts_n;
324 eth_tx_burst_t tx_pkt_burst = priv_select_tx_function(priv, priv->dev);
328 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
329 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set");
332 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));
333 /* MRs will be registered in mp2mr[] later. */
334 attr.cq = (struct ibv_cq_init_attr_ex){
337 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
338 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
339 if (is_empw_burst_func(tx_pkt_burst))
340 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
341 tmpl.cq = ibv_create_cq(priv->ctx, cqe_n, NULL, NULL, 0);
342 if (tmpl.cq == NULL) {
343 ERROR("%p: CQ creation failure", (void *)txq_ctrl);
346 attr.init = (struct ibv_qp_init_attr_ex){
347 /* CQ to be associated with the send queue. */
349 /* CQ to be associated with the receive queue. */
352 /* Max number of outstanding WRs. */
354 ((priv->device_attr.orig_attr.max_qp_wr <
356 priv->device_attr.orig_attr.max_qp_wr :
359 * Max number of scatter/gather elements in a WR,
360 * must be 1 to prevent libmlx5 from trying to affect
361 * too much memory. TX gather is not impacted by the
362 * priv->device_attr.max_sge limit and will still work
367 .qp_type = IBV_QPT_RAW_PACKET,
369 * Do *NOT* enable this, completions events are managed per
374 .comp_mask = IBV_QP_INIT_ATTR_PD,
376 if (txq_data->max_inline)
377 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
378 if (txq_data->tso_en) {
379 attr.init.max_tso_header = txq_ctrl->max_tso_header;
380 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
382 tmpl.qp = ibv_create_qp_ex(priv->ctx, &attr.init);
383 if (tmpl.qp == NULL) {
384 ERROR("%p: QP creation failure", (void *)txq_ctrl);
387 attr.mod = (struct ibv_qp_attr){
388 /* Move the QP to this state. */
389 .qp_state = IBV_QPS_INIT,
390 /* Primary port number. */
391 .port_num = priv->port
393 ret = ibv_modify_qp(tmpl.qp, &attr.mod, (IBV_QP_STATE | IBV_QP_PORT));
395 ERROR("%p: QP state to IBV_QPS_INIT failed", (void *)txq_ctrl);
398 attr.mod = (struct ibv_qp_attr){
399 .qp_state = IBV_QPS_RTR
401 ret = ibv_modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
403 ERROR("%p: QP state to IBV_QPS_RTR failed", (void *)txq_ctrl);
406 attr.mod.qp_state = IBV_QPS_RTS;
407 ret = ibv_modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
409 ERROR("%p: QP state to IBV_QPS_RTS failed", (void *)txq_ctrl);
412 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,
415 ERROR("%p: cannot allocate memory", (void *)txq_ctrl);
419 obj.cq.out = &cq_info;
422 ret = mlx5dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
425 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
426 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
427 "it should be set to %u", RTE_CACHE_LINE_SIZE);
430 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
431 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
432 txq_data->wqes = qp.sq.buf;
433 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
434 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
435 txq_data->bf_reg = qp.bf.reg;
436 txq_data->cq_db = cq_info.dbrec;
438 (volatile struct mlx5_cqe (*)[])
439 (uintptr_t)cq_info.buf;
444 txq_data->wqe_ci = 0;
445 txq_data->wqe_pi = 0;
446 txq_ibv->qp = tmpl.qp;
447 txq_ibv->cq = tmpl.cq;
448 rte_atomic32_inc(&txq_ibv->refcnt);
449 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
450 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
452 ERROR("Failed to retrieve UAR info, invalid libmlx5.so version");
455 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv,
456 (void *)txq_ibv, rte_atomic32_read(&txq_ibv->refcnt));
457 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
461 claim_zero(ibv_destroy_cq(tmpl.cq));
463 claim_zero(ibv_destroy_qp(tmpl.qp));
468 * Get an Tx queue Verbs object.
471 * Pointer to private structure.
473 * Queue index in DPDK Rx queue array
476 * The Verbs object if it exists.
479 mlx5_priv_txq_ibv_get(struct priv *priv, uint16_t idx)
481 struct mlx5_txq_ctrl *txq_ctrl;
483 if (idx >= priv->txqs_n)
485 if (!(*priv->txqs)[idx])
487 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
489 rte_atomic32_inc(&txq_ctrl->ibv->refcnt);
490 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv,
491 (void *)txq_ctrl->ibv,
492 rte_atomic32_read(&txq_ctrl->ibv->refcnt));
494 return txq_ctrl->ibv;
498 * Release an Tx verbs queue object.
501 * Pointer to private structure.
503 * Verbs Tx queue object.
506 * 0 on success, errno on failure.
509 mlx5_priv_txq_ibv_release(struct priv *priv, struct mlx5_txq_ibv *txq_ibv)
513 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv,
514 (void *)txq_ibv, rte_atomic32_read(&txq_ibv->refcnt));
515 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {
516 claim_zero(ibv_destroy_qp(txq_ibv->qp));
517 claim_zero(ibv_destroy_cq(txq_ibv->cq));
518 LIST_REMOVE(txq_ibv, next);
526 * Return true if a single reference exists on the object.
529 * Pointer to private structure.
531 * Verbs Tx queue object.
534 mlx5_priv_txq_ibv_releasable(struct priv *priv, struct mlx5_txq_ibv *txq_ibv)
538 return (rte_atomic32_read(&txq_ibv->refcnt) == 1);
542 * Verify the Verbs Tx queue list is empty
545 * Pointer to private structure.
547 * @return the number of object not released.
550 mlx5_priv_txq_ibv_verify(struct priv *priv)
553 struct mlx5_txq_ibv *txq_ibv;
555 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) {
556 DEBUG("%p: Verbs Tx queue %p still referenced", (void *)priv,
564 * Set Tx queue parameters from device configuration.
567 * Pointer to Tx queue control structure.
570 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
572 struct priv *priv = txq_ctrl->priv;
573 struct mlx5_dev_config *config = &priv->config;
574 const unsigned int max_tso_inline =
575 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) /
576 RTE_CACHE_LINE_SIZE);
577 unsigned int txq_inline;
578 unsigned int txqs_inline;
579 unsigned int inline_max_packet_sz;
580 eth_tx_burst_t tx_pkt_burst = priv_select_tx_function(priv, priv->dev);
581 int is_empw_func = is_empw_burst_func(tx_pkt_burst);
583 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ?
584 0 : config->txq_inline;
585 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ?
586 0 : config->txqs_inline;
587 inline_max_packet_sz =
588 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ?
589 0 : config->inline_max_packet_sz;
591 if (config->txq_inline == MLX5_ARG_UNSET)
592 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;
593 if (config->txqs_inline == MLX5_ARG_UNSET)
594 txqs_inline = MLX5_EMPW_MIN_TXQS;
595 if (config->inline_max_packet_sz == MLX5_ARG_UNSET)
596 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN;
597 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg;
598 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz;
600 if (txq_inline && priv->txqs_n >= txqs_inline) {
603 txq_ctrl->txq.max_inline =
604 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
605 RTE_CACHE_LINE_SIZE);
606 /* TSO and MPS can't be enabled concurrently. */
607 assert(!config->tso || !config->mps);
609 /* To minimize the size of data set, avoid requesting
612 txq_ctrl->max_inline_data =
613 ((RTE_MIN(txq_inline,
614 inline_max_packet_sz) +
615 (RTE_CACHE_LINE_SIZE - 1)) /
616 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
617 } else if (config->tso) {
618 int inline_diff = txq_ctrl->txq.max_inline -
622 * Adjust inline value as Verbs aggregates
623 * tso_inline and txq_inline fields.
625 txq_ctrl->max_inline_data = inline_diff > 0 ?
627 RTE_CACHE_LINE_SIZE :
630 txq_ctrl->max_inline_data =
631 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE;
634 * Check if the inline size is too large in a way which
635 * can make the WQE DS to overflow.
636 * Considering in calculation:
641 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE);
642 if (ds_cnt > MLX5_DSEG_MAX) {
643 unsigned int max_inline = (MLX5_DSEG_MAX - 2) *
646 max_inline = max_inline - (max_inline %
647 RTE_CACHE_LINE_SIZE);
648 WARN("txq inline is too large (%d) setting it to "
649 "the maximum possible: %d\n",
650 txq_inline, max_inline);
651 txq_ctrl->txq.max_inline = max_inline /
656 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE;
657 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline,
659 txq_ctrl->txq.tso_en = 1;
661 txq_ctrl->txq.tunnel_en = config->tunnel_en;
665 * Create a DPDK Tx queue.
668 * Pointer to private structure.
672 * Number of descriptors to configure in queue.
674 * NUMA socket on which memory must be allocated.
676 * Thresholds parameters.
679 * A DPDK queue object on success.
681 struct mlx5_txq_ctrl*
682 mlx5_priv_txq_new(struct priv *priv, uint16_t idx, uint16_t desc,
684 const struct rte_eth_txconf *conf)
686 struct mlx5_txq_ctrl *tmpl;
688 tmpl = rte_calloc_socket("TXQ", 1,
690 desc * sizeof(struct rte_mbuf *),
694 assert(desc > MLX5_TX_COMP_THRESH);
695 tmpl->txq.flags = conf->txq_flags;
697 tmpl->socket = socket;
698 tmpl->txq.elts_n = log2above(desc);
699 txq_set_params(tmpl);
700 /* MRs will be registered in mp2mr[] later. */
701 DEBUG("priv->device_attr.max_qp_wr is %d",
702 priv->device_attr.orig_attr.max_qp_wr);
703 DEBUG("priv->device_attr.max_sge is %d",
704 priv->device_attr.orig_attr.max_sge);
706 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1);
707 tmpl->txq.stats.idx = idx;
708 rte_atomic32_inc(&tmpl->refcnt);
709 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv,
710 (void *)tmpl, rte_atomic32_read(&tmpl->refcnt));
711 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
719 * Pointer to private structure.
724 * A pointer to the queue if it exists.
726 struct mlx5_txq_ctrl*
727 mlx5_priv_txq_get(struct priv *priv, uint16_t idx)
729 struct mlx5_txq_ctrl *ctrl = NULL;
731 if ((*priv->txqs)[idx]) {
732 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
736 mlx5_priv_txq_ibv_get(priv, idx);
737 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
738 struct mlx5_mr *mr = NULL;
741 if (ctrl->txq.mp2mr[i]) {
742 mr = priv_mr_get(priv, ctrl->txq.mp2mr[i]->mp);
746 rte_atomic32_inc(&ctrl->refcnt);
747 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv,
748 (void *)ctrl, rte_atomic32_read(&ctrl->refcnt));
754 * Release a Tx queue.
757 * Pointer to private structure.
762 * 0 on success, errno on failure.
765 mlx5_priv_txq_release(struct priv *priv, uint16_t idx)
768 struct mlx5_txq_ctrl *txq;
770 if (!(*priv->txqs)[idx])
772 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
773 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv,
774 (void *)txq, rte_atomic32_read(&txq->refcnt));
778 ret = mlx5_priv_txq_ibv_release(priv, txq->ibv);
782 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
783 if (txq->txq.mp2mr[i]) {
784 priv_mr_release(priv, txq->txq.mp2mr[i]);
785 txq->txq.mp2mr[i] = NULL;
788 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
790 LIST_REMOVE(txq, next);
792 (*priv->txqs)[idx] = NULL;
799 * Verify if the queue can be released.
802 * Pointer to private structure.
807 * 1 if the queue can be released.
810 mlx5_priv_txq_releasable(struct priv *priv, uint16_t idx)
812 struct mlx5_txq_ctrl *txq;
814 if (!(*priv->txqs)[idx])
816 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
817 return (rte_atomic32_read(&txq->refcnt) == 1);
821 * Verify the Tx Queue list is empty
824 * Pointer to private structure.
826 * @return the number of object not released.
829 mlx5_priv_txq_verify(struct priv *priv)
831 struct mlx5_txq_ctrl *txq;
834 LIST_FOREACH(txq, &priv->txqsctrl, next) {
835 DEBUG("%p: Tx Queue %p still referenced", (void *)priv,