4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-pedantic"
45 #include <infiniband/verbs.h>
47 #pragma GCC diagnostic error "-pedantic"
50 /* DPDK headers don't like -pedantic. */
52 #pragma GCC diagnostic ignored "-pedantic"
55 #include <rte_malloc.h>
56 #include <rte_ethdev.h>
57 #include <rte_common.h>
59 #pragma GCC diagnostic error "-pedantic"
62 #include "mlx5_utils.h"
63 #include "mlx5_defs.h"
65 #include "mlx5_rxtx.h"
66 #include "mlx5_autoconf.h"
67 #include "mlx5_defs.h"
70 * Allocate TX queue elements.
73 * Pointer to TX queue structure.
75 * Number of elements to allocate.
78 txq_alloc_elts(struct txq_ctrl *txq_ctrl, unsigned int elts_n)
82 for (i = 0; (i != elts_n); ++i)
83 (*txq_ctrl->txq.elts)[i] = NULL;
84 for (i = 0; (i != txq_ctrl->txq.wqe_n); ++i) {
85 volatile union mlx5_wqe *wqe = &(*txq_ctrl->txq.wqes)[i];
87 memset((void *)(uintptr_t)wqe, 0x0, sizeof(*wqe));
89 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
90 txq_ctrl->txq.elts_head = 0;
91 txq_ctrl->txq.elts_tail = 0;
92 txq_ctrl->txq.elts_comp = 0;
96 * Free TX queue elements.
99 * Pointer to TX queue structure.
102 txq_free_elts(struct txq_ctrl *txq_ctrl)
104 unsigned int elts_n = txq_ctrl->txq.elts_n;
105 unsigned int elts_head = txq_ctrl->txq.elts_head;
106 unsigned int elts_tail = txq_ctrl->txq.elts_tail;
107 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
109 DEBUG("%p: freeing WRs", (void *)txq_ctrl);
110 txq_ctrl->txq.elts_head = 0;
111 txq_ctrl->txq.elts_tail = 0;
112 txq_ctrl->txq.elts_comp = 0;
114 while (elts_tail != elts_head) {
115 struct rte_mbuf *elt = (*elts)[elts_tail];
118 rte_pktmbuf_free(elt);
121 memset(&(*elts)[elts_tail],
123 sizeof((*elts)[elts_tail]));
125 if (++elts_tail == elts_n)
131 * Clean up a TX queue.
133 * Destroy objects, free allocated memory and reset the structure for reuse.
136 * Pointer to TX queue structure.
139 txq_cleanup(struct txq_ctrl *txq_ctrl)
141 struct ibv_exp_release_intf_params params;
144 DEBUG("cleaning up %p", (void *)txq_ctrl);
145 txq_free_elts(txq_ctrl);
146 if (txq_ctrl->if_qp != NULL) {
147 assert(txq_ctrl->priv != NULL);
148 assert(txq_ctrl->priv->ctx != NULL);
149 assert(txq_ctrl->qp != NULL);
150 params = (struct ibv_exp_release_intf_params){
153 claim_zero(ibv_exp_release_intf(txq_ctrl->priv->ctx,
157 if (txq_ctrl->if_cq != NULL) {
158 assert(txq_ctrl->priv != NULL);
159 assert(txq_ctrl->priv->ctx != NULL);
160 assert(txq_ctrl->cq != NULL);
161 params = (struct ibv_exp_release_intf_params){
164 claim_zero(ibv_exp_release_intf(txq_ctrl->priv->ctx,
168 if (txq_ctrl->qp != NULL)
169 claim_zero(ibv_destroy_qp(txq_ctrl->qp));
170 if (txq_ctrl->cq != NULL)
171 claim_zero(ibv_destroy_cq(txq_ctrl->cq));
172 if (txq_ctrl->rd != NULL) {
173 struct ibv_exp_destroy_res_domain_attr attr = {
177 assert(txq_ctrl->priv != NULL);
178 assert(txq_ctrl->priv->ctx != NULL);
179 claim_zero(ibv_exp_destroy_res_domain(txq_ctrl->priv->ctx,
183 for (i = 0; (i != RTE_DIM(txq_ctrl->txq.mp2mr)); ++i) {
184 if (txq_ctrl->txq.mp2mr[i].mp == NULL)
186 assert(txq_ctrl->txq.mp2mr[i].mr != NULL);
187 claim_zero(ibv_dereg_mr(txq_ctrl->txq.mp2mr[i].mr));
189 memset(txq_ctrl, 0, sizeof(*txq_ctrl));
193 * Initialize TX queue.
196 * Pointer to TX queue control template.
198 * Pointer to TX queue control.
201 * 0 on success, errno value on failure.
204 txq_setup(struct txq_ctrl *tmpl, struct txq_ctrl *txq_ctrl)
206 struct mlx5_qp *qp = to_mqp(tmpl->qp);
207 struct ibv_cq *ibcq = tmpl->cq;
208 struct mlx5_cq *cq = to_mxxx(cq, cq);
210 if (cq->cqe_sz != RTE_CACHE_LINE_SIZE) {
211 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
212 "it should be set to %u", RTE_CACHE_LINE_SIZE);
215 tmpl->txq.cqe_n = ibcq->cqe + 1;
216 tmpl->txq.qp_num_8s = qp->ctrl_seg.qp_num << 8;
218 (volatile union mlx5_wqe (*)[])
219 (uintptr_t)qp->gen_data.sqstart;
220 tmpl->txq.wqe_n = qp->sq.wqe_cnt;
221 tmpl->txq.qp_db = &qp->gen_data.db[MLX5_SND_DBR];
222 tmpl->txq.bf_reg = qp->gen_data.bf->reg;
223 tmpl->txq.bf_offset = qp->gen_data.bf->offset;
224 tmpl->txq.bf_buf_size = qp->gen_data.bf->buf_size;
225 tmpl->txq.cq_db = cq->dbrec;
227 (volatile struct mlx5_cqe (*)[])
228 (uintptr_t)cq->active_buf->buf;
230 (struct rte_mbuf *(*)[tmpl->txq.elts_n])
231 ((uintptr_t)txq_ctrl + sizeof(*txq_ctrl));
236 * Configure a TX queue.
239 * Pointer to Ethernet device structure.
241 * Pointer to TX queue structure.
243 * Number of descriptors to configure in queue.
245 * NUMA socket on which memory must be allocated.
247 * Thresholds parameters.
250 * 0 on success, errno value on failure.
253 txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,
254 uint16_t desc, unsigned int socket,
255 const struct rte_eth_txconf *conf)
257 struct priv *priv = mlx5_get_priv(dev);
258 struct txq_ctrl tmpl = {
263 struct ibv_exp_query_intf_params params;
264 struct ibv_exp_qp_init_attr init;
265 struct ibv_exp_res_domain_init_attr rd;
266 struct ibv_exp_cq_init_attr cq;
267 struct ibv_exp_qp_attr mod;
268 struct ibv_exp_cq_attr cq_attr;
270 enum ibv_exp_query_intf_status status;
273 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
275 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set");
278 (void)conf; /* Thresholds configuration (ignored). */
279 assert(desc > MLX5_TX_COMP_THRESH);
280 tmpl.txq.elts_n = desc;
281 /* MRs will be registered in mp2mr[] later. */
282 attr.rd = (struct ibv_exp_res_domain_init_attr){
283 .comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL |
284 IBV_EXP_RES_DOMAIN_MSG_MODEL),
285 .thread_model = IBV_EXP_THREAD_SINGLE,
286 .msg_model = IBV_EXP_MSG_HIGH_BW,
288 tmpl.rd = ibv_exp_create_res_domain(priv->ctx, &attr.rd);
289 if (tmpl.rd == NULL) {
291 ERROR("%p: RD creation failure: %s",
292 (void *)dev, strerror(ret));
295 attr.cq = (struct ibv_exp_cq_init_attr){
296 .comp_mask = IBV_EXP_CQ_INIT_ATTR_RES_DOMAIN,
297 .res_domain = tmpl.rd,
299 tmpl.cq = ibv_exp_create_cq(priv->ctx,
300 (((desc / MLX5_TX_COMP_THRESH) - 1) ?
301 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1),
302 NULL, NULL, 0, &attr.cq);
303 if (tmpl.cq == NULL) {
305 ERROR("%p: CQ creation failure: %s",
306 (void *)dev, strerror(ret));
309 DEBUG("priv->device_attr.max_qp_wr is %d",
310 priv->device_attr.max_qp_wr);
311 DEBUG("priv->device_attr.max_sge is %d",
312 priv->device_attr.max_sge);
313 attr.init = (struct ibv_exp_qp_init_attr){
314 /* CQ to be associated with the send queue. */
316 /* CQ to be associated with the receive queue. */
319 /* Max number of outstanding WRs. */
320 .max_send_wr = ((priv->device_attr.max_qp_wr < desc) ?
321 priv->device_attr.max_qp_wr :
323 /* Max number of scatter/gather elements in a WR. */
326 .qp_type = IBV_QPT_RAW_PACKET,
327 /* Do *NOT* enable this, completions events are managed per
331 .res_domain = tmpl.rd,
332 .comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |
333 IBV_EXP_QP_INIT_ATTR_RES_DOMAIN),
335 if (priv->txq_inline && priv->txqs_n >= priv->txqs_inline) {
336 tmpl.txq.max_inline = priv->txq_inline;
337 attr.init.cap.max_inline_data = tmpl.txq.max_inline;
339 tmpl.qp = ibv_exp_create_qp(priv->ctx, &attr.init);
340 if (tmpl.qp == NULL) {
341 ret = (errno ? errno : EINVAL);
342 ERROR("%p: QP creation failure: %s",
343 (void *)dev, strerror(ret));
346 attr.mod = (struct ibv_exp_qp_attr){
347 /* Move the QP to this state. */
348 .qp_state = IBV_QPS_INIT,
349 /* Primary port number. */
350 .port_num = priv->port
352 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod,
353 (IBV_EXP_QP_STATE | IBV_EXP_QP_PORT));
355 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
356 (void *)dev, strerror(ret));
359 ret = txq_setup(&tmpl, txq_ctrl);
361 ERROR("%p: cannot initialize TX queue structure: %s",
362 (void *)dev, strerror(ret));
365 txq_alloc_elts(&tmpl, desc);
366 attr.mod = (struct ibv_exp_qp_attr){
367 .qp_state = IBV_QPS_RTR
369 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
371 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
372 (void *)dev, strerror(ret));
375 attr.mod.qp_state = IBV_QPS_RTS;
376 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
378 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
379 (void *)dev, strerror(ret));
382 attr.params = (struct ibv_exp_query_intf_params){
383 .intf_scope = IBV_EXP_INTF_GLOBAL,
384 .intf = IBV_EXP_INTF_CQ,
387 tmpl.if_cq = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
388 if (tmpl.if_cq == NULL) {
390 ERROR("%p: CQ interface family query failed with status %d",
391 (void *)dev, status);
394 attr.params = (struct ibv_exp_query_intf_params){
395 .intf_scope = IBV_EXP_INTF_GLOBAL,
396 .intf = IBV_EXP_INTF_QP_BURST,
399 /* Enable multi-packet send if supported. */
401 ((priv->mps && !priv->sriov) ?
402 IBV_EXP_QP_BURST_CREATE_ENABLE_MULTI_PACKET_SEND_WR :
405 tmpl.if_qp = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
406 if (tmpl.if_qp == NULL) {
408 ERROR("%p: QP interface family query failed with status %d",
409 (void *)dev, status);
412 /* Clean up txq in case we're reinitializing it. */
413 DEBUG("%p: cleaning-up old txq just in case", (void *)txq_ctrl);
414 txq_cleanup(txq_ctrl);
416 DEBUG("%p: txq updated with %p", (void *)txq_ctrl, (void *)&tmpl);
417 /* Pre-register known mempools. */
418 rte_mempool_walk(txq_mp2mr_iter, txq_ctrl);
428 * DPDK callback to configure a TX queue.
431 * Pointer to Ethernet device structure.
435 * Number of descriptors to configure in queue.
437 * NUMA socket on which memory must be allocated.
439 * Thresholds parameters.
442 * 0 on success, negative errno value on failure.
445 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
446 unsigned int socket, const struct rte_eth_txconf *conf)
448 struct priv *priv = dev->data->dev_private;
449 struct txq *txq = (*priv->txqs)[idx];
450 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
453 if (mlx5_is_secondary())
454 return -E_RTE_SECONDARY;
457 if (desc <= MLX5_TX_COMP_THRESH) {
458 WARN("%p: number of descriptors requested for TX queue %u"
459 " must be higher than MLX5_TX_COMP_THRESH, using"
461 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
462 desc = MLX5_TX_COMP_THRESH + 1;
464 if (!rte_is_power_of_2(desc)) {
465 desc = 1 << log2above(desc);
466 WARN("%p: increased number of descriptors in TX queue %u"
467 " to the next power of two (%d)",
468 (void *)dev, idx, desc);
470 DEBUG("%p: configuring queue %u for %u descriptors",
471 (void *)dev, idx, desc);
472 if (idx >= priv->txqs_n) {
473 ERROR("%p: queue index out of range (%u >= %u)",
474 (void *)dev, idx, priv->txqs_n);
479 DEBUG("%p: reusing already allocated queue index %u (%p)",
480 (void *)dev, idx, (void *)txq);
485 (*priv->txqs)[idx] = NULL;
486 txq_cleanup(txq_ctrl);
489 rte_calloc_socket("TXQ", 1,
491 desc * sizeof(struct rte_mbuf *),
493 if (txq_ctrl == NULL) {
494 ERROR("%p: unable to allocate queue index %u",
500 ret = txq_ctrl_setup(dev, txq_ctrl, desc, socket, conf);
504 txq_ctrl->txq.stats.idx = idx;
505 DEBUG("%p: adding TX queue %p to list",
506 (void *)dev, (void *)txq_ctrl);
507 (*priv->txqs)[idx] = &txq_ctrl->txq;
508 /* Update send callback. */
509 priv_select_tx_function(priv);
516 * DPDK callback to release a TX queue.
519 * Generic TX queue pointer.
522 mlx5_tx_queue_release(void *dpdk_txq)
524 struct txq *txq = (struct txq *)dpdk_txq;
525 struct txq_ctrl *txq_ctrl;
529 if (mlx5_is_secondary())
534 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
535 priv = txq_ctrl->priv;
537 for (i = 0; (i != priv->txqs_n); ++i)
538 if ((*priv->txqs)[i] == txq) {
539 DEBUG("%p: removing TX queue %p from list",
540 (void *)priv->dev, (void *)txq_ctrl);
541 (*priv->txqs)[i] = NULL;
544 txq_cleanup(txq_ctrl);
550 * DPDK callback for TX in secondary processes.
552 * This function configures all queues from primary process information
553 * if necessary before reverting to the normal TX burst callback.
556 * Generic pointer to TX queue structure.
558 * Packets to transmit.
560 * Number of packets in array.
563 * Number of packets successfully transmitted (<= pkts_n).
566 mlx5_tx_burst_secondary_setup(void *dpdk_txq, struct rte_mbuf **pkts,
569 struct txq *txq = dpdk_txq;
570 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
571 struct priv *priv = mlx5_secondary_data_setup(txq_ctrl->priv);
572 struct priv *primary_priv;
578 mlx5_secondary_data[priv->dev->data->port_id].primary_priv;
579 /* Look for queue index in both private structures. */
580 for (index = 0; index != priv->txqs_n; ++index)
581 if (((*primary_priv->txqs)[index] == txq) ||
582 ((*priv->txqs)[index] == txq))
584 if (index == priv->txqs_n)
586 txq = (*priv->txqs)[index];
587 return priv->dev->tx_pkt_burst(txq, pkts, pkts_n);