1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
18 #pragma GCC diagnostic ignored "-Wpedantic"
20 #include <infiniband/verbs.h>
22 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_common.h>
30 #include "mlx5_utils.h"
31 #include "mlx5_defs.h"
33 #include "mlx5_rxtx.h"
34 #include "mlx5_autoconf.h"
35 #include "mlx5_glue.h"
38 * Allocate TX queue elements.
41 * Pointer to TX queue structure.
44 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
46 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
49 for (i = 0; (i != elts_n); ++i)
50 (*txq_ctrl->txq.elts)[i] = NULL;
51 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
52 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx, elts_n);
53 txq_ctrl->txq.elts_head = 0;
54 txq_ctrl->txq.elts_tail = 0;
55 txq_ctrl->txq.elts_comp = 0;
59 * Free TX queue elements.
62 * Pointer to TX queue structure.
65 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
67 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
68 const uint16_t elts_m = elts_n - 1;
69 uint16_t elts_head = txq_ctrl->txq.elts_head;
70 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
71 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
73 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs",
74 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx);
75 txq_ctrl->txq.elts_head = 0;
76 txq_ctrl->txq.elts_tail = 0;
77 txq_ctrl->txq.elts_comp = 0;
79 while (elts_tail != elts_head) {
80 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
83 rte_pktmbuf_free_seg(elt);
86 memset(&(*elts)[elts_tail & elts_m],
88 sizeof((*elts)[elts_tail & elts_m]));
95 * Returns the per-port supported offloads.
98 * Pointer to Ethernet device.
101 * Supported Tx offloads.
104 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
106 struct mlx5_priv *priv = dev->data->dev_private;
107 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
108 DEV_TX_OFFLOAD_VLAN_INSERT);
109 struct mlx5_dev_config *config = &priv->config;
112 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
113 DEV_TX_OFFLOAD_UDP_CKSUM |
114 DEV_TX_OFFLOAD_TCP_CKSUM);
116 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
119 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
121 offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
122 DEV_TX_OFFLOAD_UDP_TNL_TSO);
124 if (config->tunnel_en) {
126 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
128 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
129 DEV_TX_OFFLOAD_GRE_TNL_TSO);
131 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
132 if (config->dv_flow_en)
133 offloads |= DEV_TX_OFFLOAD_MATCH_METADATA;
139 * DPDK callback to configure a TX queue.
142 * Pointer to Ethernet device structure.
146 * Number of descriptors to configure in queue.
148 * NUMA socket on which memory must be allocated.
150 * Thresholds parameters.
153 * 0 on success, a negative errno value otherwise and rte_errno is set.
156 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
157 unsigned int socket, const struct rte_eth_txconf *conf)
159 struct mlx5_priv *priv = dev->data->dev_private;
160 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
161 struct mlx5_txq_ctrl *txq_ctrl =
162 container_of(txq, struct mlx5_txq_ctrl, txq);
164 if (desc <= MLX5_TX_COMP_THRESH) {
166 "port %u number of descriptors requested for Tx queue"
167 " %u must be higher than MLX5_TX_COMP_THRESH, using %u"
169 dev->data->port_id, idx, MLX5_TX_COMP_THRESH + 1, desc);
170 desc = MLX5_TX_COMP_THRESH + 1;
172 if (!rte_is_power_of_2(desc)) {
173 desc = 1 << log2above(desc);
175 "port %u increased number of descriptors in Tx queue"
176 " %u to the next power of two (%d)",
177 dev->data->port_id, idx, desc);
179 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors",
180 dev->data->port_id, idx, desc);
181 if (idx >= priv->txqs_n) {
182 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)",
183 dev->data->port_id, idx, priv->txqs_n);
184 rte_errno = EOVERFLOW;
187 if (!mlx5_txq_releasable(dev, idx)) {
189 DRV_LOG(ERR, "port %u unable to release queue index %u",
190 dev->data->port_id, idx);
193 mlx5_txq_release(dev, idx);
194 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
196 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
197 dev->data->port_id, idx);
200 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
201 dev->data->port_id, idx);
202 (*priv->txqs)[idx] = &txq_ctrl->txq;
207 * DPDK callback to release a TX queue.
210 * Generic TX queue pointer.
213 mlx5_tx_queue_release(void *dpdk_txq)
215 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
216 struct mlx5_txq_ctrl *txq_ctrl;
217 struct mlx5_priv *priv;
222 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
223 priv = txq_ctrl->priv;
224 for (i = 0; (i != priv->txqs_n); ++i)
225 if ((*priv->txqs)[i] == txq) {
226 mlx5_txq_release(ETH_DEV(priv), i);
227 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
228 PORT_ID(priv), txq->idx);
234 * Initialize Tx UAR registers for primary process.
237 * Pointer to Tx queue control structure.
240 txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
242 struct mlx5_priv *priv = txq_ctrl->priv;
243 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
245 unsigned int lock_idx;
246 const size_t page_size = sysconf(_SC_PAGESIZE);
249 assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
251 ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
253 /* Assign an UAR lock according to UAR page number */
254 lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
255 MLX5_UAR_PAGE_NUM_MASK;
256 txq_ctrl->txq.uar_lock = &priv->uar_lock[lock_idx];
261 * Remap UAR register of a Tx queue for secondary process.
263 * Remapped address is stored at the table in the process private structure of
264 * the device, indexed by queue index.
267 * Pointer to Tx queue control structure.
269 * Verbs file descriptor to map UAR pages.
272 * 0 on success, a negative errno value otherwise and rte_errno is set.
275 txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)
277 struct mlx5_priv *priv = txq_ctrl->priv;
278 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
279 struct mlx5_txq_data *txq = &txq_ctrl->txq;
283 const size_t page_size = sysconf(_SC_PAGESIZE);
287 * As rdma-core, UARs are mapped in size of OS page
288 * size. Ref to libmlx5 function: mlx5_init_context()
290 uar_va = (uintptr_t)txq_ctrl->bf_reg;
291 offset = uar_va & (page_size - 1); /* Offset in page. */
292 addr = mmap(NULL, page_size, PROT_WRITE, MAP_SHARED, fd,
293 txq_ctrl->uar_mmap_offset);
294 if (addr == MAP_FAILED) {
296 "port %u mmap failed for BF reg of txq %u",
297 txq->port_id, txq->idx);
301 addr = RTE_PTR_ADD(addr, offset);
302 ppriv->uar_table[txq->idx] = addr;
307 * Unmap UAR register of a Tx queue for secondary process.
310 * Pointer to Tx queue control structure.
313 txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl)
315 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(txq_ctrl->priv));
316 const size_t page_size = sysconf(_SC_PAGESIZE);
319 addr = ppriv->uar_table[txq_ctrl->txq.idx];
320 munmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
324 * Initialize Tx UAR registers for secondary process.
327 * Pointer to Ethernet device.
329 * Verbs file descriptor to map UAR pages.
332 * 0 on success, a negative errno value otherwise and rte_errno is set.
335 mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd)
337 struct mlx5_priv *priv = dev->data->dev_private;
338 struct mlx5_txq_data *txq;
339 struct mlx5_txq_ctrl *txq_ctrl;
343 assert(rte_eal_process_type() == RTE_PROC_SECONDARY);
344 for (i = 0; i != priv->txqs_n; ++i) {
345 if (!(*priv->txqs)[i])
347 txq = (*priv->txqs)[i];
348 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
349 assert(txq->idx == (uint16_t)i);
350 ret = txq_uar_init_secondary(txq_ctrl, fd);
358 if (!(*priv->txqs)[i])
360 txq = (*priv->txqs)[i];
361 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
362 txq_uar_uninit_secondary(txq_ctrl);
368 * Create the Tx queue Verbs object.
371 * Pointer to Ethernet device.
373 * Queue index in DPDK Tx queue array.
376 * The Verbs object initialised, NULL otherwise and rte_errno is set.
378 struct mlx5_txq_ibv *
379 mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
381 struct mlx5_priv *priv = dev->data->dev_private;
382 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
383 struct mlx5_txq_ctrl *txq_ctrl =
384 container_of(txq_data, struct mlx5_txq_ctrl, txq);
385 struct mlx5_txq_ibv tmpl;
386 struct mlx5_txq_ibv *txq_ibv = NULL;
388 struct ibv_qp_init_attr_ex init;
389 struct ibv_cq_init_attr_ex cq;
390 struct ibv_qp_attr mod;
391 struct ibv_cq_ex cq_attr;
394 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
395 struct mlx5dv_cq cq_info;
396 struct mlx5dv_obj obj;
397 const int desc = 1 << txq_data->elts_n;
401 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
402 priv->verbs_alloc_ctx.obj = txq_ctrl;
403 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
405 "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set",
410 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));
411 attr.cq = (struct ibv_cq_init_attr_ex){
414 cqe_n = desc / MLX5_TX_COMP_THRESH + 1;
415 tmpl.cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);
416 if (tmpl.cq == NULL) {
417 DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
418 dev->data->port_id, idx);
422 attr.init = (struct ibv_qp_init_attr_ex){
423 /* CQ to be associated with the send queue. */
425 /* CQ to be associated with the receive queue. */
428 /* Max number of outstanding WRs. */
430 ((priv->sh->device_attr.orig_attr.max_qp_wr <
432 priv->sh->device_attr.orig_attr.max_qp_wr :
435 * Max number of scatter/gather elements in a WR,
436 * must be 1 to prevent libmlx5 from trying to affect
437 * too much memory. TX gather is not impacted by the
438 * device_attr.max_sge limit and will still work
443 .qp_type = IBV_QPT_RAW_PACKET,
445 * Do *NOT* enable this, completions events are managed per
450 .comp_mask = IBV_QP_INIT_ATTR_PD,
452 if (txq_data->max_inline)
453 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
454 if (txq_data->tso_en) {
455 attr.init.max_tso_header = txq_ctrl->max_tso_header;
456 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
458 tmpl.qp = mlx5_glue->create_qp_ex(priv->sh->ctx, &attr.init);
459 if (tmpl.qp == NULL) {
460 DRV_LOG(ERR, "port %u Tx queue %u QP creation failure",
461 dev->data->port_id, idx);
465 attr.mod = (struct ibv_qp_attr){
466 /* Move the QP to this state. */
467 .qp_state = IBV_QPS_INIT,
468 /* IB device port number. */
469 .port_num = (uint8_t)priv->ibv_port,
471 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
472 (IBV_QP_STATE | IBV_QP_PORT));
475 "port %u Tx queue %u QP state to IBV_QPS_INIT failed",
476 dev->data->port_id, idx);
480 attr.mod = (struct ibv_qp_attr){
481 .qp_state = IBV_QPS_RTR
483 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
486 "port %u Tx queue %u QP state to IBV_QPS_RTR failed",
487 dev->data->port_id, idx);
491 attr.mod.qp_state = IBV_QPS_RTS;
492 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
495 "port %u Tx queue %u QP state to IBV_QPS_RTS failed",
496 dev->data->port_id, idx);
500 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,
503 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory",
504 dev->data->port_id, idx);
509 obj.cq.out = &cq_info;
512 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
517 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
519 "port %u wrong MLX5_CQE_SIZE environment variable"
520 " value: it should be set to %u",
521 dev->data->port_id, RTE_CACHE_LINE_SIZE);
525 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
526 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
527 txq_data->wqes = qp.sq.buf;
528 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
529 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
530 txq_data->cq_db = cq_info.dbrec;
532 (volatile struct mlx5_cqe (*)[])
533 (uintptr_t)cq_info.buf;
538 txq_data->wqe_ci = 0;
539 txq_data->wqe_pi = 0;
540 txq_ibv->qp = tmpl.qp;
541 txq_ibv->cq = tmpl.cq;
542 rte_atomic32_inc(&txq_ibv->refcnt);
543 txq_ctrl->bf_reg = qp.bf.reg;
544 txq_ctrl->cqn = cq_info.cqn;
545 txq_uar_init(txq_ctrl);
546 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
547 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
548 DRV_LOG(DEBUG, "port %u: uar_mmap_offset 0x%"PRIx64,
549 dev->data->port_id, txq_ctrl->uar_mmap_offset);
552 "port %u failed to retrieve UAR info, invalid"
558 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
559 txq_ibv->txq_ctrl = txq_ctrl;
560 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
563 ret = rte_errno; /* Save rte_errno before cleanup. */
565 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
567 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
570 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
571 rte_errno = ret; /* Restore rte_errno. */
576 * Get an Tx queue Verbs object.
579 * Pointer to Ethernet device.
581 * Queue index in DPDK Tx queue array.
584 * The Verbs object if it exists.
586 struct mlx5_txq_ibv *
587 mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
589 struct mlx5_priv *priv = dev->data->dev_private;
590 struct mlx5_txq_ctrl *txq_ctrl;
592 if (idx >= priv->txqs_n)
594 if (!(*priv->txqs)[idx])
596 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
598 rte_atomic32_inc(&txq_ctrl->ibv->refcnt);
599 return txq_ctrl->ibv;
603 * Release an Tx verbs queue object.
606 * Verbs Tx queue object.
609 * 1 while a reference on it exists, 0 when freed.
612 mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv)
615 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {
616 claim_zero(mlx5_glue->destroy_qp(txq_ibv->qp));
617 claim_zero(mlx5_glue->destroy_cq(txq_ibv->cq));
618 LIST_REMOVE(txq_ibv, next);
626 * Verify the Verbs Tx queue list is empty
629 * Pointer to Ethernet device.
632 * The number of object not released.
635 mlx5_txq_ibv_verify(struct rte_eth_dev *dev)
637 struct mlx5_priv *priv = dev->data->dev_private;
639 struct mlx5_txq_ibv *txq_ibv;
641 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) {
642 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced",
643 dev->data->port_id, txq_ibv->txq_ctrl->txq.idx);
650 * Calculate the total number of WQEBB for Tx queue.
652 * Simplified version of calc_sq_size() in rdma-core.
655 * Pointer to Tx queue control structure.
658 * The number of WQEBB.
661 txq_calc_wqebb_cnt(struct mlx5_txq_ctrl *txq_ctrl)
663 unsigned int wqe_size;
664 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
666 wqe_size = MLX5_WQE_SIZE + txq_ctrl->max_inline_data;
667 return rte_align32pow2(wqe_size * desc) / MLX5_WQE_SIZE;
671 * Set Tx queue parameters from device configuration.
674 * Pointer to Tx queue control structure.
677 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
683 * Create a DPDK Tx queue.
686 * Pointer to Ethernet device.
690 * Number of descriptors to configure in queue.
692 * NUMA socket on which memory must be allocated.
694 * Thresholds parameters.
697 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
699 struct mlx5_txq_ctrl *
700 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
701 unsigned int socket, const struct rte_eth_txconf *conf)
703 struct mlx5_priv *priv = dev->data->dev_private;
704 struct mlx5_txq_ctrl *tmpl;
706 tmpl = rte_calloc_socket("TXQ", 1,
708 desc * sizeof(struct rte_mbuf *),
714 if (mlx5_mr_btree_init(&tmpl->txq.mr_ctrl.cache_bh,
715 MLX5_MR_BTREE_CACHE_N, socket)) {
716 /* rte_errno is already set. */
719 /* Save pointer of global generation number to check memory event. */
720 tmpl->txq.mr_ctrl.dev_gen_ptr = &priv->sh->mr.dev_gen;
721 assert(desc > MLX5_TX_COMP_THRESH);
722 tmpl->txq.offloads = conf->offloads |
723 dev->data->dev_conf.txmode.offloads;
725 tmpl->socket = socket;
726 tmpl->txq.elts_n = log2above(desc);
727 tmpl->txq.port_id = dev->data->port_id;
729 txq_set_params(tmpl);
730 if (txq_calc_wqebb_cnt(tmpl) >
731 priv->sh->device_attr.orig_attr.max_qp_wr) {
733 "port %u Tx WQEBB count (%d) exceeds the limit (%d),"
734 " try smaller queue size",
735 dev->data->port_id, txq_calc_wqebb_cnt(tmpl),
736 priv->sh->device_attr.orig_attr.max_qp_wr);
741 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1);
742 rte_atomic32_inc(&tmpl->refcnt);
743 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
754 * Pointer to Ethernet device.
759 * A pointer to the queue if it exists.
761 struct mlx5_txq_ctrl *
762 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
764 struct mlx5_priv *priv = dev->data->dev_private;
765 struct mlx5_txq_ctrl *ctrl = NULL;
767 if ((*priv->txqs)[idx]) {
768 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
770 mlx5_txq_ibv_get(dev, idx);
771 rte_atomic32_inc(&ctrl->refcnt);
777 * Release a Tx queue.
780 * Pointer to Ethernet device.
785 * 1 while a reference on it exists, 0 when freed.
788 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
790 struct mlx5_priv *priv = dev->data->dev_private;
791 struct mlx5_txq_ctrl *txq;
793 if (!(*priv->txqs)[idx])
795 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
796 if (txq->ibv && !mlx5_txq_ibv_release(txq->ibv))
798 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
800 mlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh);
801 LIST_REMOVE(txq, next);
803 (*priv->txqs)[idx] = NULL;
810 * Verify if the queue can be released.
813 * Pointer to Ethernet device.
818 * 1 if the queue can be released.
821 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
823 struct mlx5_priv *priv = dev->data->dev_private;
824 struct mlx5_txq_ctrl *txq;
826 if (!(*priv->txqs)[idx])
828 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
829 return (rte_atomic32_read(&txq->refcnt) == 1);
833 * Verify the Tx Queue list is empty
836 * Pointer to Ethernet device.
839 * The number of object not released.
842 mlx5_txq_verify(struct rte_eth_dev *dev)
844 struct mlx5_priv *priv = dev->data->dev_private;
845 struct mlx5_txq_ctrl *txq_ctrl;
848 LIST_FOREACH(txq_ctrl, &priv->txqsctrl, next) {
849 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced",
850 dev->data->port_id, txq_ctrl->txq.idx);