4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-pedantic"
45 #include <infiniband/verbs.h>
47 #pragma GCC diagnostic error "-pedantic"
50 /* DPDK headers don't like -pedantic. */
52 #pragma GCC diagnostic ignored "-pedantic"
55 #include <rte_malloc.h>
56 #include <rte_ethdev.h>
57 #include <rte_common.h>
59 #pragma GCC diagnostic error "-pedantic"
62 #include "mlx5_utils.h"
64 #include "mlx5_rxtx.h"
65 #include "mlx5_autoconf.h"
66 #include "mlx5_defs.h"
69 * Allocate TX queue elements.
72 * Pointer to TX queue structure.
74 * Number of elements to allocate.
77 * 0 on success, errno value on failure.
80 txq_alloc_elts(struct txq *txq, unsigned int elts_n)
83 struct txq_elt (*elts)[elts_n] =
84 rte_calloc_socket("TXQ", 1, sizeof(*elts), 0, txq->socket);
85 linear_t (*elts_linear)[elts_n] =
86 rte_calloc_socket("TXQ", 1, sizeof(*elts_linear), 0,
88 struct ibv_mr *mr_linear = NULL;
91 if ((elts == NULL) || (elts_linear == NULL)) {
92 ERROR("%p: can't allocate packets array", (void *)txq);
97 ibv_reg_mr(txq->priv->pd, elts_linear, sizeof(*elts_linear),
98 (IBV_ACCESS_LOCAL_WRITE | IBV_ACCESS_REMOTE_WRITE));
99 if (mr_linear == NULL) {
100 ERROR("%p: unable to configure MR, ibv_reg_mr() failed",
105 for (i = 0; (i != elts_n); ++i) {
106 struct txq_elt *elt = &(*elts)[i];
110 DEBUG("%p: allocated and configured %u WRs", (void *)txq, elts_n);
111 txq->elts_n = elts_n;
116 /* Request send completion every MLX5_PMD_TX_PER_COMP_REQ packets or
117 * at least 4 times per ring. */
118 txq->elts_comp_cd_init =
119 ((MLX5_PMD_TX_PER_COMP_REQ < (elts_n / 4)) ?
120 MLX5_PMD_TX_PER_COMP_REQ : (elts_n / 4));
121 txq->elts_comp_cd = txq->elts_comp_cd_init;
122 txq->elts_linear = elts_linear;
123 txq->mr_linear = mr_linear;
127 if (mr_linear != NULL)
128 claim_zero(ibv_dereg_mr(mr_linear));
130 rte_free(elts_linear);
133 DEBUG("%p: failed, freed everything", (void *)txq);
139 * Free TX queue elements.
142 * Pointer to TX queue structure.
145 txq_free_elts(struct txq *txq)
148 unsigned int elts_n = txq->elts_n;
149 struct txq_elt (*elts)[elts_n] = txq->elts;
150 linear_t (*elts_linear)[elts_n] = txq->elts_linear;
151 struct ibv_mr *mr_linear = txq->mr_linear;
153 DEBUG("%p: freeing WRs", (void *)txq);
156 txq->elts_linear = NULL;
157 txq->mr_linear = NULL;
158 if (mr_linear != NULL)
159 claim_zero(ibv_dereg_mr(mr_linear));
161 rte_free(elts_linear);
164 for (i = 0; (i != RTE_DIM(*elts)); ++i) {
165 struct txq_elt *elt = &(*elts)[i];
167 if (elt->buf == NULL)
169 rte_pktmbuf_free(elt->buf);
175 * Clean up a TX queue.
177 * Destroy objects, free allocated memory and reset the structure for reuse.
180 * Pointer to TX queue structure.
183 txq_cleanup(struct txq *txq)
185 struct ibv_exp_release_intf_params params;
188 DEBUG("cleaning up %p", (void *)txq);
190 txq->poll_cnt = NULL;
191 #if MLX5_PMD_MAX_INLINE > 0
192 txq->send_pending_inline = NULL;
194 txq->send_flush = NULL;
195 if (txq->if_qp != NULL) {
196 assert(txq->priv != NULL);
197 assert(txq->priv->ctx != NULL);
198 assert(txq->qp != NULL);
199 params = (struct ibv_exp_release_intf_params){
202 claim_zero(ibv_exp_release_intf(txq->priv->ctx,
206 if (txq->if_cq != NULL) {
207 assert(txq->priv != NULL);
208 assert(txq->priv->ctx != NULL);
209 assert(txq->cq != NULL);
210 params = (struct ibv_exp_release_intf_params){
213 claim_zero(ibv_exp_release_intf(txq->priv->ctx,
218 claim_zero(ibv_destroy_qp(txq->qp));
220 claim_zero(ibv_destroy_cq(txq->cq));
221 if (txq->rd != NULL) {
222 struct ibv_exp_destroy_res_domain_attr attr = {
226 assert(txq->priv != NULL);
227 assert(txq->priv->ctx != NULL);
228 claim_zero(ibv_exp_destroy_res_domain(txq->priv->ctx,
232 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
233 if (txq->mp2mr[i].mp == NULL)
235 assert(txq->mp2mr[i].mr != NULL);
236 claim_zero(ibv_dereg_mr(txq->mp2mr[i].mr));
238 memset(txq, 0, sizeof(*txq));
242 * Configure a TX queue.
245 * Pointer to Ethernet device structure.
247 * Pointer to TX queue structure.
249 * Number of descriptors to configure in queue.
251 * NUMA socket on which memory must be allocated.
253 * Thresholds parameters.
256 * 0 on success, errno value on failure.
259 txq_setup(struct rte_eth_dev *dev, struct txq *txq, uint16_t desc,
260 unsigned int socket, const struct rte_eth_txconf *conf)
262 struct priv *priv = mlx5_get_priv(dev);
268 struct ibv_exp_query_intf_params params;
269 struct ibv_exp_qp_init_attr init;
270 struct ibv_exp_res_domain_init_attr rd;
271 struct ibv_exp_cq_init_attr cq;
272 struct ibv_exp_qp_attr mod;
274 enum ibv_exp_query_intf_status status;
277 (void)conf; /* Thresholds configuration (ignored). */
278 if ((desc == 0) || (desc % MLX5_PMD_SGE_WR_N)) {
279 ERROR("%p: invalid number of TX descriptors (must be a"
280 " multiple of %d)", (void *)dev, MLX5_PMD_SGE_WR_N);
283 desc /= MLX5_PMD_SGE_WR_N;
284 /* MRs will be registered in mp2mr[] later. */
285 attr.rd = (struct ibv_exp_res_domain_init_attr){
286 .comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL |
287 IBV_EXP_RES_DOMAIN_MSG_MODEL),
288 .thread_model = IBV_EXP_THREAD_SINGLE,
289 .msg_model = IBV_EXP_MSG_HIGH_BW,
291 tmpl.rd = ibv_exp_create_res_domain(priv->ctx, &attr.rd);
292 if (tmpl.rd == NULL) {
294 ERROR("%p: RD creation failure: %s",
295 (void *)dev, strerror(ret));
298 attr.cq = (struct ibv_exp_cq_init_attr){
299 .comp_mask = IBV_EXP_CQ_INIT_ATTR_RES_DOMAIN,
300 .res_domain = tmpl.rd,
302 tmpl.cq = ibv_exp_create_cq(priv->ctx, desc, NULL, NULL, 0, &attr.cq);
303 if (tmpl.cq == NULL) {
305 ERROR("%p: CQ creation failure: %s",
306 (void *)dev, strerror(ret));
309 DEBUG("priv->device_attr.max_qp_wr is %d",
310 priv->device_attr.max_qp_wr);
311 DEBUG("priv->device_attr.max_sge is %d",
312 priv->device_attr.max_sge);
313 attr.init = (struct ibv_exp_qp_init_attr){
314 /* CQ to be associated with the send queue. */
316 /* CQ to be associated with the receive queue. */
319 /* Max number of outstanding WRs. */
320 .max_send_wr = ((priv->device_attr.max_qp_wr < desc) ?
321 priv->device_attr.max_qp_wr :
323 /* Max number of scatter/gather elements in a WR. */
324 .max_send_sge = ((priv->device_attr.max_sge <
326 priv->device_attr.max_sge :
328 #if MLX5_PMD_MAX_INLINE > 0
329 .max_inline_data = MLX5_PMD_MAX_INLINE,
332 .qp_type = IBV_QPT_RAW_PACKET,
333 /* Do *NOT* enable this, completions events are managed per
337 .res_domain = tmpl.rd,
338 .comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |
339 IBV_EXP_QP_INIT_ATTR_RES_DOMAIN),
341 tmpl.qp = ibv_exp_create_qp(priv->ctx, &attr.init);
342 if (tmpl.qp == NULL) {
343 ret = (errno ? errno : EINVAL);
344 ERROR("%p: QP creation failure: %s",
345 (void *)dev, strerror(ret));
348 #if MLX5_PMD_MAX_INLINE > 0
349 /* ibv_create_qp() updates this value. */
350 tmpl.max_inline = attr.init.cap.max_inline_data;
352 attr.mod = (struct ibv_exp_qp_attr){
353 /* Move the QP to this state. */
354 .qp_state = IBV_QPS_INIT,
355 /* Primary port number. */
356 .port_num = priv->port
358 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod,
359 (IBV_EXP_QP_STATE | IBV_EXP_QP_PORT));
361 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
362 (void *)dev, strerror(ret));
365 ret = txq_alloc_elts(&tmpl, desc);
367 ERROR("%p: TXQ allocation failed: %s",
368 (void *)dev, strerror(ret));
371 attr.mod = (struct ibv_exp_qp_attr){
372 .qp_state = IBV_QPS_RTR
374 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
376 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
377 (void *)dev, strerror(ret));
380 attr.mod.qp_state = IBV_QPS_RTS;
381 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
383 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
384 (void *)dev, strerror(ret));
387 attr.params = (struct ibv_exp_query_intf_params){
388 .intf_scope = IBV_EXP_INTF_GLOBAL,
389 .intf = IBV_EXP_INTF_CQ,
392 tmpl.if_cq = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
393 if (tmpl.if_cq == NULL) {
395 ERROR("%p: CQ interface family query failed with status %d",
396 (void *)dev, status);
399 attr.params = (struct ibv_exp_query_intf_params){
400 .intf_scope = IBV_EXP_INTF_GLOBAL,
401 .intf = IBV_EXP_INTF_QP_BURST,
403 #ifdef HAVE_EXP_QP_BURST_CREATE_ENABLE_MULTI_PACKET_SEND_WR
404 /* Multi packet send WR can only be used outside of VF. */
407 IBV_EXP_QP_BURST_CREATE_ENABLE_MULTI_PACKET_SEND_WR :
411 tmpl.if_qp = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
412 if (tmpl.if_qp == NULL) {
414 ERROR("%p: QP interface family query failed with status %d",
415 (void *)dev, status);
418 /* Clean up txq in case we're reinitializing it. */
419 DEBUG("%p: cleaning-up old txq just in case", (void *)txq);
422 txq->poll_cnt = txq->if_cq->poll_cnt;
423 #if MLX5_PMD_MAX_INLINE > 0
424 txq->send_pending_inline = txq->if_qp->send_pending_inline;
426 #if MLX5_PMD_SGE_WR_N > 1
427 txq->send_pending_sg_list = txq->if_qp->send_pending_sg_list;
429 txq->send_pending = txq->if_qp->send_pending;
430 txq->send_flush = txq->if_qp->send_flush;
431 DEBUG("%p: txq updated with %p", (void *)txq, (void *)&tmpl);
432 /* Pre-register known mempools. */
433 rte_mempool_walk(txq_mp2mr_iter, txq);
443 * DPDK callback to configure a TX queue.
446 * Pointer to Ethernet device structure.
450 * Number of descriptors to configure in queue.
452 * NUMA socket on which memory must be allocated.
454 * Thresholds parameters.
457 * 0 on success, negative errno value on failure.
460 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
461 unsigned int socket, const struct rte_eth_txconf *conf)
463 struct priv *priv = dev->data->dev_private;
464 struct txq *txq = (*priv->txqs)[idx];
467 if (mlx5_is_secondary())
468 return -E_RTE_SECONDARY;
471 DEBUG("%p: configuring queue %u for %u descriptors",
472 (void *)dev, idx, desc);
473 if (idx >= priv->txqs_n) {
474 ERROR("%p: queue index out of range (%u >= %u)",
475 (void *)dev, idx, priv->txqs_n);
480 DEBUG("%p: reusing already allocated queue index %u (%p)",
481 (void *)dev, idx, (void *)txq);
486 (*priv->txqs)[idx] = NULL;
489 txq = rte_calloc_socket("TXQ", 1, sizeof(*txq), 0, socket);
491 ERROR("%p: unable to allocate queue index %u",
497 ret = txq_setup(dev, txq, desc, socket, conf);
501 txq->stats.idx = idx;
502 DEBUG("%p: adding TX queue %p to list",
503 (void *)dev, (void *)txq);
504 (*priv->txqs)[idx] = txq;
505 /* Update send callback. */
506 dev->tx_pkt_burst = mlx5_tx_burst;
513 * DPDK callback to release a TX queue.
516 * Generic TX queue pointer.
519 mlx5_tx_queue_release(void *dpdk_txq)
521 struct txq *txq = (struct txq *)dpdk_txq;
525 if (mlx5_is_secondary())
532 for (i = 0; (i != priv->txqs_n); ++i)
533 if ((*priv->txqs)[i] == txq) {
534 DEBUG("%p: removing TX queue %p from list",
535 (void *)priv->dev, (void *)txq);
536 (*priv->txqs)[i] = NULL;
545 * DPDK callback for TX in secondary processes.
547 * This function configures all queues from primary process information
548 * if necessary before reverting to the normal TX burst callback.
551 * Generic pointer to TX queue structure.
553 * Packets to transmit.
555 * Number of packets in array.
558 * Number of packets successfully transmitted (<= pkts_n).
561 mlx5_tx_burst_secondary_setup(void *dpdk_txq, struct rte_mbuf **pkts,
564 struct txq *txq = dpdk_txq;
565 struct priv *priv = mlx5_secondary_data_setup(txq->priv);
566 struct priv *primary_priv;
572 mlx5_secondary_data[priv->dev->data->port_id].primary_priv;
573 /* Look for queue index in both private structures. */
574 for (index = 0; index != priv->txqs_n; ++index)
575 if (((*primary_priv->txqs)[index] == txq) ||
576 ((*priv->txqs)[index] == txq))
578 if (index == priv->txqs_n)
580 txq = (*priv->txqs)[index];
581 return priv->dev->tx_pkt_burst(txq, pkts, pkts_n);