1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_malloc.h>
26 #include <rte_ethdev_driver.h>
27 #include <rte_common.h>
29 #include "mlx5_utils.h"
30 #include "mlx5_defs.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_glue.h"
37 * Allocate TX queue elements.
40 * Pointer to TX queue structure.
43 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
45 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
48 for (i = 0; (i != elts_n); ++i)
49 (*txq_ctrl->txq.elts)[i] = NULL;
50 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
51 PORT_ID(txq_ctrl->priv), txq_ctrl->idx, elts_n);
52 txq_ctrl->txq.elts_head = 0;
53 txq_ctrl->txq.elts_tail = 0;
54 txq_ctrl->txq.elts_comp = 0;
58 * Free TX queue elements.
61 * Pointer to TX queue structure.
64 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
66 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
67 const uint16_t elts_m = elts_n - 1;
68 uint16_t elts_head = txq_ctrl->txq.elts_head;
69 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
70 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
72 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs",
73 PORT_ID(txq_ctrl->priv), txq_ctrl->idx);
74 txq_ctrl->txq.elts_head = 0;
75 txq_ctrl->txq.elts_tail = 0;
76 txq_ctrl->txq.elts_comp = 0;
78 while (elts_tail != elts_head) {
79 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
82 rte_pktmbuf_free_seg(elt);
85 memset(&(*elts)[elts_tail & elts_m],
87 sizeof((*elts)[elts_tail & elts_m]));
94 * Returns the per-port supported offloads.
97 * Pointer to Ethernet device.
100 * Supported Tx offloads.
103 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
105 struct priv *priv = dev->data->dev_private;
106 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
107 DEV_TX_OFFLOAD_VLAN_INSERT);
108 struct mlx5_dev_config *config = &priv->config;
111 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
112 DEV_TX_OFFLOAD_UDP_CKSUM |
113 DEV_TX_OFFLOAD_TCP_CKSUM);
115 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
116 if (config->tunnel_en) {
118 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
120 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
121 DEV_TX_OFFLOAD_GRE_TNL_TSO);
123 offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
124 DEV_TX_OFFLOAD_UDP_TNL_TSO);
130 * DPDK callback to configure a TX queue.
133 * Pointer to Ethernet device structure.
137 * Number of descriptors to configure in queue.
139 * NUMA socket on which memory must be allocated.
141 * Thresholds parameters.
144 * 0 on success, a negative errno value otherwise and rte_errno is set.
147 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
148 unsigned int socket, const struct rte_eth_txconf *conf)
150 struct priv *priv = dev->data->dev_private;
151 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
152 struct mlx5_txq_ctrl *txq_ctrl =
153 container_of(txq, struct mlx5_txq_ctrl, txq);
155 if (desc <= MLX5_TX_COMP_THRESH) {
157 "port %u number of descriptors requested for Tx queue"
158 " %u must be higher than MLX5_TX_COMP_THRESH, using %u"
160 dev->data->port_id, idx, MLX5_TX_COMP_THRESH + 1, desc);
161 desc = MLX5_TX_COMP_THRESH + 1;
163 if (!rte_is_power_of_2(desc)) {
164 desc = 1 << log2above(desc);
166 "port %u increased number of descriptors in Tx queue"
167 " %u to the next power of two (%d)",
168 dev->data->port_id, idx, desc);
170 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors",
171 dev->data->port_id, idx, desc);
172 if (idx >= priv->txqs_n) {
173 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)",
174 dev->data->port_id, idx, priv->txqs_n);
175 rte_errno = EOVERFLOW;
178 if (!mlx5_txq_releasable(dev, idx)) {
180 DRV_LOG(ERR, "port %u unable to release queue index %u",
181 dev->data->port_id, idx);
184 mlx5_txq_release(dev, idx);
185 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
187 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
188 dev->data->port_id, idx);
191 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
192 dev->data->port_id, idx);
193 (*priv->txqs)[idx] = &txq_ctrl->txq;
198 * DPDK callback to release a TX queue.
201 * Generic TX queue pointer.
204 mlx5_tx_queue_release(void *dpdk_txq)
206 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
207 struct mlx5_txq_ctrl *txq_ctrl;
213 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
214 priv = txq_ctrl->priv;
215 for (i = 0; (i != priv->txqs_n); ++i)
216 if ((*priv->txqs)[i] == txq) {
217 mlx5_txq_release(ETH_DEV(priv), i);
218 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
219 PORT_ID(priv), txq_ctrl->idx);
226 * Mmap TX UAR(HW doorbell) pages into reserved UAR address space.
227 * Both primary and secondary process do mmap to make UAR address
231 * Pointer to Ethernet device.
233 * Verbs file descriptor to map UAR pages.
236 * 0 on success, a negative errno value otherwise and rte_errno is set.
239 mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd)
241 struct priv *priv = dev->data->dev_private;
243 uintptr_t pages[priv->txqs_n];
244 unsigned int pages_n = 0;
249 struct mlx5_txq_data *txq;
250 struct mlx5_txq_ctrl *txq_ctrl;
252 size_t page_size = sysconf(_SC_PAGESIZE);
254 memset(pages, 0, priv->txqs_n * sizeof(uintptr_t));
256 * As rdma-core, UARs are mapped in size of OS page size.
257 * Use aligned address to avoid duplicate mmap.
258 * Ref to libmlx5 function: mlx5_init_context()
260 for (i = 0; i != priv->txqs_n; ++i) {
261 if (!(*priv->txqs)[i])
263 txq = (*priv->txqs)[i];
264 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
265 assert(txq_ctrl->idx == (uint16_t)i);
266 /* UAR addr form verbs used to find dup and offset in page. */
267 uar_va = (uintptr_t)txq_ctrl->bf_reg_orig;
268 off = uar_va & (page_size - 1); /* offset in page. */
269 uar_va = RTE_ALIGN_FLOOR(uar_va, page_size); /* page addr. */
271 for (j = 0; j != pages_n; ++j) {
272 if (pages[j] == uar_va) {
277 /* new address in reserved UAR address space. */
278 addr = RTE_PTR_ADD(priv->uar_base,
279 uar_va & (MLX5_UAR_SIZE - 1));
280 if (!already_mapped) {
281 pages[pages_n++] = uar_va;
282 /* fixed mmap to specified address in reserved
285 ret = mmap(addr, page_size,
286 PROT_WRITE, MAP_FIXED | MAP_SHARED, fd,
287 txq_ctrl->uar_mmap_offset);
289 /* fixed mmap have to return same address */
291 "port %u call to mmap failed on UAR"
293 dev->data->port_id, txq_ctrl->idx);
298 if (rte_eal_process_type() == RTE_PROC_PRIMARY) /* save once */
299 txq_ctrl->txq.bf_reg = RTE_PTR_ADD((void *)addr, off);
301 assert(txq_ctrl->txq.bf_reg ==
302 RTE_PTR_ADD((void *)addr, off));
308 * Check if the burst function is using eMPW.
310 * @param tx_pkt_burst
311 * Tx burst function pointer.
314 * 1 if the burst function is using eMPW, 0 otherwise.
317 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst)
319 if (tx_pkt_burst == mlx5_tx_burst_raw_vec ||
320 tx_pkt_burst == mlx5_tx_burst_vec ||
321 tx_pkt_burst == mlx5_tx_burst_empw)
327 * Create the Tx queue Verbs object.
330 * Pointer to Ethernet device.
332 * Queue index in DPDK Rx queue array
335 * The Verbs object initialised, NULL otherwise and rte_errno is set.
337 struct mlx5_txq_ibv *
338 mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
340 struct priv *priv = dev->data->dev_private;
341 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
342 struct mlx5_txq_ctrl *txq_ctrl =
343 container_of(txq_data, struct mlx5_txq_ctrl, txq);
344 struct mlx5_txq_ibv tmpl;
345 struct mlx5_txq_ibv *txq_ibv;
347 struct ibv_qp_init_attr_ex init;
348 struct ibv_cq_init_attr_ex cq;
349 struct ibv_qp_attr mod;
350 struct ibv_cq_ex cq_attr;
353 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
354 struct mlx5dv_cq cq_info;
355 struct mlx5dv_obj obj;
356 const int desc = 1 << txq_data->elts_n;
357 eth_tx_burst_t tx_pkt_burst = mlx5_select_tx_function(dev);
361 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
362 priv->verbs_alloc_ctx.obj = txq_ctrl;
363 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
365 "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set",
370 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));
371 /* MRs will be registered in mp2mr[] later. */
372 attr.cq = (struct ibv_cq_init_attr_ex){
375 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
376 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
377 if (is_empw_burst_func(tx_pkt_burst))
378 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
379 tmpl.cq = mlx5_glue->create_cq(priv->ctx, cqe_n, NULL, NULL, 0);
380 if (tmpl.cq == NULL) {
381 DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
382 dev->data->port_id, idx);
386 attr.init = (struct ibv_qp_init_attr_ex){
387 /* CQ to be associated with the send queue. */
389 /* CQ to be associated with the receive queue. */
392 /* Max number of outstanding WRs. */
394 ((priv->device_attr.orig_attr.max_qp_wr <
396 priv->device_attr.orig_attr.max_qp_wr :
399 * Max number of scatter/gather elements in a WR,
400 * must be 1 to prevent libmlx5 from trying to affect
401 * too much memory. TX gather is not impacted by the
402 * priv->device_attr.max_sge limit and will still work
407 .qp_type = IBV_QPT_RAW_PACKET,
409 * Do *NOT* enable this, completions events are managed per
414 .comp_mask = IBV_QP_INIT_ATTR_PD,
416 if (txq_data->max_inline)
417 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
418 if (txq_data->tso_en) {
419 attr.init.max_tso_header = txq_ctrl->max_tso_header;
420 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
422 tmpl.qp = mlx5_glue->create_qp_ex(priv->ctx, &attr.init);
423 if (tmpl.qp == NULL) {
424 DRV_LOG(ERR, "port %u Tx queue %u QP creation failure",
425 dev->data->port_id, idx);
429 attr.mod = (struct ibv_qp_attr){
430 /* Move the QP to this state. */
431 .qp_state = IBV_QPS_INIT,
432 /* Primary port number. */
433 .port_num = priv->port
435 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
436 (IBV_QP_STATE | IBV_QP_PORT));
439 "port %u Tx queue %u QP state to IBV_QPS_INIT failed",
440 dev->data->port_id, idx);
444 attr.mod = (struct ibv_qp_attr){
445 .qp_state = IBV_QPS_RTR
447 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
450 "port %u Tx queue %u QP state to IBV_QPS_RTR failed",
451 dev->data->port_id, idx);
455 attr.mod.qp_state = IBV_QPS_RTS;
456 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
459 "port %u Tx queue %u QP state to IBV_QPS_RTS failed",
460 dev->data->port_id, idx);
464 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,
467 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory",
468 dev->data->port_id, idx);
473 obj.cq.out = &cq_info;
476 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
481 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
483 "port %u wrong MLX5_CQE_SIZE environment variable"
484 " value: it should be set to %u",
485 dev->data->port_id, RTE_CACHE_LINE_SIZE);
489 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
490 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
491 txq_data->wqes = qp.sq.buf;
492 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
493 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
494 txq_ctrl->bf_reg_orig = qp.bf.reg;
495 txq_data->cq_db = cq_info.dbrec;
497 (volatile struct mlx5_cqe (*)[])
498 (uintptr_t)cq_info.buf;
503 txq_data->wqe_ci = 0;
504 txq_data->wqe_pi = 0;
505 txq_ibv->qp = tmpl.qp;
506 txq_ibv->cq = tmpl.cq;
507 rte_atomic32_inc(&txq_ibv->refcnt);
508 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
509 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
512 "port %u failed to retrieve UAR info, invalid"
518 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u: refcnt %d",
519 dev->data->port_id, idx, rte_atomic32_read(&txq_ibv->refcnt));
520 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
521 txq_ibv->txq_ctrl = txq_ctrl;
522 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
525 ret = rte_errno; /* Save rte_errno before cleanup. */
527 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
529 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
530 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
531 rte_errno = ret; /* Restore rte_errno. */
536 * Get an Tx queue Verbs object.
539 * Pointer to Ethernet device.
541 * Queue index in DPDK Rx queue array
544 * The Verbs object if it exists.
546 struct mlx5_txq_ibv *
547 mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
549 struct priv *priv = dev->data->dev_private;
550 struct mlx5_txq_ctrl *txq_ctrl;
552 if (idx >= priv->txqs_n)
554 if (!(*priv->txqs)[idx])
556 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
558 rte_atomic32_inc(&txq_ctrl->ibv->refcnt);
559 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u: refcnt %d",
560 dev->data->port_id, txq_ctrl->idx,
561 rte_atomic32_read(&txq_ctrl->ibv->refcnt));
563 return txq_ctrl->ibv;
567 * Release an Tx verbs queue object.
570 * Verbs Tx queue object.
573 * 1 while a reference on it exists, 0 when freed.
576 mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv)
579 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u: refcnt %d",
580 PORT_ID(txq_ibv->txq_ctrl->priv),
581 txq_ibv->txq_ctrl->idx, rte_atomic32_read(&txq_ibv->refcnt));
582 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {
583 claim_zero(mlx5_glue->destroy_qp(txq_ibv->qp));
584 claim_zero(mlx5_glue->destroy_cq(txq_ibv->cq));
585 LIST_REMOVE(txq_ibv, next);
593 * Return true if a single reference exists on the object.
596 * Verbs Tx queue object.
599 mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv)
602 return (rte_atomic32_read(&txq_ibv->refcnt) == 1);
606 * Verify the Verbs Tx queue list is empty
609 * Pointer to Ethernet device.
612 * The number of object not released.
615 mlx5_txq_ibv_verify(struct rte_eth_dev *dev)
617 struct priv *priv = dev->data->dev_private;
619 struct mlx5_txq_ibv *txq_ibv;
621 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) {
622 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced",
623 dev->data->port_id, txq_ibv->txq_ctrl->idx);
630 * Set Tx queue parameters from device configuration.
633 * Pointer to Tx queue control structure.
636 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
638 struct priv *priv = txq_ctrl->priv;
639 struct mlx5_dev_config *config = &priv->config;
640 const unsigned int max_tso_inline =
641 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) /
642 RTE_CACHE_LINE_SIZE);
643 unsigned int txq_inline;
644 unsigned int txqs_inline;
645 unsigned int inline_max_packet_sz;
646 eth_tx_burst_t tx_pkt_burst =
647 mlx5_select_tx_function(ETH_DEV(priv));
648 int is_empw_func = is_empw_burst_func(tx_pkt_burst);
649 int tso = !!(txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO |
650 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
651 DEV_TX_OFFLOAD_GRE_TNL_TSO |
652 DEV_TX_OFFLOAD_IP_TNL_TSO |
653 DEV_TX_OFFLOAD_UDP_TNL_TSO));
655 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ?
656 0 : config->txq_inline;
657 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ?
658 0 : config->txqs_inline;
659 inline_max_packet_sz =
660 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ?
661 0 : config->inline_max_packet_sz;
663 if (config->txq_inline == MLX5_ARG_UNSET)
664 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;
665 if (config->txqs_inline == MLX5_ARG_UNSET)
666 txqs_inline = MLX5_EMPW_MIN_TXQS;
667 if (config->inline_max_packet_sz == MLX5_ARG_UNSET)
668 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN;
669 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg;
670 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz;
672 if (txq_inline && priv->txqs_n >= txqs_inline) {
675 txq_ctrl->txq.max_inline =
676 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
677 RTE_CACHE_LINE_SIZE);
679 /* To minimize the size of data set, avoid requesting
682 txq_ctrl->max_inline_data =
683 ((RTE_MIN(txq_inline,
684 inline_max_packet_sz) +
685 (RTE_CACHE_LINE_SIZE - 1)) /
686 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
688 txq_ctrl->max_inline_data =
689 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE;
692 * Check if the inline size is too large in a way which
693 * can make the WQE DS to overflow.
694 * Considering in calculation:
699 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE);
700 if (ds_cnt > MLX5_DSEG_MAX) {
701 unsigned int max_inline = (MLX5_DSEG_MAX - 2) *
704 max_inline = max_inline - (max_inline %
705 RTE_CACHE_LINE_SIZE);
707 "port %u txq inline is too large (%d) setting"
708 " it to the maximum possible: %d\n",
709 PORT_ID(priv), txq_inline, max_inline);
710 txq_ctrl->txq.max_inline = max_inline /
715 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE;
716 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline,
718 txq_ctrl->txq.tso_en = 1;
720 txq_ctrl->txq.tunnel_en = config->tunnel_en;
721 txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
722 DEV_TX_OFFLOAD_UDP_TNL_TSO |
723 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
724 txq_ctrl->txq.offloads) && config->swp;
728 * Create a DPDK Tx queue.
731 * Pointer to Ethernet device.
735 * Number of descriptors to configure in queue.
737 * NUMA socket on which memory must be allocated.
739 * Thresholds parameters.
742 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
744 struct mlx5_txq_ctrl *
745 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
746 unsigned int socket, const struct rte_eth_txconf *conf)
748 struct priv *priv = dev->data->dev_private;
749 struct mlx5_txq_ctrl *tmpl;
751 tmpl = rte_calloc_socket("TXQ", 1,
753 desc * sizeof(struct rte_mbuf *),
759 assert(desc > MLX5_TX_COMP_THRESH);
760 tmpl->txq.offloads = conf->offloads |
761 dev->data->dev_conf.txmode.offloads;
763 tmpl->socket = socket;
764 tmpl->txq.elts_n = log2above(desc);
766 txq_set_params(tmpl);
767 /* MRs will be registered in mp2mr[] later. */
768 DRV_LOG(DEBUG, "port %u priv->device_attr.max_qp_wr is %d",
769 dev->data->port_id, priv->device_attr.orig_attr.max_qp_wr);
770 DRV_LOG(DEBUG, "port %u priv->device_attr.max_sge is %d",
771 dev->data->port_id, priv->device_attr.orig_attr.max_sge);
773 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1);
774 tmpl->txq.stats.idx = idx;
775 rte_atomic32_inc(&tmpl->refcnt);
776 DRV_LOG(DEBUG, "port %u Tx queue %u: refcnt %d", dev->data->port_id,
777 idx, rte_atomic32_read(&tmpl->refcnt));
778 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
786 * Pointer to Ethernet device.
791 * A pointer to the queue if it exists.
793 struct mlx5_txq_ctrl *
794 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
796 struct priv *priv = dev->data->dev_private;
797 struct mlx5_txq_ctrl *ctrl = NULL;
799 if ((*priv->txqs)[idx]) {
800 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
804 mlx5_txq_ibv_get(dev, idx);
805 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
806 if (ctrl->txq.mp2mr[i])
809 ctrl->txq.mp2mr[i]->mp));
811 rte_atomic32_inc(&ctrl->refcnt);
812 DRV_LOG(DEBUG, "port %u Tx queue %u refcnt %d",
814 ctrl->idx, rte_atomic32_read(&ctrl->refcnt));
820 * Release a Tx queue.
823 * Pointer to Ethernet device.
828 * 1 while a reference on it exists, 0 when freed.
831 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
833 struct priv *priv = dev->data->dev_private;
835 struct mlx5_txq_ctrl *txq;
836 size_t page_size = sysconf(_SC_PAGESIZE);
838 if (!(*priv->txqs)[idx])
840 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
841 DRV_LOG(DEBUG, "port %u Tx queue %u: refcnt %d", dev->data->port_id,
842 txq->idx, rte_atomic32_read(&txq->refcnt));
843 if (txq->ibv && !mlx5_txq_ibv_release(txq->ibv))
845 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
846 if (txq->txq.mp2mr[i]) {
847 mlx5_mr_release(txq->txq.mp2mr[i]);
848 txq->txq.mp2mr[i] = NULL;
852 munmap((void *)RTE_ALIGN_FLOOR((uintptr_t)txq->txq.bf_reg,
853 page_size), page_size);
854 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
856 LIST_REMOVE(txq, next);
858 (*priv->txqs)[idx] = NULL;
865 * Verify if the queue can be released.
868 * Pointer to Ethernet device.
873 * 1 if the queue can be released.
876 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
878 struct priv *priv = dev->data->dev_private;
879 struct mlx5_txq_ctrl *txq;
881 if (!(*priv->txqs)[idx])
883 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
884 return (rte_atomic32_read(&txq->refcnt) == 1);
888 * Verify the Tx Queue list is empty
891 * Pointer to Ethernet device.
894 * The number of object not released.
897 mlx5_txq_verify(struct rte_eth_dev *dev)
899 struct priv *priv = dev->data->dev_private;
900 struct mlx5_txq_ctrl *txq;
903 LIST_FOREACH(txq, &priv->txqsctrl, next) {
904 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced",
905 dev->data->port_id, txq->idx);