1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
18 #pragma GCC diagnostic ignored "-Wpedantic"
20 #include <infiniband/verbs.h>
22 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_common.h>
30 #include "mlx5_utils.h"
31 #include "mlx5_defs.h"
33 #include "mlx5_rxtx.h"
34 #include "mlx5_autoconf.h"
35 #include "mlx5_glue.h"
38 * Allocate TX queue elements.
41 * Pointer to TX queue structure.
44 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
46 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
49 for (i = 0; (i != elts_n); ++i)
50 (*txq_ctrl->txq.elts)[i] = NULL;
51 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
52 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx, elts_n);
53 txq_ctrl->txq.elts_head = 0;
54 txq_ctrl->txq.elts_tail = 0;
55 txq_ctrl->txq.elts_comp = 0;
59 * Free TX queue elements.
62 * Pointer to TX queue structure.
65 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
67 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
68 const uint16_t elts_m = elts_n - 1;
69 uint16_t elts_head = txq_ctrl->txq.elts_head;
70 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
71 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
73 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs",
74 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx);
75 txq_ctrl->txq.elts_head = 0;
76 txq_ctrl->txq.elts_tail = 0;
77 txq_ctrl->txq.elts_comp = 0;
79 while (elts_tail != elts_head) {
80 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
83 rte_pktmbuf_free_seg(elt);
86 memset(&(*elts)[elts_tail & elts_m],
88 sizeof((*elts)[elts_tail & elts_m]));
95 * Returns the per-port supported offloads.
98 * Pointer to Ethernet device.
101 * Supported Tx offloads.
104 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
106 struct mlx5_priv *priv = dev->data->dev_private;
107 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
108 DEV_TX_OFFLOAD_VLAN_INSERT);
109 struct mlx5_dev_config *config = &priv->config;
112 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
113 DEV_TX_OFFLOAD_UDP_CKSUM |
114 DEV_TX_OFFLOAD_TCP_CKSUM);
116 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
119 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
121 offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
122 DEV_TX_OFFLOAD_UDP_TNL_TSO);
124 if (config->tunnel_en) {
126 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
128 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
129 DEV_TX_OFFLOAD_GRE_TNL_TSO);
131 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
132 if (config->dv_flow_en)
133 offloads |= DEV_TX_OFFLOAD_MATCH_METADATA;
139 * DPDK callback to configure a TX queue.
142 * Pointer to Ethernet device structure.
146 * Number of descriptors to configure in queue.
148 * NUMA socket on which memory must be allocated.
150 * Thresholds parameters.
153 * 0 on success, a negative errno value otherwise and rte_errno is set.
156 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
157 unsigned int socket, const struct rte_eth_txconf *conf)
159 struct mlx5_priv *priv = dev->data->dev_private;
160 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
161 struct mlx5_txq_ctrl *txq_ctrl =
162 container_of(txq, struct mlx5_txq_ctrl, txq);
164 if (desc <= MLX5_TX_COMP_THRESH) {
166 "port %u number of descriptors requested for Tx queue"
167 " %u must be higher than MLX5_TX_COMP_THRESH, using %u"
169 dev->data->port_id, idx, MLX5_TX_COMP_THRESH + 1, desc);
170 desc = MLX5_TX_COMP_THRESH + 1;
172 if (!rte_is_power_of_2(desc)) {
173 desc = 1 << log2above(desc);
175 "port %u increased number of descriptors in Tx queue"
176 " %u to the next power of two (%d)",
177 dev->data->port_id, idx, desc);
179 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors",
180 dev->data->port_id, idx, desc);
181 if (idx >= priv->txqs_n) {
182 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)",
183 dev->data->port_id, idx, priv->txqs_n);
184 rte_errno = EOVERFLOW;
187 if (!mlx5_txq_releasable(dev, idx)) {
189 DRV_LOG(ERR, "port %u unable to release queue index %u",
190 dev->data->port_id, idx);
193 mlx5_txq_release(dev, idx);
194 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
196 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
197 dev->data->port_id, idx);
200 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
201 dev->data->port_id, idx);
202 (*priv->txqs)[idx] = &txq_ctrl->txq;
207 * DPDK callback to release a TX queue.
210 * Generic TX queue pointer.
213 mlx5_tx_queue_release(void *dpdk_txq)
215 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
216 struct mlx5_txq_ctrl *txq_ctrl;
217 struct mlx5_priv *priv;
222 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
223 priv = txq_ctrl->priv;
224 for (i = 0; (i != priv->txqs_n); ++i)
225 if ((*priv->txqs)[i] == txq) {
226 mlx5_txq_release(ETH_DEV(priv), i);
227 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
228 PORT_ID(priv), txq->idx);
234 * Initialize Tx UAR registers for primary process.
237 * Pointer to Tx queue control structure.
240 txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
242 struct mlx5_priv *priv = txq_ctrl->priv;
243 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
245 unsigned int lock_idx;
246 const size_t page_size = sysconf(_SC_PAGESIZE);
249 assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
251 ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
253 /* Assign an UAR lock according to UAR page number */
254 lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
255 MLX5_UAR_PAGE_NUM_MASK;
256 txq_ctrl->txq.uar_lock = &priv->uar_lock[lock_idx];
261 * Remap UAR register of a Tx queue for secondary process.
263 * Remapped address is stored at the table in the process private structure of
264 * the device, indexed by queue index.
267 * Pointer to Tx queue control structure.
269 * Verbs file descriptor to map UAR pages.
272 * 0 on success, a negative errno value otherwise and rte_errno is set.
275 txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)
277 struct mlx5_priv *priv = txq_ctrl->priv;
278 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
279 struct mlx5_txq_data *txq = &txq_ctrl->txq;
283 const size_t page_size = sysconf(_SC_PAGESIZE);
287 * As rdma-core, UARs are mapped in size of OS page
288 * size. Ref to libmlx5 function: mlx5_init_context()
290 uar_va = (uintptr_t)txq_ctrl->bf_reg;
291 offset = uar_va & (page_size - 1); /* Offset in page. */
292 addr = mmap(NULL, page_size, PROT_WRITE, MAP_SHARED, fd,
293 txq_ctrl->uar_mmap_offset);
294 if (addr == MAP_FAILED) {
296 "port %u mmap failed for BF reg of txq %u",
297 txq->port_id, txq->idx);
301 addr = RTE_PTR_ADD(addr, offset);
302 ppriv->uar_table[txq->idx] = addr;
307 * Unmap UAR register of a Tx queue for secondary process.
310 * Pointer to Tx queue control structure.
313 txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl)
315 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(txq_ctrl->priv));
316 const size_t page_size = sysconf(_SC_PAGESIZE);
319 addr = ppriv->uar_table[txq_ctrl->txq.idx];
320 munmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
324 * Initialize Tx UAR registers for secondary process.
327 * Pointer to Ethernet device.
329 * Verbs file descriptor to map UAR pages.
332 * 0 on success, a negative errno value otherwise and rte_errno is set.
335 mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd)
337 struct mlx5_priv *priv = dev->data->dev_private;
338 struct mlx5_txq_data *txq;
339 struct mlx5_txq_ctrl *txq_ctrl;
343 assert(rte_eal_process_type() == RTE_PROC_SECONDARY);
344 for (i = 0; i != priv->txqs_n; ++i) {
345 if (!(*priv->txqs)[i])
347 txq = (*priv->txqs)[i];
348 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
349 assert(txq->idx == (uint16_t)i);
350 ret = txq_uar_init_secondary(txq_ctrl, fd);
358 if (!(*priv->txqs)[i])
360 txq = (*priv->txqs)[i];
361 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
362 txq_uar_uninit_secondary(txq_ctrl);
368 * Check if the burst function is using eMPW.
370 * @param tx_pkt_burst
371 * Tx burst function pointer.
374 * 1 if the burst function is using eMPW, 0 otherwise.
377 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst)
379 if (tx_pkt_burst == mlx5_tx_burst_raw_vec ||
380 tx_pkt_burst == mlx5_tx_burst_vec ||
381 tx_pkt_burst == mlx5_tx_burst_empw)
387 * Create the Tx queue Verbs object.
390 * Pointer to Ethernet device.
392 * Queue index in DPDK Tx queue array.
395 * The Verbs object initialised, NULL otherwise and rte_errno is set.
397 struct mlx5_txq_ibv *
398 mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
400 struct mlx5_priv *priv = dev->data->dev_private;
401 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
402 struct mlx5_txq_ctrl *txq_ctrl =
403 container_of(txq_data, struct mlx5_txq_ctrl, txq);
404 struct mlx5_txq_ibv tmpl;
405 struct mlx5_txq_ibv *txq_ibv = NULL;
407 struct ibv_qp_init_attr_ex init;
408 struct ibv_cq_init_attr_ex cq;
409 struct ibv_qp_attr mod;
410 struct ibv_cq_ex cq_attr;
413 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
414 struct mlx5dv_cq cq_info;
415 struct mlx5dv_obj obj;
416 const int desc = 1 << txq_data->elts_n;
417 eth_tx_burst_t tx_pkt_burst = mlx5_select_tx_function(dev);
421 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
422 priv->verbs_alloc_ctx.obj = txq_ctrl;
423 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
425 "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set",
430 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));
431 attr.cq = (struct ibv_cq_init_attr_ex){
434 cqe_n = desc / MLX5_TX_COMP_THRESH + 1;
435 if (is_empw_burst_func(tx_pkt_burst))
436 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
437 tmpl.cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);
438 if (tmpl.cq == NULL) {
439 DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
440 dev->data->port_id, idx);
444 attr.init = (struct ibv_qp_init_attr_ex){
445 /* CQ to be associated with the send queue. */
447 /* CQ to be associated with the receive queue. */
450 /* Max number of outstanding WRs. */
452 ((priv->sh->device_attr.orig_attr.max_qp_wr <
454 priv->sh->device_attr.orig_attr.max_qp_wr :
457 * Max number of scatter/gather elements in a WR,
458 * must be 1 to prevent libmlx5 from trying to affect
459 * too much memory. TX gather is not impacted by the
460 * device_attr.max_sge limit and will still work
465 .qp_type = IBV_QPT_RAW_PACKET,
467 * Do *NOT* enable this, completions events are managed per
472 .comp_mask = IBV_QP_INIT_ATTR_PD,
474 if (txq_data->max_inline)
475 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
476 if (txq_data->tso_en) {
477 attr.init.max_tso_header = txq_ctrl->max_tso_header;
478 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
480 tmpl.qp = mlx5_glue->create_qp_ex(priv->sh->ctx, &attr.init);
481 if (tmpl.qp == NULL) {
482 DRV_LOG(ERR, "port %u Tx queue %u QP creation failure",
483 dev->data->port_id, idx);
487 attr.mod = (struct ibv_qp_attr){
488 /* Move the QP to this state. */
489 .qp_state = IBV_QPS_INIT,
490 /* IB device port number. */
491 .port_num = (uint8_t)priv->ibv_port,
493 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
494 (IBV_QP_STATE | IBV_QP_PORT));
497 "port %u Tx queue %u QP state to IBV_QPS_INIT failed",
498 dev->data->port_id, idx);
502 attr.mod = (struct ibv_qp_attr){
503 .qp_state = IBV_QPS_RTR
505 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
508 "port %u Tx queue %u QP state to IBV_QPS_RTR failed",
509 dev->data->port_id, idx);
513 attr.mod.qp_state = IBV_QPS_RTS;
514 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
517 "port %u Tx queue %u QP state to IBV_QPS_RTS failed",
518 dev->data->port_id, idx);
522 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,
525 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory",
526 dev->data->port_id, idx);
531 obj.cq.out = &cq_info;
534 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
539 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
541 "port %u wrong MLX5_CQE_SIZE environment variable"
542 " value: it should be set to %u",
543 dev->data->port_id, RTE_CACHE_LINE_SIZE);
547 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
548 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
549 txq_data->wqes = qp.sq.buf;
550 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
551 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
552 txq_data->cq_db = cq_info.dbrec;
554 (volatile struct mlx5_cqe (*)[])
555 (uintptr_t)cq_info.buf;
560 txq_data->wqe_ci = 0;
561 txq_data->wqe_pi = 0;
562 txq_ibv->qp = tmpl.qp;
563 txq_ibv->cq = tmpl.cq;
564 rte_atomic32_inc(&txq_ibv->refcnt);
565 txq_ctrl->bf_reg = qp.bf.reg;
566 txq_ctrl->cqn = cq_info.cqn;
567 txq_uar_init(txq_ctrl);
568 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
569 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
570 DRV_LOG(DEBUG, "port %u: uar_mmap_offset 0x%"PRIx64,
571 dev->data->port_id, txq_ctrl->uar_mmap_offset);
574 "port %u failed to retrieve UAR info, invalid"
580 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
581 txq_ibv->txq_ctrl = txq_ctrl;
582 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
585 ret = rte_errno; /* Save rte_errno before cleanup. */
587 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
589 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
592 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
593 rte_errno = ret; /* Restore rte_errno. */
598 * Get an Tx queue Verbs object.
601 * Pointer to Ethernet device.
603 * Queue index in DPDK Tx queue array.
606 * The Verbs object if it exists.
608 struct mlx5_txq_ibv *
609 mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
611 struct mlx5_priv *priv = dev->data->dev_private;
612 struct mlx5_txq_ctrl *txq_ctrl;
614 if (idx >= priv->txqs_n)
616 if (!(*priv->txqs)[idx])
618 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
620 rte_atomic32_inc(&txq_ctrl->ibv->refcnt);
621 return txq_ctrl->ibv;
625 * Release an Tx verbs queue object.
628 * Verbs Tx queue object.
631 * 1 while a reference on it exists, 0 when freed.
634 mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv)
637 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {
638 claim_zero(mlx5_glue->destroy_qp(txq_ibv->qp));
639 claim_zero(mlx5_glue->destroy_cq(txq_ibv->cq));
640 LIST_REMOVE(txq_ibv, next);
648 * Verify the Verbs Tx queue list is empty
651 * Pointer to Ethernet device.
654 * The number of object not released.
657 mlx5_txq_ibv_verify(struct rte_eth_dev *dev)
659 struct mlx5_priv *priv = dev->data->dev_private;
661 struct mlx5_txq_ibv *txq_ibv;
663 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) {
664 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced",
665 dev->data->port_id, txq_ibv->txq_ctrl->txq.idx);
672 * Calcuate the total number of WQEBB for Tx queue.
674 * Simplified version of calc_sq_size() in rdma-core.
677 * Pointer to Tx queue control structure.
680 * The number of WQEBB.
683 txq_calc_wqebb_cnt(struct mlx5_txq_ctrl *txq_ctrl)
685 unsigned int wqe_size;
686 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
688 wqe_size = MLX5_WQE_SIZE + txq_ctrl->max_inline_data;
689 return rte_align32pow2(wqe_size * desc) / MLX5_WQE_SIZE;
693 * Set Tx queue parameters from device configuration.
696 * Pointer to Tx queue control structure.
699 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
701 struct mlx5_priv *priv = txq_ctrl->priv;
702 struct mlx5_dev_config *config = &priv->config;
703 const unsigned int max_tso_inline =
704 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) /
705 RTE_CACHE_LINE_SIZE);
706 unsigned int txq_inline;
707 unsigned int txqs_inline;
708 unsigned int inline_max_packet_sz;
709 eth_tx_burst_t tx_pkt_burst =
710 mlx5_select_tx_function(ETH_DEV(priv));
711 int is_empw_func = is_empw_burst_func(tx_pkt_burst);
712 int tso = !!(txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO |
713 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
714 DEV_TX_OFFLOAD_GRE_TNL_TSO |
715 DEV_TX_OFFLOAD_IP_TNL_TSO |
716 DEV_TX_OFFLOAD_UDP_TNL_TSO));
718 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ?
719 0 : config->txq_inline;
720 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ?
721 0 : config->txqs_inline;
722 inline_max_packet_sz =
723 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ?
724 0 : config->inline_max_packet_sz;
726 if (config->txq_inline == MLX5_ARG_UNSET)
727 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;
728 if (config->txqs_inline == MLX5_ARG_UNSET)
729 txqs_inline = MLX5_EMPW_MIN_TXQS;
730 if (config->inline_max_packet_sz == MLX5_ARG_UNSET)
731 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN;
732 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg;
733 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz;
735 if (txq_inline && priv->txqs_n >= txqs_inline) {
738 txq_ctrl->txq.max_inline =
739 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
740 RTE_CACHE_LINE_SIZE);
742 /* To minimize the size of data set, avoid requesting
745 txq_ctrl->max_inline_data =
746 ((RTE_MIN(txq_inline,
747 inline_max_packet_sz) +
748 (RTE_CACHE_LINE_SIZE - 1)) /
749 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
751 txq_ctrl->max_inline_data =
752 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE;
755 * Check if the inline size is too large in a way which
756 * can make the WQE DS to overflow.
757 * Considering in calculation:
762 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE);
763 if (ds_cnt > MLX5_DSEG_MAX) {
764 unsigned int max_inline = (MLX5_DSEG_MAX - 2) *
767 max_inline = max_inline - (max_inline %
768 RTE_CACHE_LINE_SIZE);
770 "port %u txq inline is too large (%d) setting"
771 " it to the maximum possible: %d\n",
772 PORT_ID(priv), txq_inline, max_inline);
773 txq_ctrl->txq.max_inline = max_inline /
778 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE;
779 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline,
781 txq_ctrl->txq.tso_en = 1;
783 txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
784 txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
785 DEV_TX_OFFLOAD_UDP_TNL_TSO |
786 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
787 txq_ctrl->txq.offloads) && config->swp;
791 * Create a DPDK Tx queue.
794 * Pointer to Ethernet device.
798 * Number of descriptors to configure in queue.
800 * NUMA socket on which memory must be allocated.
802 * Thresholds parameters.
805 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
807 struct mlx5_txq_ctrl *
808 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
809 unsigned int socket, const struct rte_eth_txconf *conf)
811 struct mlx5_priv *priv = dev->data->dev_private;
812 struct mlx5_txq_ctrl *tmpl;
814 tmpl = rte_calloc_socket("TXQ", 1,
816 desc * sizeof(struct rte_mbuf *),
822 if (mlx5_mr_btree_init(&tmpl->txq.mr_ctrl.cache_bh,
823 MLX5_MR_BTREE_CACHE_N, socket)) {
824 /* rte_errno is already set. */
827 /* Save pointer of global generation number to check memory event. */
828 tmpl->txq.mr_ctrl.dev_gen_ptr = &priv->sh->mr.dev_gen;
829 assert(desc > MLX5_TX_COMP_THRESH);
830 tmpl->txq.offloads = conf->offloads |
831 dev->data->dev_conf.txmode.offloads;
833 tmpl->socket = socket;
834 tmpl->txq.elts_n = log2above(desc);
835 tmpl->txq.port_id = dev->data->port_id;
837 txq_set_params(tmpl);
838 if (txq_calc_wqebb_cnt(tmpl) >
839 priv->sh->device_attr.orig_attr.max_qp_wr) {
841 "port %u Tx WQEBB count (%d) exceeds the limit (%d),"
842 " try smaller queue size",
843 dev->data->port_id, txq_calc_wqebb_cnt(tmpl),
844 priv->sh->device_attr.orig_attr.max_qp_wr);
849 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1);
850 rte_atomic32_inc(&tmpl->refcnt);
851 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
862 * Pointer to Ethernet device.
867 * A pointer to the queue if it exists.
869 struct mlx5_txq_ctrl *
870 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
872 struct mlx5_priv *priv = dev->data->dev_private;
873 struct mlx5_txq_ctrl *ctrl = NULL;
875 if ((*priv->txqs)[idx]) {
876 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
878 mlx5_txq_ibv_get(dev, idx);
879 rte_atomic32_inc(&ctrl->refcnt);
885 * Release a Tx queue.
888 * Pointer to Ethernet device.
893 * 1 while a reference on it exists, 0 when freed.
896 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
898 struct mlx5_priv *priv = dev->data->dev_private;
899 struct mlx5_txq_ctrl *txq;
901 if (!(*priv->txqs)[idx])
903 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
904 if (txq->ibv && !mlx5_txq_ibv_release(txq->ibv))
906 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
908 mlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh);
909 LIST_REMOVE(txq, next);
911 (*priv->txqs)[idx] = NULL;
918 * Verify if the queue can be released.
921 * Pointer to Ethernet device.
926 * 1 if the queue can be released.
929 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
931 struct mlx5_priv *priv = dev->data->dev_private;
932 struct mlx5_txq_ctrl *txq;
934 if (!(*priv->txqs)[idx])
936 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
937 return (rte_atomic32_read(&txq->refcnt) == 1);
941 * Verify the Tx Queue list is empty
944 * Pointer to Ethernet device.
947 * The number of object not released.
950 mlx5_txq_verify(struct rte_eth_dev *dev)
952 struct mlx5_priv *priv = dev->data->dev_private;
953 struct mlx5_txq_ctrl *txq_ctrl;
956 LIST_FOREACH(txq_ctrl, &priv->txqsctrl, next) {
957 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced",
958 dev->data->port_id, txq_ctrl->txq.idx);