1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
18 #pragma GCC diagnostic ignored "-Wpedantic"
20 #include <infiniband/verbs.h>
21 #include <infiniband/mlx5dv.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_malloc.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_common.h>
31 #include <mlx5_glue.h>
32 #include <mlx5_devx_cmds.h>
33 #include <mlx5_common.h>
35 #include "mlx5_defs.h"
36 #include "mlx5_utils.h"
38 #include "mlx5_rxtx.h"
39 #include "mlx5_autoconf.h"
42 * Allocate TX queue elements.
45 * Pointer to TX queue structure.
48 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
50 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
53 for (i = 0; (i != elts_n); ++i)
54 txq_ctrl->txq.elts[i] = NULL;
55 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
56 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx, elts_n);
57 txq_ctrl->txq.elts_head = 0;
58 txq_ctrl->txq.elts_tail = 0;
59 txq_ctrl->txq.elts_comp = 0;
63 * Free TX queue elements.
66 * Pointer to TX queue structure.
69 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
71 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
72 const uint16_t elts_m = elts_n - 1;
73 uint16_t elts_head = txq_ctrl->txq.elts_head;
74 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
75 struct rte_mbuf *(*elts)[elts_n] = &txq_ctrl->txq.elts;
77 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs",
78 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx);
79 txq_ctrl->txq.elts_head = 0;
80 txq_ctrl->txq.elts_tail = 0;
81 txq_ctrl->txq.elts_comp = 0;
83 while (elts_tail != elts_head) {
84 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
87 rte_pktmbuf_free_seg(elt);
90 memset(&(*elts)[elts_tail & elts_m],
92 sizeof((*elts)[elts_tail & elts_m]));
99 * Returns the per-port supported offloads.
102 * Pointer to Ethernet device.
105 * Supported Tx offloads.
108 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
110 struct mlx5_priv *priv = dev->data->dev_private;
111 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
112 DEV_TX_OFFLOAD_VLAN_INSERT);
113 struct mlx5_dev_config *config = &priv->config;
116 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
117 DEV_TX_OFFLOAD_UDP_CKSUM |
118 DEV_TX_OFFLOAD_TCP_CKSUM);
120 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
123 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
125 offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
126 DEV_TX_OFFLOAD_UDP_TNL_TSO);
128 if (config->tunnel_en) {
130 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
132 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
133 DEV_TX_OFFLOAD_GRE_TNL_TSO |
134 DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
140 * Tx queue presetup checks.
143 * Pointer to Ethernet device structure.
147 * Number of descriptors to configure in queue.
150 * 0 on success, a negative errno value otherwise and rte_errno is set.
153 mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc)
155 struct mlx5_priv *priv = dev->data->dev_private;
157 if (desc <= MLX5_TX_COMP_THRESH) {
159 "port %u number of descriptors requested for Tx queue"
160 " %u must be higher than MLX5_TX_COMP_THRESH, using %u"
162 dev->data->port_id, idx, MLX5_TX_COMP_THRESH + 1, desc);
163 desc = MLX5_TX_COMP_THRESH + 1;
165 if (!rte_is_power_of_2(desc)) {
166 desc = 1 << log2above(desc);
168 "port %u increased number of descriptors in Tx queue"
169 " %u to the next power of two (%d)",
170 dev->data->port_id, idx, desc);
172 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors",
173 dev->data->port_id, idx, desc);
174 if (idx >= priv->txqs_n) {
175 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)",
176 dev->data->port_id, idx, priv->txqs_n);
177 rte_errno = EOVERFLOW;
180 if (!mlx5_txq_releasable(dev, idx)) {
182 DRV_LOG(ERR, "port %u unable to release queue index %u",
183 dev->data->port_id, idx);
186 mlx5_txq_release(dev, idx);
190 * DPDK callback to configure a TX queue.
193 * Pointer to Ethernet device structure.
197 * Number of descriptors to configure in queue.
199 * NUMA socket on which memory must be allocated.
201 * Thresholds parameters.
204 * 0 on success, a negative errno value otherwise and rte_errno is set.
207 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
208 unsigned int socket, const struct rte_eth_txconf *conf)
210 struct mlx5_priv *priv = dev->data->dev_private;
211 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
212 struct mlx5_txq_ctrl *txq_ctrl =
213 container_of(txq, struct mlx5_txq_ctrl, txq);
216 res = mlx5_tx_queue_pre_setup(dev, idx, desc);
219 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
221 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
222 dev->data->port_id, idx);
225 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
226 dev->data->port_id, idx);
227 (*priv->txqs)[idx] = &txq_ctrl->txq;
232 * DPDK callback to configure a TX hairpin queue.
235 * Pointer to Ethernet device structure.
239 * Number of descriptors to configure in queue.
240 * @param[in] hairpin_conf
241 * The hairpin binding configuration.
244 * 0 on success, a negative errno value otherwise and rte_errno is set.
247 mlx5_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
249 const struct rte_eth_hairpin_conf *hairpin_conf)
251 struct mlx5_priv *priv = dev->data->dev_private;
252 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
253 struct mlx5_txq_ctrl *txq_ctrl =
254 container_of(txq, struct mlx5_txq_ctrl, txq);
257 res = mlx5_tx_queue_pre_setup(dev, idx, desc);
260 if (hairpin_conf->peer_count != 1 ||
261 hairpin_conf->peers[0].port != dev->data->port_id ||
262 hairpin_conf->peers[0].queue >= priv->rxqs_n) {
263 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
264 " invalid hairpind configuration", dev->data->port_id,
269 txq_ctrl = mlx5_txq_hairpin_new(dev, idx, desc, hairpin_conf);
271 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
272 dev->data->port_id, idx);
275 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
276 dev->data->port_id, idx);
277 (*priv->txqs)[idx] = &txq_ctrl->txq;
282 * DPDK callback to release a TX queue.
285 * Generic TX queue pointer.
288 mlx5_tx_queue_release(void *dpdk_txq)
290 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
291 struct mlx5_txq_ctrl *txq_ctrl;
292 struct mlx5_priv *priv;
297 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
298 priv = txq_ctrl->priv;
299 for (i = 0; (i != priv->txqs_n); ++i)
300 if ((*priv->txqs)[i] == txq) {
301 mlx5_txq_release(ETH_DEV(priv), i);
302 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
303 PORT_ID(priv), txq->idx);
309 * Configure the doorbell register non-cached attribute.
312 * Pointer to Tx queue control structure.
317 txq_uar_ncattr_init(struct mlx5_txq_ctrl *txq_ctrl, size_t page_size)
319 struct mlx5_priv *priv = txq_ctrl->priv;
322 txq_ctrl->txq.db_heu = priv->config.dbnc == MLX5_TXDB_HEURISTIC;
323 txq_ctrl->txq.db_nc = 0;
324 /* Check the doorbell register mapping type. */
325 cmd = txq_ctrl->uar_mmap_offset / page_size;
326 cmd >>= MLX5_UAR_MMAP_CMD_SHIFT;
327 cmd &= MLX5_UAR_MMAP_CMD_MASK;
328 if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD)
329 txq_ctrl->txq.db_nc = 1;
333 * Initialize Tx UAR registers for primary process.
336 * Pointer to Tx queue control structure.
339 txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
341 struct mlx5_priv *priv = txq_ctrl->priv;
342 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
343 const size_t page_size = sysconf(_SC_PAGESIZE);
345 unsigned int lock_idx;
348 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
350 assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
352 ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
353 txq_uar_ncattr_init(txq_ctrl, page_size);
355 /* Assign an UAR lock according to UAR page number */
356 lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
357 MLX5_UAR_PAGE_NUM_MASK;
358 txq_ctrl->txq.uar_lock = &priv->uar_lock[lock_idx];
363 * Remap UAR register of a Tx queue for secondary process.
365 * Remapped address is stored at the table in the process private structure of
366 * the device, indexed by queue index.
369 * Pointer to Tx queue control structure.
371 * Verbs file descriptor to map UAR pages.
374 * 0 on success, a negative errno value otherwise and rte_errno is set.
377 txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)
379 struct mlx5_priv *priv = txq_ctrl->priv;
380 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
381 struct mlx5_txq_data *txq = &txq_ctrl->txq;
385 const size_t page_size = sysconf(_SC_PAGESIZE);
387 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
391 * As rdma-core, UARs are mapped in size of OS page
392 * size. Ref to libmlx5 function: mlx5_init_context()
394 uar_va = (uintptr_t)txq_ctrl->bf_reg;
395 offset = uar_va & (page_size - 1); /* Offset in page. */
396 addr = mmap(NULL, page_size, PROT_WRITE, MAP_SHARED, fd,
397 txq_ctrl->uar_mmap_offset);
398 if (addr == MAP_FAILED) {
400 "port %u mmap failed for BF reg of txq %u",
401 txq->port_id, txq->idx);
405 addr = RTE_PTR_ADD(addr, offset);
406 ppriv->uar_table[txq->idx] = addr;
407 txq_uar_ncattr_init(txq_ctrl, page_size);
412 * Unmap UAR register of a Tx queue for secondary process.
415 * Pointer to Tx queue control structure.
418 txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl)
420 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(txq_ctrl->priv));
421 const size_t page_size = sysconf(_SC_PAGESIZE);
424 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
426 addr = ppriv->uar_table[txq_ctrl->txq.idx];
427 munmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
431 * Initialize Tx UAR registers for secondary process.
434 * Pointer to Ethernet device.
436 * Verbs file descriptor to map UAR pages.
439 * 0 on success, a negative errno value otherwise and rte_errno is set.
442 mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd)
444 struct mlx5_priv *priv = dev->data->dev_private;
445 struct mlx5_txq_data *txq;
446 struct mlx5_txq_ctrl *txq_ctrl;
450 assert(rte_eal_process_type() == RTE_PROC_SECONDARY);
451 for (i = 0; i != priv->txqs_n; ++i) {
452 if (!(*priv->txqs)[i])
454 txq = (*priv->txqs)[i];
455 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
456 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
458 assert(txq->idx == (uint16_t)i);
459 ret = txq_uar_init_secondary(txq_ctrl, fd);
467 if (!(*priv->txqs)[i])
469 txq = (*priv->txqs)[i];
470 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
471 txq_uar_uninit_secondary(txq_ctrl);
477 * Create the Tx hairpin queue object.
480 * Pointer to Ethernet device.
482 * Queue index in DPDK Tx queue array
485 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
487 static struct mlx5_txq_obj *
488 mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
490 struct mlx5_priv *priv = dev->data->dev_private;
491 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
492 struct mlx5_txq_ctrl *txq_ctrl =
493 container_of(txq_data, struct mlx5_txq_ctrl, txq);
494 struct mlx5_devx_create_sq_attr attr = { 0 };
495 struct mlx5_txq_obj *tmpl = NULL;
499 assert(!txq_ctrl->obj);
500 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
504 "port %u Tx queue %u cannot allocate memory resources",
505 dev->data->port_id, txq_data->idx);
509 tmpl->type = MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN;
510 tmpl->txq_ctrl = txq_ctrl;
513 /* Workaround for hairpin startup */
514 attr.wq_attr.log_hairpin_num_packets = log2above(32);
515 /* Workaround for packets larger than 1KB */
516 attr.wq_attr.log_hairpin_data_sz =
517 priv->config.hca_attr.log_max_hairpin_wq_data_sz;
518 attr.tis_num = priv->sh->tis->id;
519 tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->ctx, &attr);
522 "port %u tx hairpin queue %u can't create sq object",
523 dev->data->port_id, idx);
527 DRV_LOG(DEBUG, "port %u sxq %u updated with %p", dev->data->port_id,
529 rte_atomic32_inc(&tmpl->refcnt);
530 LIST_INSERT_HEAD(&priv->txqsobj, tmpl, next);
533 ret = rte_errno; /* Save rte_errno before cleanup. */
535 mlx5_devx_cmd_destroy(tmpl->tis);
537 mlx5_devx_cmd_destroy(tmpl->sq);
538 rte_errno = ret; /* Restore rte_errno. */
543 * Create the Tx queue Verbs object.
546 * Pointer to Ethernet device.
548 * Queue index in DPDK Tx queue array.
550 * Type of the Tx queue object to create.
553 * The Verbs object initialised, NULL otherwise and rte_errno is set.
555 struct mlx5_txq_obj *
556 mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
557 enum mlx5_txq_obj_type type)
559 struct mlx5_priv *priv = dev->data->dev_private;
560 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
561 struct mlx5_txq_ctrl *txq_ctrl =
562 container_of(txq_data, struct mlx5_txq_ctrl, txq);
563 struct mlx5_txq_obj tmpl;
564 struct mlx5_txq_obj *txq_obj = NULL;
566 struct ibv_qp_init_attr_ex init;
567 struct ibv_cq_init_attr_ex cq;
568 struct ibv_qp_attr mod;
571 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
572 struct mlx5dv_cq cq_info;
573 struct mlx5dv_obj obj;
574 const int desc = 1 << txq_data->elts_n;
577 if (type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN)
578 return mlx5_txq_obj_hairpin_new(dev, idx);
579 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
580 /* If using DevX, need additional mask to read tisn value. */
581 if (priv->config.devx && !priv->sh->tdn)
582 qp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;
585 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
586 priv->verbs_alloc_ctx.obj = txq_ctrl;
587 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
589 "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set",
594 memset(&tmpl, 0, sizeof(struct mlx5_txq_obj));
595 attr.cq = (struct ibv_cq_init_attr_ex){
598 cqe_n = desc / MLX5_TX_COMP_THRESH +
599 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
600 tmpl.cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);
601 if (tmpl.cq == NULL) {
602 DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
603 dev->data->port_id, idx);
607 attr.init = (struct ibv_qp_init_attr_ex){
608 /* CQ to be associated with the send queue. */
610 /* CQ to be associated with the receive queue. */
613 /* Max number of outstanding WRs. */
615 ((priv->sh->device_attr.orig_attr.max_qp_wr <
617 priv->sh->device_attr.orig_attr.max_qp_wr :
620 * Max number of scatter/gather elements in a WR,
621 * must be 1 to prevent libmlx5 from trying to affect
622 * too much memory. TX gather is not impacted by the
623 * device_attr.max_sge limit and will still work
628 .qp_type = IBV_QPT_RAW_PACKET,
630 * Do *NOT* enable this, completions events are managed per
635 .comp_mask = IBV_QP_INIT_ATTR_PD,
637 if (txq_data->inlen_send)
638 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
639 if (txq_data->tso_en) {
640 attr.init.max_tso_header = txq_ctrl->max_tso_header;
641 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
643 tmpl.qp = mlx5_glue->create_qp_ex(priv->sh->ctx, &attr.init);
644 if (tmpl.qp == NULL) {
645 DRV_LOG(ERR, "port %u Tx queue %u QP creation failure",
646 dev->data->port_id, idx);
650 attr.mod = (struct ibv_qp_attr){
651 /* Move the QP to this state. */
652 .qp_state = IBV_QPS_INIT,
653 /* IB device port number. */
654 .port_num = (uint8_t)priv->ibv_port,
656 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
657 (IBV_QP_STATE | IBV_QP_PORT));
660 "port %u Tx queue %u QP state to IBV_QPS_INIT failed",
661 dev->data->port_id, idx);
665 attr.mod = (struct ibv_qp_attr){
666 .qp_state = IBV_QPS_RTR
668 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
671 "port %u Tx queue %u QP state to IBV_QPS_RTR failed",
672 dev->data->port_id, idx);
676 attr.mod.qp_state = IBV_QPS_RTS;
677 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
680 "port %u Tx queue %u QP state to IBV_QPS_RTS failed",
681 dev->data->port_id, idx);
685 txq_obj = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_obj), 0,
688 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory",
689 dev->data->port_id, idx);
694 obj.cq.out = &cq_info;
697 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
702 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
704 "port %u wrong MLX5_CQE_SIZE environment variable"
705 " value: it should be set to %u",
706 dev->data->port_id, RTE_CACHE_LINE_SIZE);
710 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
711 txq_data->cqe_s = 1 << txq_data->cqe_n;
712 txq_data->cqe_m = txq_data->cqe_s - 1;
713 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
714 txq_data->wqes = qp.sq.buf;
715 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
716 txq_data->wqe_s = 1 << txq_data->wqe_n;
717 txq_data->wqe_m = txq_data->wqe_s - 1;
718 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
719 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
720 txq_data->cq_db = cq_info.dbrec;
721 txq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf;
724 txq_data->wqe_ci = 0;
725 txq_data->wqe_pi = 0;
726 txq_data->wqe_comp = 0;
727 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
728 txq_data->fcqs = rte_calloc_socket(__func__,
730 sizeof(*txq_data->fcqs),
733 if (!txq_data->fcqs) {
734 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory (FCQ)",
735 dev->data->port_id, idx);
739 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
741 * If using DevX need to query and store TIS transport domain value.
742 * This is done once per port.
743 * Will use this value on Rx, when creating matching TIR.
745 if (priv->config.devx && !priv->sh->tdn) {
746 ret = mlx5_devx_cmd_qp_query_tis_td(tmpl.qp, qp.tisn,
749 DRV_LOG(ERR, "Fail to query port %u Tx queue %u QP TIS "
750 "transport domain", dev->data->port_id, idx);
754 DRV_LOG(DEBUG, "port %u Tx queue %u TIS number %d "
755 "transport domain %d", dev->data->port_id,
756 idx, qp.tisn, priv->sh->tdn);
760 txq_obj->qp = tmpl.qp;
761 txq_obj->cq = tmpl.cq;
762 rte_atomic32_inc(&txq_obj->refcnt);
763 txq_ctrl->bf_reg = qp.bf.reg;
764 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
765 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
766 DRV_LOG(DEBUG, "port %u: uar_mmap_offset 0x%"PRIx64,
767 dev->data->port_id, txq_ctrl->uar_mmap_offset);
770 "port %u failed to retrieve UAR info, invalid"
776 txq_uar_init(txq_ctrl);
777 LIST_INSERT_HEAD(&priv->txqsobj, txq_obj, next);
778 txq_obj->txq_ctrl = txq_ctrl;
779 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
782 ret = rte_errno; /* Save rte_errno before cleanup. */
784 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
786 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
787 if (txq_data && txq_data->fcqs)
788 rte_free(txq_data->fcqs);
791 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
792 rte_errno = ret; /* Restore rte_errno. */
797 * Get an Tx queue Verbs object.
800 * Pointer to Ethernet device.
802 * Queue index in DPDK Tx queue array.
805 * The Verbs object if it exists.
807 struct mlx5_txq_obj *
808 mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
810 struct mlx5_priv *priv = dev->data->dev_private;
811 struct mlx5_txq_ctrl *txq_ctrl;
813 if (idx >= priv->txqs_n)
815 if (!(*priv->txqs)[idx])
817 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
819 rte_atomic32_inc(&txq_ctrl->obj->refcnt);
820 return txq_ctrl->obj;
824 * Release an Tx verbs queue object.
827 * Verbs Tx queue object.
830 * 1 while a reference on it exists, 0 when freed.
833 mlx5_txq_obj_release(struct mlx5_txq_obj *txq_obj)
836 if (rte_atomic32_dec_and_test(&txq_obj->refcnt)) {
837 if (txq_obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN) {
839 claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));
841 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
842 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
843 if (txq_obj->txq_ctrl->txq.fcqs)
844 rte_free(txq_obj->txq_ctrl->txq.fcqs);
846 LIST_REMOVE(txq_obj, next);
854 * Verify the Verbs Tx queue list is empty
857 * Pointer to Ethernet device.
860 * The number of object not released.
863 mlx5_txq_obj_verify(struct rte_eth_dev *dev)
865 struct mlx5_priv *priv = dev->data->dev_private;
867 struct mlx5_txq_obj *txq_obj;
869 LIST_FOREACH(txq_obj, &priv->txqsobj, next) {
870 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced",
871 dev->data->port_id, txq_obj->txq_ctrl->txq.idx);
878 * Calculate the total number of WQEBB for Tx queue.
880 * Simplified version of calc_sq_size() in rdma-core.
883 * Pointer to Tx queue control structure.
886 * The number of WQEBB.
889 txq_calc_wqebb_cnt(struct mlx5_txq_ctrl *txq_ctrl)
891 unsigned int wqe_size;
892 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
894 wqe_size = MLX5_WQE_CSEG_SIZE +
897 MLX5_ESEG_MIN_INLINE_SIZE +
898 txq_ctrl->max_inline_data;
899 return rte_align32pow2(wqe_size * desc) / MLX5_WQE_SIZE;
903 * Calculate the maximal inline data size for Tx queue.
906 * Pointer to Tx queue control structure.
909 * The maximal inline data size.
912 txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl)
914 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
915 struct mlx5_priv *priv = txq_ctrl->priv;
916 unsigned int wqe_size;
918 wqe_size = priv->sh->device_attr.orig_attr.max_qp_wr / desc;
922 * This calculation is derived from tthe source of
923 * mlx5_calc_send_wqe() in rdma_core library.
925 wqe_size = wqe_size * MLX5_WQE_SIZE -
930 MLX5_DSEG_MIN_INLINE_SIZE;
935 * Set Tx queue parameters from device configuration.
938 * Pointer to Tx queue control structure.
941 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
943 struct mlx5_priv *priv = txq_ctrl->priv;
944 struct mlx5_dev_config *config = &priv->config;
945 unsigned int inlen_send; /* Inline data for ordinary SEND.*/
946 unsigned int inlen_empw; /* Inline data for enhanced MPW. */
947 unsigned int inlen_mode; /* Minimal required Inline data. */
948 unsigned int txqs_inline; /* Min Tx queues to enable inline. */
949 uint64_t dev_txoff = priv->dev_data->dev_conf.txmode.offloads;
950 bool tso = txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO |
951 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
952 DEV_TX_OFFLOAD_GRE_TNL_TSO |
953 DEV_TX_OFFLOAD_IP_TNL_TSO |
954 DEV_TX_OFFLOAD_UDP_TNL_TSO);
958 if (config->txqs_inline == MLX5_ARG_UNSET)
960 #if defined(RTE_ARCH_ARM64)
961 (priv->pci_dev->id.device_id ==
962 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) ?
963 MLX5_INLINE_MAX_TXQS_BLUEFIELD :
965 MLX5_INLINE_MAX_TXQS;
967 txqs_inline = (unsigned int)config->txqs_inline;
968 inlen_send = (config->txq_inline_max == MLX5_ARG_UNSET) ?
969 MLX5_SEND_DEF_INLINE_LEN :
970 (unsigned int)config->txq_inline_max;
971 inlen_empw = (config->txq_inline_mpw == MLX5_ARG_UNSET) ?
972 MLX5_EMPW_DEF_INLINE_LEN :
973 (unsigned int)config->txq_inline_mpw;
974 inlen_mode = (config->txq_inline_min == MLX5_ARG_UNSET) ?
975 0 : (unsigned int)config->txq_inline_min;
976 if (config->mps != MLX5_MPW_ENHANCED && config->mps != MLX5_MPW)
979 * If there is requested minimal amount of data to inline
980 * we MUST enable inlining. This is a case for ConnectX-4
981 * which usually requires L2 inlined for correct operating
982 * and ConnectX-4LX which requires L2-L4 inlined to
983 * support E-Switch Flows.
986 if (inlen_mode <= MLX5_ESEG_MIN_INLINE_SIZE) {
988 * Optimize minimal inlining for single
989 * segment packets to fill one WQEBB
992 temp = MLX5_ESEG_MIN_INLINE_SIZE;
994 temp = inlen_mode - MLX5_ESEG_MIN_INLINE_SIZE;
995 temp = RTE_ALIGN(temp, MLX5_WSEG_SIZE) +
996 MLX5_ESEG_MIN_INLINE_SIZE;
997 temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN);
999 if (temp != inlen_mode) {
1001 "port %u minimal required inline setting"
1002 " aligned from %u to %u",
1003 PORT_ID(priv), inlen_mode, temp);
1008 * If port is configured to support VLAN insertion and device
1009 * does not support this feature by HW (for NICs before ConnectX-5
1010 * or in case of wqe_vlan_insert flag is not set) we must enable
1011 * data inline on all queues because it is supported by single
1014 txq_ctrl->txq.vlan_en = config->hw_vlan_insert;
1015 vlan_inline = (dev_txoff & DEV_TX_OFFLOAD_VLAN_INSERT) &&
1016 !config->hw_vlan_insert;
1018 * If there are few Tx queues it is prioritized
1019 * to save CPU cycles and disable data inlining at all.
1021 if (inlen_send && priv->txqs_n >= txqs_inline) {
1023 * The data sent with ordinal MLX5_OPCODE_SEND
1024 * may be inlined in Ethernet Segment, align the
1025 * length accordingly to fit entire WQEBBs.
1027 temp = RTE_MAX(inlen_send,
1028 MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE);
1029 temp -= MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE;
1030 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE);
1031 temp += MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE;
1032 temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX +
1033 MLX5_ESEG_MIN_INLINE_SIZE -
1034 MLX5_WQE_CSEG_SIZE -
1035 MLX5_WQE_ESEG_SIZE -
1036 MLX5_WQE_DSEG_SIZE * 2);
1037 temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN);
1038 temp = RTE_MAX(temp, inlen_mode);
1039 if (temp != inlen_send) {
1041 "port %u ordinary send inline setting"
1042 " aligned from %u to %u",
1043 PORT_ID(priv), inlen_send, temp);
1047 * Not aligned to cache lines, but to WQEs.
1048 * First bytes of data (initial alignment)
1049 * is going to be copied explicitly at the
1050 * beginning of inlining buffer in Ethernet
1053 assert(inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
1054 assert(inlen_send <= MLX5_WQE_SIZE_MAX +
1055 MLX5_ESEG_MIN_INLINE_SIZE -
1056 MLX5_WQE_CSEG_SIZE -
1057 MLX5_WQE_ESEG_SIZE -
1058 MLX5_WQE_DSEG_SIZE * 2);
1059 } else if (inlen_mode) {
1061 * If minimal inlining is requested we must
1062 * enable inlining in general, despite the
1063 * number of configured queues. Ignore the
1064 * txq_inline_max devarg, this is not
1065 * full-featured inline.
1067 inlen_send = inlen_mode;
1069 } else if (vlan_inline) {
1071 * Hardware does not report offload for
1072 * VLAN insertion, we must enable data inline
1073 * to implement feature by software.
1075 inlen_send = MLX5_ESEG_MIN_INLINE_SIZE;
1081 txq_ctrl->txq.inlen_send = inlen_send;
1082 txq_ctrl->txq.inlen_mode = inlen_mode;
1083 txq_ctrl->txq.inlen_empw = 0;
1084 if (inlen_send && inlen_empw && priv->txqs_n >= txqs_inline) {
1086 * The data sent with MLX5_OPCODE_ENHANCED_MPSW
1087 * may be inlined in Data Segment, align the
1088 * length accordingly to fit entire WQEBBs.
1090 temp = RTE_MAX(inlen_empw,
1091 MLX5_WQE_SIZE + MLX5_DSEG_MIN_INLINE_SIZE);
1092 temp -= MLX5_DSEG_MIN_INLINE_SIZE;
1093 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE);
1094 temp += MLX5_DSEG_MIN_INLINE_SIZE;
1095 temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX +
1096 MLX5_DSEG_MIN_INLINE_SIZE -
1097 MLX5_WQE_CSEG_SIZE -
1098 MLX5_WQE_ESEG_SIZE -
1099 MLX5_WQE_DSEG_SIZE);
1100 temp = RTE_MIN(temp, MLX5_EMPW_MAX_INLINE_LEN);
1101 if (temp != inlen_empw) {
1103 "port %u enhanced empw inline setting"
1104 " aligned from %u to %u",
1105 PORT_ID(priv), inlen_empw, temp);
1108 assert(inlen_empw >= MLX5_ESEG_MIN_INLINE_SIZE);
1109 assert(inlen_empw <= MLX5_WQE_SIZE_MAX +
1110 MLX5_DSEG_MIN_INLINE_SIZE -
1111 MLX5_WQE_CSEG_SIZE -
1112 MLX5_WQE_ESEG_SIZE -
1113 MLX5_WQE_DSEG_SIZE);
1114 txq_ctrl->txq.inlen_empw = inlen_empw;
1116 txq_ctrl->max_inline_data = RTE_MAX(inlen_send, inlen_empw);
1118 txq_ctrl->max_tso_header = MLX5_MAX_TSO_HEADER;
1119 txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->max_inline_data,
1120 MLX5_MAX_TSO_HEADER);
1121 txq_ctrl->txq.tso_en = 1;
1123 txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
1124 txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
1125 DEV_TX_OFFLOAD_UDP_TNL_TSO |
1126 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
1127 txq_ctrl->txq.offloads) && config->swp;
1131 * Adjust Tx queue data inline parameters for large queue sizes.
1132 * The data inline feature requires multiple WQEs to fit the packets,
1133 * and if the large amount of Tx descriptors is requested by application
1134 * the total WQE amount may exceed the hardware capabilities. If the
1135 * default inline setting are used we can try to adjust these ones and
1136 * meet the hardware requirements and not exceed the queue size.
1139 * Pointer to Tx queue control structure.
1142 * Zero on success, otherwise the parameters can not be adjusted.
1145 txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)
1147 struct mlx5_priv *priv = txq_ctrl->priv;
1148 struct mlx5_dev_config *config = &priv->config;
1149 unsigned int max_inline;
1151 max_inline = txq_calc_inline_max(txq_ctrl);
1152 if (!txq_ctrl->txq.inlen_send) {
1154 * Inline data feature is not engaged at all.
1155 * There is nothing to adjust.
1159 if (txq_ctrl->max_inline_data <= max_inline) {
1161 * The requested inline data length does not
1162 * exceed queue capabilities.
1166 if (txq_ctrl->txq.inlen_mode > max_inline) {
1168 "minimal data inline requirements (%u) are not"
1169 " satisfied (%u) on port %u, try the smaller"
1170 " Tx queue size (%d)",
1171 txq_ctrl->txq.inlen_mode, max_inline,
1172 priv->dev_data->port_id,
1173 priv->sh->device_attr.orig_attr.max_qp_wr);
1176 if (txq_ctrl->txq.inlen_send > max_inline &&
1177 config->txq_inline_max != MLX5_ARG_UNSET &&
1178 config->txq_inline_max > (int)max_inline) {
1180 "txq_inline_max requirements (%u) are not"
1181 " satisfied (%u) on port %u, try the smaller"
1182 " Tx queue size (%d)",
1183 txq_ctrl->txq.inlen_send, max_inline,
1184 priv->dev_data->port_id,
1185 priv->sh->device_attr.orig_attr.max_qp_wr);
1188 if (txq_ctrl->txq.inlen_empw > max_inline &&
1189 config->txq_inline_mpw != MLX5_ARG_UNSET &&
1190 config->txq_inline_mpw > (int)max_inline) {
1192 "txq_inline_mpw requirements (%u) are not"
1193 " satisfied (%u) on port %u, try the smaller"
1194 " Tx queue size (%d)",
1195 txq_ctrl->txq.inlen_empw, max_inline,
1196 priv->dev_data->port_id,
1197 priv->sh->device_attr.orig_attr.max_qp_wr);
1200 if (txq_ctrl->txq.tso_en && max_inline < MLX5_MAX_TSO_HEADER) {
1202 "tso header inline requirements (%u) are not"
1203 " satisfied (%u) on port %u, try the smaller"
1204 " Tx queue size (%d)",
1205 MLX5_MAX_TSO_HEADER, max_inline,
1206 priv->dev_data->port_id,
1207 priv->sh->device_attr.orig_attr.max_qp_wr);
1210 if (txq_ctrl->txq.inlen_send > max_inline) {
1212 "adjust txq_inline_max (%u->%u)"
1213 " due to large Tx queue on port %u",
1214 txq_ctrl->txq.inlen_send, max_inline,
1215 priv->dev_data->port_id);
1216 txq_ctrl->txq.inlen_send = max_inline;
1218 if (txq_ctrl->txq.inlen_empw > max_inline) {
1220 "adjust txq_inline_mpw (%u->%u)"
1221 "due to large Tx queue on port %u",
1222 txq_ctrl->txq.inlen_empw, max_inline,
1223 priv->dev_data->port_id);
1224 txq_ctrl->txq.inlen_empw = max_inline;
1226 txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->txq.inlen_send,
1227 txq_ctrl->txq.inlen_empw);
1228 assert(txq_ctrl->max_inline_data <= max_inline);
1229 assert(txq_ctrl->txq.inlen_mode <= max_inline);
1230 assert(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send);
1231 assert(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw ||
1232 !txq_ctrl->txq.inlen_empw);
1240 * Create a DPDK Tx queue.
1243 * Pointer to Ethernet device.
1247 * Number of descriptors to configure in queue.
1249 * NUMA socket on which memory must be allocated.
1251 * Thresholds parameters.
1254 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1256 struct mlx5_txq_ctrl *
1257 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1258 unsigned int socket, const struct rte_eth_txconf *conf)
1260 struct mlx5_priv *priv = dev->data->dev_private;
1261 struct mlx5_txq_ctrl *tmpl;
1263 tmpl = rte_calloc_socket("TXQ", 1,
1265 desc * sizeof(struct rte_mbuf *),
1271 if (mlx5_mr_btree_init(&tmpl->txq.mr_ctrl.cache_bh,
1272 MLX5_MR_BTREE_CACHE_N, socket)) {
1273 /* rte_errno is already set. */
1276 /* Save pointer of global generation number to check memory event. */
1277 tmpl->txq.mr_ctrl.dev_gen_ptr = &priv->sh->mr.dev_gen;
1278 assert(desc > MLX5_TX_COMP_THRESH);
1279 tmpl->txq.offloads = conf->offloads |
1280 dev->data->dev_conf.txmode.offloads;
1282 tmpl->socket = socket;
1283 tmpl->txq.elts_n = log2above(desc);
1284 tmpl->txq.elts_s = desc;
1285 tmpl->txq.elts_m = desc - 1;
1286 tmpl->txq.port_id = dev->data->port_id;
1287 tmpl->txq.idx = idx;
1288 txq_set_params(tmpl);
1289 if (txq_adjust_params(tmpl))
1291 if (txq_calc_wqebb_cnt(tmpl) >
1292 priv->sh->device_attr.orig_attr.max_qp_wr) {
1294 "port %u Tx WQEBB count (%d) exceeds the limit (%d),"
1295 " try smaller queue size",
1296 dev->data->port_id, txq_calc_wqebb_cnt(tmpl),
1297 priv->sh->device_attr.orig_attr.max_qp_wr);
1301 rte_atomic32_inc(&tmpl->refcnt);
1302 tmpl->type = MLX5_TXQ_TYPE_STANDARD;
1303 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
1311 * Create a DPDK Tx hairpin queue.
1314 * Pointer to Ethernet device.
1318 * Number of descriptors to configure in queue.
1319 * @param hairpin_conf
1320 * The hairpin configuration.
1323 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1325 struct mlx5_txq_ctrl *
1326 mlx5_txq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1327 const struct rte_eth_hairpin_conf *hairpin_conf)
1329 struct mlx5_priv *priv = dev->data->dev_private;
1330 struct mlx5_txq_ctrl *tmpl;
1332 tmpl = rte_calloc_socket("TXQ", 1,
1333 sizeof(*tmpl), 0, SOCKET_ID_ANY);
1339 tmpl->socket = SOCKET_ID_ANY;
1340 tmpl->txq.elts_n = log2above(desc);
1341 tmpl->txq.port_id = dev->data->port_id;
1342 tmpl->txq.idx = idx;
1343 tmpl->hairpin_conf = *hairpin_conf;
1344 tmpl->type = MLX5_TXQ_TYPE_HAIRPIN;
1345 rte_atomic32_inc(&tmpl->refcnt);
1346 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
1354 * Pointer to Ethernet device.
1359 * A pointer to the queue if it exists.
1361 struct mlx5_txq_ctrl *
1362 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
1364 struct mlx5_priv *priv = dev->data->dev_private;
1365 struct mlx5_txq_ctrl *ctrl = NULL;
1367 if ((*priv->txqs)[idx]) {
1368 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
1370 mlx5_txq_obj_get(dev, idx);
1371 rte_atomic32_inc(&ctrl->refcnt);
1377 * Release a Tx queue.
1380 * Pointer to Ethernet device.
1385 * 1 while a reference on it exists, 0 when freed.
1388 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
1390 struct mlx5_priv *priv = dev->data->dev_private;
1391 struct mlx5_txq_ctrl *txq;
1393 if (!(*priv->txqs)[idx])
1395 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
1396 if (txq->obj && !mlx5_txq_obj_release(txq->obj))
1398 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
1400 mlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh);
1401 LIST_REMOVE(txq, next);
1403 (*priv->txqs)[idx] = NULL;
1410 * Verify if the queue can be released.
1413 * Pointer to Ethernet device.
1418 * 1 if the queue can be released.
1421 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
1423 struct mlx5_priv *priv = dev->data->dev_private;
1424 struct mlx5_txq_ctrl *txq;
1426 if (!(*priv->txqs)[idx])
1428 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
1429 return (rte_atomic32_read(&txq->refcnt) == 1);
1433 * Verify the Tx Queue list is empty
1436 * Pointer to Ethernet device.
1439 * The number of object not released.
1442 mlx5_txq_verify(struct rte_eth_dev *dev)
1444 struct mlx5_priv *priv = dev->data->dev_private;
1445 struct mlx5_txq_ctrl *txq_ctrl;
1448 LIST_FOREACH(txq_ctrl, &priv->txqsctrl, next) {
1449 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced",
1450 dev->data->port_id, txq_ctrl->txq.idx);