1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox.
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_malloc.h>
26 #include <rte_ethdev_driver.h>
27 #include <rte_common.h>
29 #include "mlx5_utils.h"
30 #include "mlx5_defs.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_glue.h"
37 * Allocate TX queue elements.
40 * Pointer to TX queue structure.
43 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
45 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
48 for (i = 0; (i != elts_n); ++i)
49 (*txq_ctrl->txq.elts)[i] = NULL;
50 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
51 txq_ctrl->priv->dev->data->port_id, txq_ctrl->idx, elts_n);
52 txq_ctrl->txq.elts_head = 0;
53 txq_ctrl->txq.elts_tail = 0;
54 txq_ctrl->txq.elts_comp = 0;
58 * Free TX queue elements.
61 * Pointer to TX queue structure.
64 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
66 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
67 const uint16_t elts_m = elts_n - 1;
68 uint16_t elts_head = txq_ctrl->txq.elts_head;
69 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
70 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
72 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs",
73 txq_ctrl->priv->dev->data->port_id, txq_ctrl->idx);
74 txq_ctrl->txq.elts_head = 0;
75 txq_ctrl->txq.elts_tail = 0;
76 txq_ctrl->txq.elts_comp = 0;
78 while (elts_tail != elts_head) {
79 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
82 rte_pktmbuf_free_seg(elt);
85 memset(&(*elts)[elts_tail & elts_m],
87 sizeof((*elts)[elts_tail & elts_m]));
94 * Returns the per-port supported offloads.
97 * Pointer to Ethernet device.
100 * Supported Tx offloads.
103 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
105 struct priv *priv = dev->data->dev_private;
106 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
107 DEV_TX_OFFLOAD_VLAN_INSERT);
108 struct mlx5_dev_config *config = &priv->config;
111 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
112 DEV_TX_OFFLOAD_UDP_CKSUM |
113 DEV_TX_OFFLOAD_TCP_CKSUM);
115 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
116 if (config->tunnel_en) {
118 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
120 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
121 DEV_TX_OFFLOAD_GRE_TNL_TSO);
127 * Checks if the per-queue offload configuration is valid.
130 * Pointer to Ethernet device.
132 * Per-queue offloads configuration.
135 * 1 if the configuration is valid, 0 otherwise.
138 mlx5_is_tx_queue_offloads_allowed(struct rte_eth_dev *dev, uint64_t offloads)
140 uint64_t port_offloads = dev->data->dev_conf.txmode.offloads;
141 uint64_t port_supp_offloads = mlx5_get_tx_port_offloads(dev);
143 /* There are no Tx offloads which are per queue. */
144 if ((offloads & port_supp_offloads) != offloads)
146 if ((port_offloads ^ offloads) & port_supp_offloads)
152 * DPDK callback to configure a TX queue.
155 * Pointer to Ethernet device structure.
159 * Number of descriptors to configure in queue.
161 * NUMA socket on which memory must be allocated.
163 * Thresholds parameters.
166 * 0 on success, a negative errno value otherwise and rte_errno is set.
169 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
170 unsigned int socket, const struct rte_eth_txconf *conf)
172 struct priv *priv = dev->data->dev_private;
173 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
174 struct mlx5_txq_ctrl *txq_ctrl =
175 container_of(txq, struct mlx5_txq_ctrl, txq);
178 * Don't verify port offloads for application which
181 if (!!(conf->txq_flags & ETH_TXQ_FLAGS_IGNORE) &&
182 !mlx5_is_tx_queue_offloads_allowed(dev, conf->offloads)) {
185 "port %u Tx queue offloads 0x%" PRIx64 " don't match"
186 " port offloads 0x%" PRIx64 " or supported offloads 0x%"
188 dev->data->port_id, conf->offloads,
189 dev->data->dev_conf.txmode.offloads,
190 mlx5_get_tx_port_offloads(dev));
193 if (desc <= MLX5_TX_COMP_THRESH) {
195 "port %u number of descriptors requested for Tx queue"
196 " %u must be higher than MLX5_TX_COMP_THRESH, using %u"
198 dev->data->port_id, idx, MLX5_TX_COMP_THRESH + 1, desc);
199 desc = MLX5_TX_COMP_THRESH + 1;
201 if (!rte_is_power_of_2(desc)) {
202 desc = 1 << log2above(desc);
204 "port %u increased number of descriptors in Tx queue"
205 " %u to the next power of two (%d)",
206 dev->data->port_id, idx, desc);
208 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors",
209 dev->data->port_id, idx, desc);
210 if (idx >= priv->txqs_n) {
211 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)",
212 dev->data->port_id, idx, priv->txqs_n);
213 rte_errno = EOVERFLOW;
216 if (!mlx5_txq_releasable(dev, idx)) {
218 DRV_LOG(ERR, "port %u unable to release queue index %u",
219 dev->data->port_id, idx);
222 mlx5_txq_release(dev, idx);
223 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
225 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
226 dev->data->port_id, idx);
229 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
230 dev->data->port_id, idx);
231 (*priv->txqs)[idx] = &txq_ctrl->txq;
236 * DPDK callback to release a TX queue.
239 * Generic TX queue pointer.
242 mlx5_tx_queue_release(void *dpdk_txq)
244 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
245 struct mlx5_txq_ctrl *txq_ctrl;
251 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
252 priv = txq_ctrl->priv;
253 for (i = 0; (i != priv->txqs_n); ++i)
254 if ((*priv->txqs)[i] == txq) {
255 mlx5_txq_release(priv->dev, i);
256 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
257 priv->dev->data->port_id, txq_ctrl->idx);
264 * Mmap TX UAR(HW doorbell) pages into reserved UAR address space.
265 * Both primary and secondary process do mmap to make UAR address
269 * Pointer to Ethernet device.
271 * Verbs file descriptor to map UAR pages.
274 * 0 on success, a negative errno value otherwise and rte_errno is set.
277 mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd)
279 struct priv *priv = dev->data->dev_private;
281 uintptr_t pages[priv->txqs_n];
282 unsigned int pages_n = 0;
287 struct mlx5_txq_data *txq;
288 struct mlx5_txq_ctrl *txq_ctrl;
290 size_t page_size = sysconf(_SC_PAGESIZE);
292 memset(pages, 0, priv->txqs_n * sizeof(uintptr_t));
294 * As rdma-core, UARs are mapped in size of OS page size.
295 * Use aligned address to avoid duplicate mmap.
296 * Ref to libmlx5 function: mlx5_init_context()
298 for (i = 0; i != priv->txqs_n; ++i) {
299 if (!(*priv->txqs)[i])
301 txq = (*priv->txqs)[i];
302 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
303 assert(txq_ctrl->idx == (uint16_t)i);
304 /* UAR addr form verbs used to find dup and offset in page. */
305 uar_va = (uintptr_t)txq_ctrl->bf_reg_orig;
306 off = uar_va & (page_size - 1); /* offset in page. */
307 uar_va = RTE_ALIGN_FLOOR(uar_va, page_size); /* page addr. */
309 for (j = 0; j != pages_n; ++j) {
310 if (pages[j] == uar_va) {
315 /* new address in reserved UAR address space. */
316 addr = RTE_PTR_ADD(priv->uar_base,
317 uar_va & (MLX5_UAR_SIZE - 1));
318 if (!already_mapped) {
319 pages[pages_n++] = uar_va;
320 /* fixed mmap to specified address in reserved
323 ret = mmap(addr, page_size,
324 PROT_WRITE, MAP_FIXED | MAP_SHARED, fd,
325 txq_ctrl->uar_mmap_offset);
327 /* fixed mmap have to return same address */
329 "port %u call to mmap failed on UAR"
331 dev->data->port_id, txq_ctrl->idx);
336 if (rte_eal_process_type() == RTE_PROC_PRIMARY) /* save once */
337 txq_ctrl->txq.bf_reg = RTE_PTR_ADD((void *)addr, off);
339 assert(txq_ctrl->txq.bf_reg ==
340 RTE_PTR_ADD((void *)addr, off));
346 * Check if the burst function is using eMPW.
348 * @param tx_pkt_burst
349 * Tx burst function pointer.
352 * 1 if the burst function is using eMPW, 0 otherwise.
355 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst)
357 if (tx_pkt_burst == mlx5_tx_burst_raw_vec ||
358 tx_pkt_burst == mlx5_tx_burst_vec ||
359 tx_pkt_burst == mlx5_tx_burst_empw)
365 * Create the Tx queue Verbs object.
368 * Pointer to Ethernet device.
370 * Queue index in DPDK Rx queue array
373 * The Verbs object initialised, NULL otherwise and rte_errno is set.
375 struct mlx5_txq_ibv *
376 mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
378 struct priv *priv = dev->data->dev_private;
379 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
380 struct mlx5_txq_ctrl *txq_ctrl =
381 container_of(txq_data, struct mlx5_txq_ctrl, txq);
382 struct mlx5_txq_ibv tmpl;
383 struct mlx5_txq_ibv *txq_ibv;
385 struct ibv_qp_init_attr_ex init;
386 struct ibv_cq_init_attr_ex cq;
387 struct ibv_qp_attr mod;
388 struct ibv_cq_ex cq_attr;
391 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
392 struct mlx5dv_cq cq_info;
393 struct mlx5dv_obj obj;
394 const int desc = 1 << txq_data->elts_n;
395 eth_tx_burst_t tx_pkt_burst = mlx5_select_tx_function(dev);
399 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
400 priv->verbs_alloc_ctx.obj = txq_ctrl;
401 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
403 "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set",
408 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));
409 /* MRs will be registered in mp2mr[] later. */
410 attr.cq = (struct ibv_cq_init_attr_ex){
413 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
414 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
415 if (is_empw_burst_func(tx_pkt_burst))
416 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
417 tmpl.cq = mlx5_glue->create_cq(priv->ctx, cqe_n, NULL, NULL, 0);
418 if (tmpl.cq == NULL) {
419 DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
420 dev->data->port_id, idx);
424 attr.init = (struct ibv_qp_init_attr_ex){
425 /* CQ to be associated with the send queue. */
427 /* CQ to be associated with the receive queue. */
430 /* Max number of outstanding WRs. */
432 ((priv->device_attr.orig_attr.max_qp_wr <
434 priv->device_attr.orig_attr.max_qp_wr :
437 * Max number of scatter/gather elements in a WR,
438 * must be 1 to prevent libmlx5 from trying to affect
439 * too much memory. TX gather is not impacted by the
440 * priv->device_attr.max_sge limit and will still work
445 .qp_type = IBV_QPT_RAW_PACKET,
447 * Do *NOT* enable this, completions events are managed per
452 .comp_mask = IBV_QP_INIT_ATTR_PD,
454 if (txq_data->max_inline)
455 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
456 if (txq_data->tso_en) {
457 attr.init.max_tso_header = txq_ctrl->max_tso_header;
458 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
460 tmpl.qp = mlx5_glue->create_qp_ex(priv->ctx, &attr.init);
461 if (tmpl.qp == NULL) {
462 DRV_LOG(ERR, "port %u Tx queue %u QP creation failure",
463 dev->data->port_id, idx);
467 attr.mod = (struct ibv_qp_attr){
468 /* Move the QP to this state. */
469 .qp_state = IBV_QPS_INIT,
470 /* Primary port number. */
471 .port_num = priv->port
473 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
474 (IBV_QP_STATE | IBV_QP_PORT));
477 "port %u Tx queue %u QP state to IBV_QPS_INIT failed",
478 dev->data->port_id, idx);
482 attr.mod = (struct ibv_qp_attr){
483 .qp_state = IBV_QPS_RTR
485 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
488 "port %u Tx queue %u QP state to IBV_QPS_RTR failed",
489 dev->data->port_id, idx);
493 attr.mod.qp_state = IBV_QPS_RTS;
494 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
497 "port %u Tx queue %u QP state to IBV_QPS_RTS failed",
498 dev->data->port_id, idx);
502 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,
505 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory",
506 dev->data->port_id, idx);
511 obj.cq.out = &cq_info;
514 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
519 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
521 "port %u wrong MLX5_CQE_SIZE environment variable"
522 " value: it should be set to %u",
523 dev->data->port_id, RTE_CACHE_LINE_SIZE);
527 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
528 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
529 txq_data->wqes = qp.sq.buf;
530 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
531 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
532 txq_ctrl->bf_reg_orig = qp.bf.reg;
533 txq_data->cq_db = cq_info.dbrec;
535 (volatile struct mlx5_cqe (*)[])
536 (uintptr_t)cq_info.buf;
541 txq_data->wqe_ci = 0;
542 txq_data->wqe_pi = 0;
543 txq_ibv->qp = tmpl.qp;
544 txq_ibv->cq = tmpl.cq;
545 rte_atomic32_inc(&txq_ibv->refcnt);
546 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
547 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
550 "port %u failed to retrieve UAR info, invalid"
556 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u: refcnt %d",
557 dev->data->port_id, idx, rte_atomic32_read(&txq_ibv->refcnt));
558 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
559 txq_ibv->txq_ctrl = txq_ctrl;
560 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
563 ret = rte_errno; /* Save rte_errno before cleanup. */
565 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
567 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
568 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
569 rte_errno = ret; /* Restore rte_errno. */
574 * Get an Tx queue Verbs object.
577 * Pointer to Ethernet device.
579 * Queue index in DPDK Rx queue array
582 * The Verbs object if it exists.
584 struct mlx5_txq_ibv *
585 mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
587 struct priv *priv = dev->data->dev_private;
588 struct mlx5_txq_ctrl *txq_ctrl;
590 if (idx >= priv->txqs_n)
592 if (!(*priv->txqs)[idx])
594 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
596 rte_atomic32_inc(&txq_ctrl->ibv->refcnt);
597 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u: refcnt %d",
598 dev->data->port_id, txq_ctrl->idx,
599 rte_atomic32_read(&txq_ctrl->ibv->refcnt));
601 return txq_ctrl->ibv;
605 * Release an Tx verbs queue object.
608 * Verbs Tx queue object.
611 * 1 while a reference on it exists, 0 when freed.
614 mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv)
617 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u: refcnt %d",
618 txq_ibv->txq_ctrl->priv->dev->data->port_id,
619 txq_ibv->txq_ctrl->idx, rte_atomic32_read(&txq_ibv->refcnt));
620 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {
621 claim_zero(mlx5_glue->destroy_qp(txq_ibv->qp));
622 claim_zero(mlx5_glue->destroy_cq(txq_ibv->cq));
623 LIST_REMOVE(txq_ibv, next);
631 * Return true if a single reference exists on the object.
634 * Verbs Tx queue object.
637 mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv)
640 return (rte_atomic32_read(&txq_ibv->refcnt) == 1);
644 * Verify the Verbs Tx queue list is empty
647 * Pointer to Ethernet device.
650 * The number of object not released.
653 mlx5_txq_ibv_verify(struct rte_eth_dev *dev)
655 struct priv *priv = dev->data->dev_private;
657 struct mlx5_txq_ibv *txq_ibv;
659 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) {
660 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced",
661 dev->data->port_id, txq_ibv->txq_ctrl->idx);
668 * Set Tx queue parameters from device configuration.
671 * Pointer to Tx queue control structure.
674 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
676 struct priv *priv = txq_ctrl->priv;
677 struct mlx5_dev_config *config = &priv->config;
678 const unsigned int max_tso_inline =
679 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) /
680 RTE_CACHE_LINE_SIZE);
681 unsigned int txq_inline;
682 unsigned int txqs_inline;
683 unsigned int inline_max_packet_sz;
684 eth_tx_burst_t tx_pkt_burst =
685 mlx5_select_tx_function(txq_ctrl->priv->dev);
686 int is_empw_func = is_empw_burst_func(tx_pkt_burst);
687 int tso = !!(txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_TCP_TSO);
689 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ?
690 0 : config->txq_inline;
691 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ?
692 0 : config->txqs_inline;
693 inline_max_packet_sz =
694 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ?
695 0 : config->inline_max_packet_sz;
697 if (config->txq_inline == MLX5_ARG_UNSET)
698 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;
699 if (config->txqs_inline == MLX5_ARG_UNSET)
700 txqs_inline = MLX5_EMPW_MIN_TXQS;
701 if (config->inline_max_packet_sz == MLX5_ARG_UNSET)
702 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN;
703 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg;
704 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz;
706 if (txq_inline && priv->txqs_n >= txqs_inline) {
709 txq_ctrl->txq.max_inline =
710 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
711 RTE_CACHE_LINE_SIZE);
713 /* To minimize the size of data set, avoid requesting
716 txq_ctrl->max_inline_data =
717 ((RTE_MIN(txq_inline,
718 inline_max_packet_sz) +
719 (RTE_CACHE_LINE_SIZE - 1)) /
720 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
722 int inline_diff = txq_ctrl->txq.max_inline -
726 * Adjust inline value as Verbs aggregates
727 * tso_inline and txq_inline fields.
729 txq_ctrl->max_inline_data = inline_diff > 0 ?
731 RTE_CACHE_LINE_SIZE :
734 txq_ctrl->max_inline_data =
735 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE;
738 * Check if the inline size is too large in a way which
739 * can make the WQE DS to overflow.
740 * Considering in calculation:
745 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE);
746 if (ds_cnt > MLX5_DSEG_MAX) {
747 unsigned int max_inline = (MLX5_DSEG_MAX - 2) *
750 max_inline = max_inline - (max_inline %
751 RTE_CACHE_LINE_SIZE);
753 "port %u txq inline is too large (%d) setting"
754 " it to the maximum possible: %d\n",
755 priv->dev->data->port_id, txq_inline,
757 txq_ctrl->txq.max_inline = max_inline /
762 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE;
763 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline,
765 txq_ctrl->txq.tso_en = 1;
767 txq_ctrl->txq.tunnel_en = config->tunnel_en;
771 * Create a DPDK Tx queue.
774 * Pointer to Ethernet device.
778 * Number of descriptors to configure in queue.
780 * NUMA socket on which memory must be allocated.
782 * Thresholds parameters.
785 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
787 struct mlx5_txq_ctrl *
788 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
789 unsigned int socket, const struct rte_eth_txconf *conf)
791 struct priv *priv = dev->data->dev_private;
792 struct mlx5_txq_ctrl *tmpl;
794 tmpl = rte_calloc_socket("TXQ", 1,
796 desc * sizeof(struct rte_mbuf *),
802 assert(desc > MLX5_TX_COMP_THRESH);
803 tmpl->txq.offloads = conf->offloads;
805 tmpl->socket = socket;
806 tmpl->txq.elts_n = log2above(desc);
808 txq_set_params(tmpl);
809 /* MRs will be registered in mp2mr[] later. */
810 DRV_LOG(DEBUG, "port %u priv->device_attr.max_qp_wr is %d",
811 dev->data->port_id, priv->device_attr.orig_attr.max_qp_wr);
812 DRV_LOG(DEBUG, "port %u priv->device_attr.max_sge is %d",
813 dev->data->port_id, priv->device_attr.orig_attr.max_sge);
815 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1);
816 tmpl->txq.stats.idx = idx;
817 rte_atomic32_inc(&tmpl->refcnt);
818 DRV_LOG(DEBUG, "port %u Tx queue %u: refcnt %d", dev->data->port_id,
819 idx, rte_atomic32_read(&tmpl->refcnt));
820 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
828 * Pointer to Ethernet device.
833 * A pointer to the queue if it exists.
835 struct mlx5_txq_ctrl *
836 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
838 struct priv *priv = dev->data->dev_private;
839 struct mlx5_txq_ctrl *ctrl = NULL;
841 if ((*priv->txqs)[idx]) {
842 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
846 mlx5_txq_ibv_get(dev, idx);
847 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
848 if (ctrl->txq.mp2mr[i])
851 ctrl->txq.mp2mr[i]->mp));
853 rte_atomic32_inc(&ctrl->refcnt);
854 DRV_LOG(DEBUG, "port %u Tx queue %u refcnt %d",
856 ctrl->idx, rte_atomic32_read(&ctrl->refcnt));
862 * Release a Tx queue.
865 * Pointer to Ethernet device.
870 * 1 while a reference on it exists, 0 when freed.
873 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
875 struct priv *priv = dev->data->dev_private;
877 struct mlx5_txq_ctrl *txq;
878 size_t page_size = sysconf(_SC_PAGESIZE);
880 if (!(*priv->txqs)[idx])
882 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
883 DRV_LOG(DEBUG, "port %u Tx queue %u: refcnt %d", dev->data->port_id,
884 txq->idx, rte_atomic32_read(&txq->refcnt));
885 if (txq->ibv && !mlx5_txq_ibv_release(txq->ibv))
887 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
888 if (txq->txq.mp2mr[i]) {
889 mlx5_mr_release(txq->txq.mp2mr[i]);
890 txq->txq.mp2mr[i] = NULL;
894 munmap((void *)RTE_ALIGN_FLOOR((uintptr_t)txq->txq.bf_reg,
895 page_size), page_size);
896 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
898 LIST_REMOVE(txq, next);
900 (*priv->txqs)[idx] = NULL;
907 * Verify if the queue can be released.
910 * Pointer to Ethernet device.
915 * 1 if the queue can be released.
918 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
920 struct priv *priv = dev->data->dev_private;
921 struct mlx5_txq_ctrl *txq;
923 if (!(*priv->txqs)[idx])
925 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
926 return (rte_atomic32_read(&txq->refcnt) == 1);
930 * Verify the Tx Queue list is empty
933 * Pointer to Ethernet device.
936 * The number of object not released.
939 mlx5_txq_verify(struct rte_eth_dev *dev)
941 struct priv *priv = dev->data->dev_private;
942 struct mlx5_txq_ctrl *txq;
945 LIST_FOREACH(txq, &priv->txqsctrl, next) {
946 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced",
947 dev->data->port_id, txq->idx);