1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_malloc.h>
26 #include <rte_ethdev_driver.h>
27 #include <rte_common.h>
29 #include "mlx5_utils.h"
30 #include "mlx5_defs.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_glue.h"
37 * Allocate TX queue elements.
40 * Pointer to TX queue structure.
43 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
45 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
48 for (i = 0; (i != elts_n); ++i)
49 (*txq_ctrl->txq.elts)[i] = NULL;
50 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
51 PORT_ID(txq_ctrl->priv), txq_ctrl->idx, elts_n);
52 txq_ctrl->txq.elts_head = 0;
53 txq_ctrl->txq.elts_tail = 0;
54 txq_ctrl->txq.elts_comp = 0;
58 * Free TX queue elements.
61 * Pointer to TX queue structure.
64 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
66 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
67 const uint16_t elts_m = elts_n - 1;
68 uint16_t elts_head = txq_ctrl->txq.elts_head;
69 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
70 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
72 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs",
73 PORT_ID(txq_ctrl->priv), txq_ctrl->idx);
74 txq_ctrl->txq.elts_head = 0;
75 txq_ctrl->txq.elts_tail = 0;
76 txq_ctrl->txq.elts_comp = 0;
78 while (elts_tail != elts_head) {
79 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
82 rte_pktmbuf_free_seg(elt);
85 memset(&(*elts)[elts_tail & elts_m],
87 sizeof((*elts)[elts_tail & elts_m]));
94 * Returns the per-port supported offloads.
97 * Pointer to Ethernet device.
100 * Supported Tx offloads.
103 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
105 struct priv *priv = dev->data->dev_private;
106 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
107 DEV_TX_OFFLOAD_VLAN_INSERT);
108 struct mlx5_dev_config *config = &priv->config;
111 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
112 DEV_TX_OFFLOAD_UDP_CKSUM |
113 DEV_TX_OFFLOAD_TCP_CKSUM);
115 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
116 if (config->tunnel_en) {
118 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
120 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
121 DEV_TX_OFFLOAD_GRE_TNL_TSO);
123 offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
124 DEV_TX_OFFLOAD_UDP_TNL_TSO);
130 * DPDK callback to configure a TX queue.
133 * Pointer to Ethernet device structure.
137 * Number of descriptors to configure in queue.
139 * NUMA socket on which memory must be allocated.
141 * Thresholds parameters.
144 * 0 on success, a negative errno value otherwise and rte_errno is set.
147 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
148 unsigned int socket, const struct rte_eth_txconf *conf)
150 struct priv *priv = dev->data->dev_private;
151 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
152 struct mlx5_txq_ctrl *txq_ctrl =
153 container_of(txq, struct mlx5_txq_ctrl, txq);
155 if (desc <= MLX5_TX_COMP_THRESH) {
157 "port %u number of descriptors requested for Tx queue"
158 " %u must be higher than MLX5_TX_COMP_THRESH, using %u"
160 dev->data->port_id, idx, MLX5_TX_COMP_THRESH + 1, desc);
161 desc = MLX5_TX_COMP_THRESH + 1;
163 if (!rte_is_power_of_2(desc)) {
164 desc = 1 << log2above(desc);
166 "port %u increased number of descriptors in Tx queue"
167 " %u to the next power of two (%d)",
168 dev->data->port_id, idx, desc);
170 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors",
171 dev->data->port_id, idx, desc);
172 if (idx >= priv->txqs_n) {
173 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)",
174 dev->data->port_id, idx, priv->txqs_n);
175 rte_errno = EOVERFLOW;
178 if (!mlx5_txq_releasable(dev, idx)) {
180 DRV_LOG(ERR, "port %u unable to release queue index %u",
181 dev->data->port_id, idx);
184 mlx5_txq_release(dev, idx);
185 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
187 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
188 dev->data->port_id, idx);
191 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
192 dev->data->port_id, idx);
193 (*priv->txqs)[idx] = &txq_ctrl->txq;
198 * DPDK callback to release a TX queue.
201 * Generic TX queue pointer.
204 mlx5_tx_queue_release(void *dpdk_txq)
206 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
207 struct mlx5_txq_ctrl *txq_ctrl;
213 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
214 priv = txq_ctrl->priv;
215 for (i = 0; (i != priv->txqs_n); ++i)
216 if ((*priv->txqs)[i] == txq) {
217 mlx5_txq_release(ETH_DEV(priv), i);
218 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
219 PORT_ID(priv), txq_ctrl->idx);
226 * Mmap TX UAR(HW doorbell) pages into reserved UAR address space.
227 * Both primary and secondary process do mmap to make UAR address
231 * Pointer to Ethernet device.
233 * Verbs file descriptor to map UAR pages.
236 * 0 on success, a negative errno value otherwise and rte_errno is set.
239 mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd)
241 struct priv *priv = dev->data->dev_private;
243 uintptr_t pages[priv->txqs_n];
244 unsigned int pages_n = 0;
249 struct mlx5_txq_data *txq;
250 struct mlx5_txq_ctrl *txq_ctrl;
252 size_t page_size = sysconf(_SC_PAGESIZE);
254 memset(pages, 0, priv->txqs_n * sizeof(uintptr_t));
256 * As rdma-core, UARs are mapped in size of OS page size.
257 * Use aligned address to avoid duplicate mmap.
258 * Ref to libmlx5 function: mlx5_init_context()
260 for (i = 0; i != priv->txqs_n; ++i) {
261 if (!(*priv->txqs)[i])
263 txq = (*priv->txqs)[i];
264 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
265 assert(txq_ctrl->idx == (uint16_t)i);
266 /* UAR addr form verbs used to find dup and offset in page. */
267 uar_va = (uintptr_t)txq_ctrl->bf_reg_orig;
268 off = uar_va & (page_size - 1); /* offset in page. */
269 uar_va = RTE_ALIGN_FLOOR(uar_va, page_size); /* page addr. */
271 for (j = 0; j != pages_n; ++j) {
272 if (pages[j] == uar_va) {
277 /* new address in reserved UAR address space. */
278 addr = RTE_PTR_ADD(priv->uar_base,
279 uar_va & (MLX5_UAR_SIZE - 1));
280 if (!already_mapped) {
281 pages[pages_n++] = uar_va;
282 /* fixed mmap to specified address in reserved
285 ret = mmap(addr, page_size,
286 PROT_WRITE, MAP_FIXED | MAP_SHARED, fd,
287 txq_ctrl->uar_mmap_offset);
289 /* fixed mmap have to return same address */
291 "port %u call to mmap failed on UAR"
293 dev->data->port_id, txq_ctrl->idx);
298 if (rte_eal_process_type() == RTE_PROC_PRIMARY) /* save once */
299 txq_ctrl->txq.bf_reg = RTE_PTR_ADD((void *)addr, off);
301 assert(txq_ctrl->txq.bf_reg ==
302 RTE_PTR_ADD((void *)addr, off));
308 * Check if the burst function is using eMPW.
310 * @param tx_pkt_burst
311 * Tx burst function pointer.
314 * 1 if the burst function is using eMPW, 0 otherwise.
317 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst)
319 if (tx_pkt_burst == mlx5_tx_burst_raw_vec ||
320 tx_pkt_burst == mlx5_tx_burst_vec ||
321 tx_pkt_burst == mlx5_tx_burst_empw)
327 * Create the Tx queue Verbs object.
330 * Pointer to Ethernet device.
332 * Queue index in DPDK Rx queue array
335 * The Verbs object initialised, NULL otherwise and rte_errno is set.
337 struct mlx5_txq_ibv *
338 mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
340 struct priv *priv = dev->data->dev_private;
341 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
342 struct mlx5_txq_ctrl *txq_ctrl =
343 container_of(txq_data, struct mlx5_txq_ctrl, txq);
344 struct mlx5_txq_ibv tmpl;
345 struct mlx5_txq_ibv *txq_ibv;
347 struct ibv_qp_init_attr_ex init;
348 struct ibv_cq_init_attr_ex cq;
349 struct ibv_qp_attr mod;
350 struct ibv_cq_ex cq_attr;
353 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
354 struct mlx5dv_cq cq_info;
355 struct mlx5dv_obj obj;
356 const int desc = 1 << txq_data->elts_n;
357 eth_tx_burst_t tx_pkt_burst = mlx5_select_tx_function(dev);
361 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
362 priv->verbs_alloc_ctx.obj = txq_ctrl;
363 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
365 "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set",
370 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));
371 attr.cq = (struct ibv_cq_init_attr_ex){
374 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
375 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
376 if (is_empw_burst_func(tx_pkt_burst))
377 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
378 tmpl.cq = mlx5_glue->create_cq(priv->ctx, cqe_n, NULL, NULL, 0);
379 if (tmpl.cq == NULL) {
380 DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
381 dev->data->port_id, idx);
385 attr.init = (struct ibv_qp_init_attr_ex){
386 /* CQ to be associated with the send queue. */
388 /* CQ to be associated with the receive queue. */
391 /* Max number of outstanding WRs. */
393 ((priv->device_attr.orig_attr.max_qp_wr <
395 priv->device_attr.orig_attr.max_qp_wr :
398 * Max number of scatter/gather elements in a WR,
399 * must be 1 to prevent libmlx5 from trying to affect
400 * too much memory. TX gather is not impacted by the
401 * priv->device_attr.max_sge limit and will still work
406 .qp_type = IBV_QPT_RAW_PACKET,
408 * Do *NOT* enable this, completions events are managed per
413 .comp_mask = IBV_QP_INIT_ATTR_PD,
415 if (txq_data->max_inline)
416 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
417 if (txq_data->tso_en) {
418 attr.init.max_tso_header = txq_ctrl->max_tso_header;
419 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
421 tmpl.qp = mlx5_glue->create_qp_ex(priv->ctx, &attr.init);
422 if (tmpl.qp == NULL) {
423 DRV_LOG(ERR, "port %u Tx queue %u QP creation failure",
424 dev->data->port_id, idx);
428 attr.mod = (struct ibv_qp_attr){
429 /* Move the QP to this state. */
430 .qp_state = IBV_QPS_INIT,
431 /* Primary port number. */
432 .port_num = priv->port
434 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
435 (IBV_QP_STATE | IBV_QP_PORT));
438 "port %u Tx queue %u QP state to IBV_QPS_INIT failed",
439 dev->data->port_id, idx);
443 attr.mod = (struct ibv_qp_attr){
444 .qp_state = IBV_QPS_RTR
446 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
449 "port %u Tx queue %u QP state to IBV_QPS_RTR failed",
450 dev->data->port_id, idx);
454 attr.mod.qp_state = IBV_QPS_RTS;
455 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
458 "port %u Tx queue %u QP state to IBV_QPS_RTS failed",
459 dev->data->port_id, idx);
463 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,
466 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory",
467 dev->data->port_id, idx);
472 obj.cq.out = &cq_info;
475 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
480 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
482 "port %u wrong MLX5_CQE_SIZE environment variable"
483 " value: it should be set to %u",
484 dev->data->port_id, RTE_CACHE_LINE_SIZE);
488 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
489 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
490 txq_data->wqes = qp.sq.buf;
491 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
492 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
493 txq_ctrl->bf_reg_orig = qp.bf.reg;
494 txq_data->cq_db = cq_info.dbrec;
496 (volatile struct mlx5_cqe (*)[])
497 (uintptr_t)cq_info.buf;
502 txq_data->wqe_ci = 0;
503 txq_data->wqe_pi = 0;
504 txq_ibv->qp = tmpl.qp;
505 txq_ibv->cq = tmpl.cq;
506 rte_atomic32_inc(&txq_ibv->refcnt);
507 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
508 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
511 "port %u failed to retrieve UAR info, invalid"
517 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u: refcnt %d",
518 dev->data->port_id, idx, rte_atomic32_read(&txq_ibv->refcnt));
519 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
520 txq_ibv->txq_ctrl = txq_ctrl;
521 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
524 ret = rte_errno; /* Save rte_errno before cleanup. */
526 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
528 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
529 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
530 rte_errno = ret; /* Restore rte_errno. */
535 * Get an Tx queue Verbs object.
538 * Pointer to Ethernet device.
540 * Queue index in DPDK Rx queue array
543 * The Verbs object if it exists.
545 struct mlx5_txq_ibv *
546 mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
548 struct priv *priv = dev->data->dev_private;
549 struct mlx5_txq_ctrl *txq_ctrl;
551 if (idx >= priv->txqs_n)
553 if (!(*priv->txqs)[idx])
555 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
557 rte_atomic32_inc(&txq_ctrl->ibv->refcnt);
558 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u: refcnt %d",
559 dev->data->port_id, txq_ctrl->idx,
560 rte_atomic32_read(&txq_ctrl->ibv->refcnt));
562 return txq_ctrl->ibv;
566 * Release an Tx verbs queue object.
569 * Verbs Tx queue object.
572 * 1 while a reference on it exists, 0 when freed.
575 mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv)
578 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u: refcnt %d",
579 PORT_ID(txq_ibv->txq_ctrl->priv),
580 txq_ibv->txq_ctrl->idx, rte_atomic32_read(&txq_ibv->refcnt));
581 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {
582 claim_zero(mlx5_glue->destroy_qp(txq_ibv->qp));
583 claim_zero(mlx5_glue->destroy_cq(txq_ibv->cq));
584 LIST_REMOVE(txq_ibv, next);
592 * Return true if a single reference exists on the object.
595 * Verbs Tx queue object.
598 mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv)
601 return (rte_atomic32_read(&txq_ibv->refcnt) == 1);
605 * Verify the Verbs Tx queue list is empty
608 * Pointer to Ethernet device.
611 * The number of object not released.
614 mlx5_txq_ibv_verify(struct rte_eth_dev *dev)
616 struct priv *priv = dev->data->dev_private;
618 struct mlx5_txq_ibv *txq_ibv;
620 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) {
621 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced",
622 dev->data->port_id, txq_ibv->txq_ctrl->idx);
629 * Set Tx queue parameters from device configuration.
632 * Pointer to Tx queue control structure.
635 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
637 struct priv *priv = txq_ctrl->priv;
638 struct mlx5_dev_config *config = &priv->config;
639 const unsigned int max_tso_inline =
640 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) /
641 RTE_CACHE_LINE_SIZE);
642 unsigned int txq_inline;
643 unsigned int txqs_inline;
644 unsigned int inline_max_packet_sz;
645 eth_tx_burst_t tx_pkt_burst =
646 mlx5_select_tx_function(ETH_DEV(priv));
647 int is_empw_func = is_empw_burst_func(tx_pkt_burst);
648 int tso = !!(txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO |
649 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
650 DEV_TX_OFFLOAD_GRE_TNL_TSO |
651 DEV_TX_OFFLOAD_IP_TNL_TSO |
652 DEV_TX_OFFLOAD_UDP_TNL_TSO));
654 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ?
655 0 : config->txq_inline;
656 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ?
657 0 : config->txqs_inline;
658 inline_max_packet_sz =
659 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ?
660 0 : config->inline_max_packet_sz;
662 if (config->txq_inline == MLX5_ARG_UNSET)
663 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;
664 if (config->txqs_inline == MLX5_ARG_UNSET)
665 txqs_inline = MLX5_EMPW_MIN_TXQS;
666 if (config->inline_max_packet_sz == MLX5_ARG_UNSET)
667 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN;
668 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg;
669 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz;
671 if (txq_inline && priv->txqs_n >= txqs_inline) {
674 txq_ctrl->txq.max_inline =
675 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
676 RTE_CACHE_LINE_SIZE);
678 /* To minimize the size of data set, avoid requesting
681 txq_ctrl->max_inline_data =
682 ((RTE_MIN(txq_inline,
683 inline_max_packet_sz) +
684 (RTE_CACHE_LINE_SIZE - 1)) /
685 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
687 txq_ctrl->max_inline_data =
688 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE;
691 * Check if the inline size is too large in a way which
692 * can make the WQE DS to overflow.
693 * Considering in calculation:
698 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE);
699 if (ds_cnt > MLX5_DSEG_MAX) {
700 unsigned int max_inline = (MLX5_DSEG_MAX - 2) *
703 max_inline = max_inline - (max_inline %
704 RTE_CACHE_LINE_SIZE);
706 "port %u txq inline is too large (%d) setting"
707 " it to the maximum possible: %d\n",
708 PORT_ID(priv), txq_inline, max_inline);
709 txq_ctrl->txq.max_inline = max_inline /
714 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE;
715 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline,
717 txq_ctrl->txq.tso_en = 1;
719 txq_ctrl->txq.tunnel_en = config->tunnel_en;
720 txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
721 DEV_TX_OFFLOAD_UDP_TNL_TSO |
722 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
723 txq_ctrl->txq.offloads) && config->swp;
727 * Create a DPDK Tx queue.
730 * Pointer to Ethernet device.
734 * Number of descriptors to configure in queue.
736 * NUMA socket on which memory must be allocated.
738 * Thresholds parameters.
741 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
743 struct mlx5_txq_ctrl *
744 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
745 unsigned int socket, const struct rte_eth_txconf *conf)
747 struct priv *priv = dev->data->dev_private;
748 struct mlx5_txq_ctrl *tmpl;
750 tmpl = rte_calloc_socket("TXQ", 1,
752 desc * sizeof(struct rte_mbuf *),
758 assert(desc > MLX5_TX_COMP_THRESH);
759 tmpl->txq.offloads = conf->offloads |
760 dev->data->dev_conf.txmode.offloads;
762 tmpl->socket = socket;
763 tmpl->txq.elts_n = log2above(desc);
765 txq_set_params(tmpl);
766 DRV_LOG(DEBUG, "port %u priv->device_attr.max_qp_wr is %d",
767 dev->data->port_id, priv->device_attr.orig_attr.max_qp_wr);
768 DRV_LOG(DEBUG, "port %u priv->device_attr.max_sge is %d",
769 dev->data->port_id, priv->device_attr.orig_attr.max_sge);
771 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1);
772 tmpl->txq.stats.idx = idx;
773 rte_atomic32_inc(&tmpl->refcnt);
774 DRV_LOG(DEBUG, "port %u Tx queue %u: refcnt %d", dev->data->port_id,
775 idx, rte_atomic32_read(&tmpl->refcnt));
776 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
784 * Pointer to Ethernet device.
789 * A pointer to the queue if it exists.
791 struct mlx5_txq_ctrl *
792 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
794 struct priv *priv = dev->data->dev_private;
795 struct mlx5_txq_ctrl *ctrl = NULL;
797 if ((*priv->txqs)[idx]) {
798 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
800 mlx5_txq_ibv_get(dev, idx);
801 rte_atomic32_inc(&ctrl->refcnt);
802 DRV_LOG(DEBUG, "port %u Tx queue %u refcnt %d",
804 ctrl->idx, rte_atomic32_read(&ctrl->refcnt));
810 * Release a Tx queue.
813 * Pointer to Ethernet device.
818 * 1 while a reference on it exists, 0 when freed.
821 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
823 struct priv *priv = dev->data->dev_private;
824 struct mlx5_txq_ctrl *txq;
825 size_t page_size = sysconf(_SC_PAGESIZE);
827 if (!(*priv->txqs)[idx])
829 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
830 DRV_LOG(DEBUG, "port %u Tx queue %u: refcnt %d", dev->data->port_id,
831 txq->idx, rte_atomic32_read(&txq->refcnt));
832 if (txq->ibv && !mlx5_txq_ibv_release(txq->ibv))
835 munmap((void *)RTE_ALIGN_FLOOR((uintptr_t)txq->txq.bf_reg,
836 page_size), page_size);
837 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
839 LIST_REMOVE(txq, next);
841 (*priv->txqs)[idx] = NULL;
848 * Verify if the queue can be released.
851 * Pointer to Ethernet device.
856 * 1 if the queue can be released.
859 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
861 struct priv *priv = dev->data->dev_private;
862 struct mlx5_txq_ctrl *txq;
864 if (!(*priv->txqs)[idx])
866 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
867 return (rte_atomic32_read(&txq->refcnt) == 1);
871 * Verify the Tx Queue list is empty
874 * Pointer to Ethernet device.
877 * The number of object not released.
880 mlx5_txq_verify(struct rte_eth_dev *dev)
882 struct priv *priv = dev->data->dev_private;
883 struct mlx5_txq_ctrl *txq;
886 LIST_FOREACH(txq, &priv->txqsctrl, next) {
887 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced",
888 dev->data->port_id, txq->idx);