4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
47 #pragma GCC diagnostic error "-Wpedantic"
50 /* DPDK headers don't like -pedantic. */
52 #pragma GCC diagnostic ignored "-Wpedantic"
55 #include <rte_malloc.h>
56 #include <rte_ethdev.h>
57 #include <rte_common.h>
59 #pragma GCC diagnostic error "-Wpedantic"
62 #include "mlx5_utils.h"
63 #include "mlx5_defs.h"
65 #include "mlx5_rxtx.h"
66 #include "mlx5_autoconf.h"
69 * Allocate TX queue elements.
72 * Pointer to TX queue structure.
74 * Number of elements to allocate.
77 txq_alloc_elts(struct txq_ctrl *txq_ctrl, unsigned int elts_n)
81 for (i = 0; (i != elts_n); ++i)
82 (*txq_ctrl->txq.elts)[i] = NULL;
83 for (i = 0; (i != (1u << txq_ctrl->txq.wqe_n)); ++i) {
84 volatile struct mlx5_wqe64 *wqe =
85 (volatile struct mlx5_wqe64 *)
86 txq_ctrl->txq.wqes + i;
88 memset((void *)(uintptr_t)wqe, 0x0, sizeof(*wqe));
90 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
91 txq_ctrl->txq.elts_head = 0;
92 txq_ctrl->txq.elts_tail = 0;
93 txq_ctrl->txq.elts_comp = 0;
97 * Free TX queue elements.
100 * Pointer to TX queue structure.
103 txq_free_elts(struct txq_ctrl *txq_ctrl)
105 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
106 const uint16_t elts_m = elts_n - 1;
107 uint16_t elts_head = txq_ctrl->txq.elts_head;
108 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
109 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
111 DEBUG("%p: freeing WRs", (void *)txq_ctrl);
112 txq_ctrl->txq.elts_head = 0;
113 txq_ctrl->txq.elts_tail = 0;
114 txq_ctrl->txq.elts_comp = 0;
116 while (elts_tail != elts_head) {
117 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
120 rte_pktmbuf_free_seg(elt);
123 memset(&(*elts)[elts_tail & elts_m],
125 sizeof((*elts)[elts_tail & elts_m]));
132 * Clean up a TX queue.
134 * Destroy objects, free allocated memory and reset the structure for reuse.
137 * Pointer to TX queue structure.
140 txq_cleanup(struct txq_ctrl *txq_ctrl)
144 DEBUG("cleaning up %p", (void *)txq_ctrl);
145 txq_free_elts(txq_ctrl);
146 if (txq_ctrl->qp != NULL)
147 claim_zero(ibv_destroy_qp(txq_ctrl->qp));
148 if (txq_ctrl->cq != NULL)
149 claim_zero(ibv_destroy_cq(txq_ctrl->cq));
150 for (i = 0; (i != RTE_DIM(txq_ctrl->txq.mp2mr)); ++i) {
151 if (txq_ctrl->txq.mp2mr[i].mr == NULL)
153 claim_zero(ibv_dereg_mr(txq_ctrl->txq.mp2mr[i].mr));
155 memset(txq_ctrl, 0, sizeof(*txq_ctrl));
159 * Initialize TX queue.
162 * Pointer to TX queue control template.
164 * Pointer to TX queue control.
167 * 0 on success, errno value on failure.
170 txq_setup(struct txq_ctrl *tmpl, struct txq_ctrl *txq_ctrl)
172 struct mlx5_qp *qp = to_mqp(tmpl->qp);
173 struct ibv_cq *ibcq = tmpl->cq;
174 struct ibv_mlx5_cq_info cq_info;
176 if (ibv_mlx5_exp_get_cq_info(ibcq, &cq_info)) {
177 ERROR("Unable to query CQ info. check your OFED.");
180 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
181 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
182 "it should be set to %u", RTE_CACHE_LINE_SIZE);
185 tmpl->txq.cqe_n = log2above(cq_info.cqe_cnt);
186 tmpl->txq.qp_num_8s = qp->ctrl_seg.qp_num << 8;
187 tmpl->txq.wqes = qp->gen_data.sqstart;
188 tmpl->txq.wqe_n = log2above(qp->sq.wqe_cnt);
189 tmpl->txq.qp_db = &qp->gen_data.db[MLX5_SND_DBR];
190 tmpl->txq.bf_reg = qp->gen_data.bf->reg;
191 tmpl->txq.cq_db = cq_info.dbrec;
193 (volatile struct mlx5_cqe (*)[])
194 (uintptr_t)cq_info.buf;
196 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])
197 ((uintptr_t)txq_ctrl + sizeof(*txq_ctrl));
202 * Configure a TX queue.
205 * Pointer to Ethernet device structure.
207 * Pointer to TX queue structure.
209 * Number of descriptors to configure in queue.
211 * NUMA socket on which memory must be allocated.
213 * Thresholds parameters.
216 * 0 on success, errno value on failure.
219 txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,
220 uint16_t desc, unsigned int socket,
221 const struct rte_eth_txconf *conf)
223 struct priv *priv = mlx5_get_priv(dev);
224 struct txq_ctrl tmpl = {
229 struct ibv_exp_qp_init_attr init;
230 struct ibv_exp_cq_init_attr cq;
231 struct ibv_exp_qp_attr mod;
232 struct ibv_exp_cq_attr cq_attr;
235 const unsigned int max_tso_inline = ((MLX5_MAX_TSO_HEADER +
236 (RTE_CACHE_LINE_SIZE - 1)) /
237 RTE_CACHE_LINE_SIZE);
240 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
242 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set");
245 tmpl.txq.flags = conf->txq_flags;
246 assert(desc > MLX5_TX_COMP_THRESH);
247 tmpl.txq.elts_n = log2above(desc);
248 if (priv->mps == MLX5_MPW_ENHANCED)
249 tmpl.txq.mpw_hdr_dseg = priv->mpw_hdr_dseg;
250 /* MRs will be registered in mp2mr[] later. */
251 attr.cq = (struct ibv_exp_cq_init_attr){
254 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
255 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
256 if (priv->mps == MLX5_MPW_ENHANCED)
257 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
258 tmpl.cq = ibv_exp_create_cq(priv->ctx,
260 NULL, NULL, 0, &attr.cq);
261 if (tmpl.cq == NULL) {
263 ERROR("%p: CQ creation failure: %s",
264 (void *)dev, strerror(ret));
267 DEBUG("priv->device_attr.max_qp_wr is %d",
268 priv->device_attr.max_qp_wr);
269 DEBUG("priv->device_attr.max_sge is %d",
270 priv->device_attr.max_sge);
271 attr.init = (struct ibv_exp_qp_init_attr){
272 /* CQ to be associated with the send queue. */
274 /* CQ to be associated with the receive queue. */
277 /* Max number of outstanding WRs. */
278 .max_send_wr = ((priv->device_attr.max_qp_wr < desc) ?
279 priv->device_attr.max_qp_wr :
282 * Max number of scatter/gather elements in a WR,
283 * must be 1 to prevent libmlx5 from trying to affect
284 * too much memory. TX gather is not impacted by the
285 * priv->device_attr.max_sge limit and will still work
290 .qp_type = IBV_QPT_RAW_PACKET,
291 /* Do *NOT* enable this, completions events are managed per
295 .comp_mask = IBV_EXP_QP_INIT_ATTR_PD,
297 if (priv->txq_inline && (priv->txqs_n >= priv->txqs_inline)) {
298 tmpl.txq.max_inline =
299 ((priv->txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
300 RTE_CACHE_LINE_SIZE);
301 tmpl.txq.inline_en = 1;
302 /* TSO and MPS can't be enabled concurrently. */
303 assert(!priv->tso || !priv->mps);
304 if (priv->mps == MLX5_MPW_ENHANCED) {
305 tmpl.txq.inline_max_packet_sz =
306 priv->inline_max_packet_sz;
307 /* To minimize the size of data set, avoid requesting
310 attr.init.cap.max_inline_data =
311 ((RTE_MIN(priv->txq_inline,
312 priv->inline_max_packet_sz) +
313 (RTE_CACHE_LINE_SIZE - 1)) /
314 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
315 } else if (priv->tso) {
316 int inline_diff = tmpl.txq.max_inline - max_tso_inline;
319 * Adjust inline value as Verbs aggregates
320 * tso_inline and txq_inline fields.
322 attr.init.cap.max_inline_data = inline_diff > 0 ?
324 RTE_CACHE_LINE_SIZE :
327 attr.init.cap.max_inline_data =
328 tmpl.txq.max_inline * RTE_CACHE_LINE_SIZE;
332 attr.init.max_tso_header =
333 max_tso_inline * RTE_CACHE_LINE_SIZE;
334 attr.init.comp_mask |= IBV_EXP_QP_INIT_ATTR_MAX_TSO_HEADER;
335 tmpl.txq.max_inline = RTE_MAX(tmpl.txq.max_inline,
340 tmpl.txq.tunnel_en = 1;
341 tmpl.qp = ibv_exp_create_qp(priv->ctx, &attr.init);
342 if (tmpl.qp == NULL) {
343 ret = (errno ? errno : EINVAL);
344 ERROR("%p: QP creation failure: %s",
345 (void *)dev, strerror(ret));
348 DEBUG("TX queue capabilities: max_send_wr=%u, max_send_sge=%u,"
349 " max_inline_data=%u",
350 attr.init.cap.max_send_wr,
351 attr.init.cap.max_send_sge,
352 attr.init.cap.max_inline_data);
353 attr.mod = (struct ibv_exp_qp_attr){
354 /* Move the QP to this state. */
355 .qp_state = IBV_QPS_INIT,
356 /* Primary port number. */
357 .port_num = priv->port
359 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod,
360 (IBV_EXP_QP_STATE | IBV_EXP_QP_PORT));
362 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
363 (void *)dev, strerror(ret));
366 ret = txq_setup(&tmpl, txq_ctrl);
368 ERROR("%p: cannot initialize TX queue structure: %s",
369 (void *)dev, strerror(ret));
372 txq_alloc_elts(&tmpl, desc);
373 attr.mod = (struct ibv_exp_qp_attr){
374 .qp_state = IBV_QPS_RTR
376 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
378 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
379 (void *)dev, strerror(ret));
382 attr.mod.qp_state = IBV_QPS_RTS;
383 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
385 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
386 (void *)dev, strerror(ret));
389 /* Clean up txq in case we're reinitializing it. */
390 DEBUG("%p: cleaning-up old txq just in case", (void *)txq_ctrl);
391 txq_cleanup(txq_ctrl);
393 DEBUG("%p: txq updated with %p", (void *)txq_ctrl, (void *)&tmpl);
394 /* Pre-register known mempools. */
395 rte_mempool_walk(txq_mp2mr_iter, txq_ctrl);
405 * DPDK callback to configure a TX queue.
408 * Pointer to Ethernet device structure.
412 * Number of descriptors to configure in queue.
414 * NUMA socket on which memory must be allocated.
416 * Thresholds parameters.
419 * 0 on success, negative errno value on failure.
422 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
423 unsigned int socket, const struct rte_eth_txconf *conf)
425 struct priv *priv = dev->data->dev_private;
426 struct txq *txq = (*priv->txqs)[idx];
427 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
430 if (mlx5_is_secondary())
431 return -E_RTE_SECONDARY;
434 if (desc <= MLX5_TX_COMP_THRESH) {
435 WARN("%p: number of descriptors requested for TX queue %u"
436 " must be higher than MLX5_TX_COMP_THRESH, using"
438 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
439 desc = MLX5_TX_COMP_THRESH + 1;
441 if (!rte_is_power_of_2(desc)) {
442 desc = 1 << log2above(desc);
443 WARN("%p: increased number of descriptors in TX queue %u"
444 " to the next power of two (%d)",
445 (void *)dev, idx, desc);
447 DEBUG("%p: configuring queue %u for %u descriptors",
448 (void *)dev, idx, desc);
449 if (idx >= priv->txqs_n) {
450 ERROR("%p: queue index out of range (%u >= %u)",
451 (void *)dev, idx, priv->txqs_n);
456 DEBUG("%p: reusing already allocated queue index %u (%p)",
457 (void *)dev, idx, (void *)txq);
462 (*priv->txqs)[idx] = NULL;
463 txq_cleanup(txq_ctrl);
464 /* Resize if txq size is changed. */
465 if (txq_ctrl->txq.elts_n != log2above(desc)) {
466 txq_ctrl = rte_realloc(txq_ctrl,
468 desc * sizeof(struct rte_mbuf *),
469 RTE_CACHE_LINE_SIZE);
471 ERROR("%p: unable to reallocate queue index %u",
479 rte_calloc_socket("TXQ", 1,
481 desc * sizeof(struct rte_mbuf *),
483 if (txq_ctrl == NULL) {
484 ERROR("%p: unable to allocate queue index %u",
490 ret = txq_ctrl_setup(dev, txq_ctrl, desc, socket, conf);
494 txq_ctrl->txq.stats.idx = idx;
495 DEBUG("%p: adding TX queue %p to list",
496 (void *)dev, (void *)txq_ctrl);
497 (*priv->txqs)[idx] = &txq_ctrl->txq;
504 * DPDK callback to release a TX queue.
507 * Generic TX queue pointer.
510 mlx5_tx_queue_release(void *dpdk_txq)
512 struct txq *txq = (struct txq *)dpdk_txq;
513 struct txq_ctrl *txq_ctrl;
517 if (mlx5_is_secondary())
522 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
523 priv = txq_ctrl->priv;
525 for (i = 0; (i != priv->txqs_n); ++i)
526 if ((*priv->txqs)[i] == txq) {
527 DEBUG("%p: removing TX queue %p from list",
528 (void *)priv->dev, (void *)txq_ctrl);
529 (*priv->txqs)[i] = NULL;
532 txq_cleanup(txq_ctrl);
538 * DPDK callback for TX in secondary processes.
540 * This function configures all queues from primary process information
541 * if necessary before reverting to the normal TX burst callback.
544 * Generic pointer to TX queue structure.
546 * Packets to transmit.
548 * Number of packets in array.
551 * Number of packets successfully transmitted (<= pkts_n).
554 mlx5_tx_burst_secondary_setup(void *dpdk_txq, struct rte_mbuf **pkts,
557 struct txq *txq = dpdk_txq;
558 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
559 struct priv *priv = mlx5_secondary_data_setup(txq_ctrl->priv);
560 struct priv *primary_priv;
566 mlx5_secondary_data[priv->dev->data->port_id].primary_priv;
567 /* Look for queue index in both private structures. */
568 for (index = 0; index != priv->txqs_n; ++index)
569 if (((*primary_priv->txqs)[index] == txq) ||
570 ((*priv->txqs)[index] == txq))
572 if (index == priv->txqs_n)
574 txq = (*priv->txqs)[index];
575 return priv->dev->tx_pkt_burst(txq, pkts, pkts_n);