1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox.
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_malloc.h>
26 #include <rte_ethdev_driver.h>
27 #include <rte_common.h>
29 #include "mlx5_utils.h"
30 #include "mlx5_defs.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_glue.h"
37 * Allocate TX queue elements.
40 * Pointer to TX queue structure.
43 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
45 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
48 for (i = 0; (i != elts_n); ++i)
49 (*txq_ctrl->txq.elts)[i] = NULL;
50 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
51 txq_ctrl->txq.elts_head = 0;
52 txq_ctrl->txq.elts_tail = 0;
53 txq_ctrl->txq.elts_comp = 0;
57 * Free TX queue elements.
60 * Pointer to TX queue structure.
63 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
65 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
66 const uint16_t elts_m = elts_n - 1;
67 uint16_t elts_head = txq_ctrl->txq.elts_head;
68 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
69 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
71 DEBUG("%p: freeing WRs", (void *)txq_ctrl);
72 txq_ctrl->txq.elts_head = 0;
73 txq_ctrl->txq.elts_tail = 0;
74 txq_ctrl->txq.elts_comp = 0;
76 while (elts_tail != elts_head) {
77 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
80 rte_pktmbuf_free_seg(elt);
83 memset(&(*elts)[elts_tail & elts_m],
85 sizeof((*elts)[elts_tail & elts_m]));
92 * Returns the per-port supported offloads.
95 * Pointer to private structure.
98 * Supported Tx offloads.
101 mlx5_priv_get_tx_port_offloads(struct priv *priv)
103 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
104 DEV_TX_OFFLOAD_VLAN_INSERT);
105 struct mlx5_dev_config *config = &priv->config;
108 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
109 DEV_TX_OFFLOAD_UDP_CKSUM |
110 DEV_TX_OFFLOAD_TCP_CKSUM);
112 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
113 if (config->tunnel_en) {
115 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
117 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
118 DEV_TX_OFFLOAD_GRE_TNL_TSO);
124 * Checks if the per-queue offload configuration is valid.
127 * Pointer to private structure.
129 * Per-queue offloads configuration.
132 * 1 if the configuration is valid, 0 otherwise.
135 priv_is_tx_queue_offloads_allowed(struct priv *priv, uint64_t offloads)
137 uint64_t port_offloads = priv->dev->data->dev_conf.txmode.offloads;
138 uint64_t port_supp_offloads = mlx5_priv_get_tx_port_offloads(priv);
140 /* There are no Tx offloads which are per queue. */
141 if ((offloads & port_supp_offloads) != offloads)
143 if ((port_offloads ^ offloads) & port_supp_offloads)
149 * DPDK callback to configure a TX queue.
152 * Pointer to Ethernet device structure.
156 * Number of descriptors to configure in queue.
158 * NUMA socket on which memory must be allocated.
160 * Thresholds parameters.
163 * 0 on success, negative errno value on failure.
166 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
167 unsigned int socket, const struct rte_eth_txconf *conf)
169 struct priv *priv = dev->data->dev_private;
170 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
171 struct mlx5_txq_ctrl *txq_ctrl =
172 container_of(txq, struct mlx5_txq_ctrl, txq);
177 * Don't verify port offloads for application which
180 if (!!(conf->txq_flags & ETH_TXQ_FLAGS_IGNORE) &&
181 !priv_is_tx_queue_offloads_allowed(priv, conf->offloads)) {
183 ERROR("%p: Tx queue offloads 0x%" PRIx64 " don't match port "
184 "offloads 0x%" PRIx64 " or supported offloads 0x%" PRIx64,
185 (void *)dev, conf->offloads,
186 dev->data->dev_conf.txmode.offloads,
187 mlx5_priv_get_tx_port_offloads(priv));
190 if (desc <= MLX5_TX_COMP_THRESH) {
191 WARN("%p: number of descriptors requested for TX queue %u"
192 " must be higher than MLX5_TX_COMP_THRESH, using"
194 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
195 desc = MLX5_TX_COMP_THRESH + 1;
197 if (!rte_is_power_of_2(desc)) {
198 desc = 1 << log2above(desc);
199 WARN("%p: increased number of descriptors in TX queue %u"
200 " to the next power of two (%d)",
201 (void *)dev, idx, desc);
203 DEBUG("%p: configuring queue %u for %u descriptors",
204 (void *)dev, idx, desc);
205 if (idx >= priv->txqs_n) {
206 ERROR("%p: queue index out of range (%u >= %u)",
207 (void *)dev, idx, priv->txqs_n);
211 if (!mlx5_priv_txq_releasable(priv, idx)) {
213 ERROR("%p: unable to release queue index %u",
217 mlx5_priv_txq_release(priv, idx);
218 txq_ctrl = mlx5_priv_txq_new(priv, idx, desc, socket, conf);
220 ERROR("%p: unable to allocate queue index %u",
225 DEBUG("%p: adding TX queue %p to list",
226 (void *)dev, (void *)txq_ctrl);
227 (*priv->txqs)[idx] = &txq_ctrl->txq;
234 * DPDK callback to release a TX queue.
237 * Generic TX queue pointer.
240 mlx5_tx_queue_release(void *dpdk_txq)
242 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
243 struct mlx5_txq_ctrl *txq_ctrl;
249 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
250 priv = txq_ctrl->priv;
252 for (i = 0; (i != priv->txqs_n); ++i)
253 if ((*priv->txqs)[i] == txq) {
254 DEBUG("%p: removing TX queue %p from list",
255 (void *)priv->dev, (void *)txq_ctrl);
256 mlx5_priv_txq_release(priv, i);
264 * Mmap TX UAR(HW doorbell) pages into reserved UAR address space.
265 * Both primary and secondary process do mmap to make UAR address
269 * Pointer to private structure.
271 * Verbs file descriptor to map UAR pages.
274 * 0 on success, errno value on failure.
277 priv_tx_uar_remap(struct priv *priv, int fd)
280 uintptr_t pages[priv->txqs_n];
281 unsigned int pages_n = 0;
286 struct mlx5_txq_data *txq;
287 struct mlx5_txq_ctrl *txq_ctrl;
289 size_t page_size = sysconf(_SC_PAGESIZE);
292 memset(pages, 0, priv->txqs_n * sizeof(uintptr_t));
294 * As rdma-core, UARs are mapped in size of OS page size.
295 * Use aligned address to avoid duplicate mmap.
296 * Ref to libmlx5 function: mlx5_init_context()
298 for (i = 0; i != priv->txqs_n; ++i) {
299 if (!(*priv->txqs)[i])
301 txq = (*priv->txqs)[i];
302 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
303 /* UAR addr form verbs used to find dup and offset in page. */
304 uar_va = (uintptr_t)txq_ctrl->bf_reg_orig;
305 off = uar_va & (page_size - 1); /* offset in page. */
306 uar_va = RTE_ALIGN_FLOOR(uar_va, page_size); /* page addr. */
308 for (j = 0; j != pages_n; ++j) {
309 if (pages[j] == uar_va) {
314 /* new address in reserved UAR address space. */
315 addr = RTE_PTR_ADD(priv->uar_base,
316 uar_va & (MLX5_UAR_SIZE - 1));
317 if (!already_mapped) {
318 pages[pages_n++] = uar_va;
319 /* fixed mmap to specified address in reserved
322 ret = mmap(addr, page_size,
323 PROT_WRITE, MAP_FIXED | MAP_SHARED, fd,
324 txq_ctrl->uar_mmap_offset);
326 /* fixed mmap have to return same address */
327 ERROR("call to mmap failed on UAR for txq %d\n",
333 if (rte_eal_process_type() == RTE_PROC_PRIMARY) /* save once */
334 txq_ctrl->txq.bf_reg = RTE_PTR_ADD((void *)addr, off);
336 assert(txq_ctrl->txq.bf_reg ==
337 RTE_PTR_ADD((void *)addr, off));
343 * Check if the burst function is using eMPW.
345 * @param tx_pkt_burst
346 * Tx burst function pointer.
349 * 1 if the burst function is using eMPW, 0 otherwise.
352 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst)
354 if (tx_pkt_burst == mlx5_tx_burst_raw_vec ||
355 tx_pkt_burst == mlx5_tx_burst_vec ||
356 tx_pkt_burst == mlx5_tx_burst_empw)
362 * Create the Tx queue Verbs object.
365 * Pointer to private structure.
367 * Queue index in DPDK Rx queue array
370 * The Verbs object initialised if it can be created.
372 struct mlx5_txq_ibv *
373 mlx5_priv_txq_ibv_new(struct priv *priv, uint16_t idx)
375 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
376 struct mlx5_txq_ctrl *txq_ctrl =
377 container_of(txq_data, struct mlx5_txq_ctrl, txq);
378 struct mlx5_txq_ibv tmpl;
379 struct mlx5_txq_ibv *txq_ibv;
381 struct ibv_qp_init_attr_ex init;
382 struct ibv_cq_init_attr_ex cq;
383 struct ibv_qp_attr mod;
384 struct ibv_cq_ex cq_attr;
387 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
388 struct mlx5dv_cq cq_info;
389 struct mlx5dv_obj obj;
390 const int desc = 1 << txq_data->elts_n;
391 eth_tx_burst_t tx_pkt_burst = priv_select_tx_function(priv, priv->dev);
395 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
396 priv->verbs_alloc_ctx.obj = txq_ctrl;
397 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
398 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set");
401 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));
402 /* MRs will be registered in mp2mr[] later. */
403 attr.cq = (struct ibv_cq_init_attr_ex){
406 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
407 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
408 if (is_empw_burst_func(tx_pkt_burst))
409 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
410 tmpl.cq = mlx5_glue->create_cq(priv->ctx, cqe_n, NULL, NULL, 0);
411 if (tmpl.cq == NULL) {
412 ERROR("%p: CQ creation failure", (void *)txq_ctrl);
415 attr.init = (struct ibv_qp_init_attr_ex){
416 /* CQ to be associated with the send queue. */
418 /* CQ to be associated with the receive queue. */
421 /* Max number of outstanding WRs. */
423 ((priv->device_attr.orig_attr.max_qp_wr <
425 priv->device_attr.orig_attr.max_qp_wr :
428 * Max number of scatter/gather elements in a WR,
429 * must be 1 to prevent libmlx5 from trying to affect
430 * too much memory. TX gather is not impacted by the
431 * priv->device_attr.max_sge limit and will still work
436 .qp_type = IBV_QPT_RAW_PACKET,
438 * Do *NOT* enable this, completions events are managed per
443 .comp_mask = IBV_QP_INIT_ATTR_PD,
445 if (txq_data->max_inline)
446 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
447 if (txq_data->tso_en) {
448 attr.init.max_tso_header = txq_ctrl->max_tso_header;
449 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
451 tmpl.qp = mlx5_glue->create_qp_ex(priv->ctx, &attr.init);
452 if (tmpl.qp == NULL) {
453 ERROR("%p: QP creation failure", (void *)txq_ctrl);
456 attr.mod = (struct ibv_qp_attr){
457 /* Move the QP to this state. */
458 .qp_state = IBV_QPS_INIT,
459 /* Primary port number. */
460 .port_num = priv->port
462 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
463 (IBV_QP_STATE | IBV_QP_PORT));
465 ERROR("%p: QP state to IBV_QPS_INIT failed", (void *)txq_ctrl);
468 attr.mod = (struct ibv_qp_attr){
469 .qp_state = IBV_QPS_RTR
471 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
473 ERROR("%p: QP state to IBV_QPS_RTR failed", (void *)txq_ctrl);
476 attr.mod.qp_state = IBV_QPS_RTS;
477 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
479 ERROR("%p: QP state to IBV_QPS_RTS failed", (void *)txq_ctrl);
482 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,
485 ERROR("%p: cannot allocate memory", (void *)txq_ctrl);
489 obj.cq.out = &cq_info;
492 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
495 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
496 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
497 "it should be set to %u", RTE_CACHE_LINE_SIZE);
500 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
501 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
502 txq_data->wqes = qp.sq.buf;
503 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
504 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
505 txq_ctrl->bf_reg_orig = qp.bf.reg;
506 txq_data->cq_db = cq_info.dbrec;
508 (volatile struct mlx5_cqe (*)[])
509 (uintptr_t)cq_info.buf;
514 txq_data->wqe_ci = 0;
515 txq_data->wqe_pi = 0;
516 txq_ibv->qp = tmpl.qp;
517 txq_ibv->cq = tmpl.cq;
518 rte_atomic32_inc(&txq_ibv->refcnt);
519 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
520 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
522 ERROR("Failed to retrieve UAR info, invalid libmlx5.so version");
525 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv,
526 (void *)txq_ibv, rte_atomic32_read(&txq_ibv->refcnt));
527 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
528 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
532 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
534 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
535 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
540 * Get an Tx queue Verbs object.
543 * Pointer to private structure.
545 * Queue index in DPDK Rx queue array
548 * The Verbs object if it exists.
550 struct mlx5_txq_ibv *
551 mlx5_priv_txq_ibv_get(struct priv *priv, uint16_t idx)
553 struct mlx5_txq_ctrl *txq_ctrl;
555 if (idx >= priv->txqs_n)
557 if (!(*priv->txqs)[idx])
559 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
561 rte_atomic32_inc(&txq_ctrl->ibv->refcnt);
562 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv,
563 (void *)txq_ctrl->ibv,
564 rte_atomic32_read(&txq_ctrl->ibv->refcnt));
566 return txq_ctrl->ibv;
570 * Release an Tx verbs queue object.
573 * Pointer to private structure.
575 * Verbs Tx queue object.
578 * 0 on success, errno on failure.
581 mlx5_priv_txq_ibv_release(struct priv *priv __rte_unused,
582 struct mlx5_txq_ibv *txq_ibv)
585 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv,
586 (void *)txq_ibv, rte_atomic32_read(&txq_ibv->refcnt));
587 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {
588 claim_zero(mlx5_glue->destroy_qp(txq_ibv->qp));
589 claim_zero(mlx5_glue->destroy_cq(txq_ibv->cq));
590 LIST_REMOVE(txq_ibv, next);
598 * Return true if a single reference exists on the object.
601 * Pointer to private structure.
603 * Verbs Tx queue object.
606 mlx5_priv_txq_ibv_releasable(struct priv *priv __rte_unused,
607 struct mlx5_txq_ibv *txq_ibv)
610 return (rte_atomic32_read(&txq_ibv->refcnt) == 1);
614 * Verify the Verbs Tx queue list is empty
617 * Pointer to private structure.
620 * The number of object not released.
623 mlx5_priv_txq_ibv_verify(struct priv *priv)
626 struct mlx5_txq_ibv *txq_ibv;
628 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) {
629 DEBUG("%p: Verbs Tx queue %p still referenced", (void *)priv,
637 * Set Tx queue parameters from device configuration.
640 * Pointer to Tx queue control structure.
643 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
645 struct priv *priv = txq_ctrl->priv;
646 struct mlx5_dev_config *config = &priv->config;
647 const unsigned int max_tso_inline =
648 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) /
649 RTE_CACHE_LINE_SIZE);
650 unsigned int txq_inline;
651 unsigned int txqs_inline;
652 unsigned int inline_max_packet_sz;
653 eth_tx_burst_t tx_pkt_burst = priv_select_tx_function(priv, priv->dev);
654 int is_empw_func = is_empw_burst_func(tx_pkt_burst);
655 int tso = !!(txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_TCP_TSO);
657 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ?
658 0 : config->txq_inline;
659 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ?
660 0 : config->txqs_inline;
661 inline_max_packet_sz =
662 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ?
663 0 : config->inline_max_packet_sz;
665 if (config->txq_inline == MLX5_ARG_UNSET)
666 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;
667 if (config->txqs_inline == MLX5_ARG_UNSET)
668 txqs_inline = MLX5_EMPW_MIN_TXQS;
669 if (config->inline_max_packet_sz == MLX5_ARG_UNSET)
670 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN;
671 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg;
672 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz;
674 if (txq_inline && priv->txqs_n >= txqs_inline) {
677 txq_ctrl->txq.max_inline =
678 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
679 RTE_CACHE_LINE_SIZE);
681 /* To minimize the size of data set, avoid requesting
684 txq_ctrl->max_inline_data =
685 ((RTE_MIN(txq_inline,
686 inline_max_packet_sz) +
687 (RTE_CACHE_LINE_SIZE - 1)) /
688 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
690 int inline_diff = txq_ctrl->txq.max_inline -
694 * Adjust inline value as Verbs aggregates
695 * tso_inline and txq_inline fields.
697 txq_ctrl->max_inline_data = inline_diff > 0 ?
699 RTE_CACHE_LINE_SIZE :
702 txq_ctrl->max_inline_data =
703 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE;
706 * Check if the inline size is too large in a way which
707 * can make the WQE DS to overflow.
708 * Considering in calculation:
713 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE);
714 if (ds_cnt > MLX5_DSEG_MAX) {
715 unsigned int max_inline = (MLX5_DSEG_MAX - 2) *
718 max_inline = max_inline - (max_inline %
719 RTE_CACHE_LINE_SIZE);
720 WARN("txq inline is too large (%d) setting it to "
721 "the maximum possible: %d\n",
722 txq_inline, max_inline);
723 txq_ctrl->txq.max_inline = max_inline /
728 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE;
729 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline,
731 txq_ctrl->txq.tso_en = 1;
733 txq_ctrl->txq.tunnel_en = config->tunnel_en;
737 * Create a DPDK Tx queue.
740 * Pointer to private structure.
744 * Number of descriptors to configure in queue.
746 * NUMA socket on which memory must be allocated.
748 * Thresholds parameters.
751 * A DPDK queue object on success.
753 struct mlx5_txq_ctrl *
754 mlx5_priv_txq_new(struct priv *priv, uint16_t idx, uint16_t desc,
756 const struct rte_eth_txconf *conf)
758 struct mlx5_txq_ctrl *tmpl;
760 tmpl = rte_calloc_socket("TXQ", 1,
762 desc * sizeof(struct rte_mbuf *),
766 assert(desc > MLX5_TX_COMP_THRESH);
767 tmpl->txq.offloads = conf->offloads;
769 tmpl->socket = socket;
770 tmpl->txq.elts_n = log2above(desc);
771 txq_set_params(tmpl);
772 /* MRs will be registered in mp2mr[] later. */
773 DEBUG("priv->device_attr.max_qp_wr is %d",
774 priv->device_attr.orig_attr.max_qp_wr);
775 DEBUG("priv->device_attr.max_sge is %d",
776 priv->device_attr.orig_attr.max_sge);
778 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1);
779 tmpl->txq.stats.idx = idx;
780 rte_atomic32_inc(&tmpl->refcnt);
781 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv,
782 (void *)tmpl, rte_atomic32_read(&tmpl->refcnt));
783 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
791 * Pointer to private structure.
796 * A pointer to the queue if it exists.
798 struct mlx5_txq_ctrl *
799 mlx5_priv_txq_get(struct priv *priv, uint16_t idx)
801 struct mlx5_txq_ctrl *ctrl = NULL;
803 if ((*priv->txqs)[idx]) {
804 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
808 mlx5_priv_txq_ibv_get(priv, idx);
809 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
810 if (ctrl->txq.mp2mr[i])
813 ctrl->txq.mp2mr[i]->mp));
815 rte_atomic32_inc(&ctrl->refcnt);
816 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv,
817 (void *)ctrl, rte_atomic32_read(&ctrl->refcnt));
823 * Release a Tx queue.
826 * Pointer to private structure.
831 * 0 on success, errno on failure.
834 mlx5_priv_txq_release(struct priv *priv, uint16_t idx)
837 struct mlx5_txq_ctrl *txq;
838 size_t page_size = sysconf(_SC_PAGESIZE);
840 if (!(*priv->txqs)[idx])
842 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
843 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv,
844 (void *)txq, rte_atomic32_read(&txq->refcnt));
848 ret = mlx5_priv_txq_ibv_release(priv, txq->ibv);
852 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
853 if (txq->txq.mp2mr[i]) {
854 priv_mr_release(priv, txq->txq.mp2mr[i]);
855 txq->txq.mp2mr[i] = NULL;
859 munmap((void *)RTE_ALIGN_FLOOR((uintptr_t)txq->txq.bf_reg,
860 page_size), page_size);
861 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
863 LIST_REMOVE(txq, next);
865 (*priv->txqs)[idx] = NULL;
872 * Verify if the queue can be released.
875 * Pointer to private structure.
880 * 1 if the queue can be released.
883 mlx5_priv_txq_releasable(struct priv *priv, uint16_t idx)
885 struct mlx5_txq_ctrl *txq;
887 if (!(*priv->txqs)[idx])
889 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
890 return (rte_atomic32_read(&txq->refcnt) == 1);
894 * Verify the Tx Queue list is empty
897 * Pointer to private structure.
900 * The number of object not released.
903 mlx5_priv_txq_verify(struct priv *priv)
905 struct mlx5_txq_ctrl *txq;
908 LIST_FOREACH(txq, &priv->txqsctrl, next) {
909 DEBUG("%p: Tx Queue %p still referenced", (void *)priv,