1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox.
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_malloc.h>
26 #include <rte_ethdev_driver.h>
27 #include <rte_common.h>
29 #include "mlx5_utils.h"
30 #include "mlx5_defs.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_glue.h"
37 * Allocate TX queue elements.
40 * Pointer to TX queue structure.
43 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
45 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
48 for (i = 0; (i != elts_n); ++i)
49 (*txq_ctrl->txq.elts)[i] = NULL;
50 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
51 txq_ctrl->txq.elts_head = 0;
52 txq_ctrl->txq.elts_tail = 0;
53 txq_ctrl->txq.elts_comp = 0;
57 * Free TX queue elements.
60 * Pointer to TX queue structure.
63 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
65 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
66 const uint16_t elts_m = elts_n - 1;
67 uint16_t elts_head = txq_ctrl->txq.elts_head;
68 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
69 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
71 DEBUG("%p: freeing WRs", (void *)txq_ctrl);
72 txq_ctrl->txq.elts_head = 0;
73 txq_ctrl->txq.elts_tail = 0;
74 txq_ctrl->txq.elts_comp = 0;
76 while (elts_tail != elts_head) {
77 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
80 rte_pktmbuf_free_seg(elt);
83 memset(&(*elts)[elts_tail & elts_m],
85 sizeof((*elts)[elts_tail & elts_m]));
92 * Returns the per-port supported offloads.
95 * Pointer to Ethernet device.
98 * Supported Tx offloads.
101 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
103 struct priv *priv = dev->data->dev_private;
104 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
105 DEV_TX_OFFLOAD_VLAN_INSERT);
106 struct mlx5_dev_config *config = &priv->config;
109 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
110 DEV_TX_OFFLOAD_UDP_CKSUM |
111 DEV_TX_OFFLOAD_TCP_CKSUM);
113 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
114 if (config->tunnel_en) {
116 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
118 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
119 DEV_TX_OFFLOAD_GRE_TNL_TSO);
125 * Checks if the per-queue offload configuration is valid.
128 * Pointer to Ethernet device.
130 * Per-queue offloads configuration.
133 * 1 if the configuration is valid, 0 otherwise.
136 mlx5_is_tx_queue_offloads_allowed(struct rte_eth_dev *dev, uint64_t offloads)
138 uint64_t port_offloads = dev->data->dev_conf.txmode.offloads;
139 uint64_t port_supp_offloads = mlx5_get_tx_port_offloads(dev);
141 /* There are no Tx offloads which are per queue. */
142 if ((offloads & port_supp_offloads) != offloads)
144 if ((port_offloads ^ offloads) & port_supp_offloads)
150 * DPDK callback to configure a TX queue.
153 * Pointer to Ethernet device structure.
157 * Number of descriptors to configure in queue.
159 * NUMA socket on which memory must be allocated.
161 * Thresholds parameters.
164 * 0 on success, negative errno value on failure.
167 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
168 unsigned int socket, const struct rte_eth_txconf *conf)
170 struct priv *priv = dev->data->dev_private;
171 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
172 struct mlx5_txq_ctrl *txq_ctrl =
173 container_of(txq, struct mlx5_txq_ctrl, txq);
177 * Don't verify port offloads for application which
180 if (!!(conf->txq_flags & ETH_TXQ_FLAGS_IGNORE) &&
181 !mlx5_is_tx_queue_offloads_allowed(dev, conf->offloads)) {
183 ERROR("%p: Tx queue offloads 0x%" PRIx64 " don't match port "
184 "offloads 0x%" PRIx64 " or supported offloads 0x%" PRIx64,
185 (void *)dev, conf->offloads,
186 dev->data->dev_conf.txmode.offloads,
187 mlx5_get_tx_port_offloads(dev));
190 if (desc <= MLX5_TX_COMP_THRESH) {
191 WARN("%p: number of descriptors requested for TX queue %u"
192 " must be higher than MLX5_TX_COMP_THRESH, using"
194 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
195 desc = MLX5_TX_COMP_THRESH + 1;
197 if (!rte_is_power_of_2(desc)) {
198 desc = 1 << log2above(desc);
199 WARN("%p: increased number of descriptors in TX queue %u"
200 " to the next power of two (%d)",
201 (void *)dev, idx, desc);
203 DEBUG("%p: configuring queue %u for %u descriptors",
204 (void *)dev, idx, desc);
205 if (idx >= priv->txqs_n) {
206 ERROR("%p: queue index out of range (%u >= %u)",
207 (void *)dev, idx, priv->txqs_n);
210 if (!mlx5_txq_releasable(dev, idx)) {
212 ERROR("%p: unable to release queue index %u",
216 mlx5_txq_release(dev, idx);
217 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
219 ERROR("%p: unable to allocate queue index %u",
224 DEBUG("%p: adding TX queue %p to list",
225 (void *)dev, (void *)txq_ctrl);
226 (*priv->txqs)[idx] = &txq_ctrl->txq;
232 * DPDK callback to release a TX queue.
235 * Generic TX queue pointer.
238 mlx5_tx_queue_release(void *dpdk_txq)
240 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
241 struct mlx5_txq_ctrl *txq_ctrl;
247 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
248 priv = txq_ctrl->priv;
249 for (i = 0; (i != priv->txqs_n); ++i)
250 if ((*priv->txqs)[i] == txq) {
251 DEBUG("%p: removing TX queue %p from list",
252 (void *)priv->dev, (void *)txq_ctrl);
253 mlx5_txq_release(priv->dev, i);
260 * Mmap TX UAR(HW doorbell) pages into reserved UAR address space.
261 * Both primary and secondary process do mmap to make UAR address
265 * Pointer to Ethernet device.
267 * Verbs file descriptor to map UAR pages.
270 * 0 on success, errno value on failure.
273 mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd)
275 struct priv *priv = dev->data->dev_private;
277 uintptr_t pages[priv->txqs_n];
278 unsigned int pages_n = 0;
283 struct mlx5_txq_data *txq;
284 struct mlx5_txq_ctrl *txq_ctrl;
286 size_t page_size = sysconf(_SC_PAGESIZE);
289 memset(pages, 0, priv->txqs_n * sizeof(uintptr_t));
291 * As rdma-core, UARs are mapped in size of OS page size.
292 * Use aligned address to avoid duplicate mmap.
293 * Ref to libmlx5 function: mlx5_init_context()
295 for (i = 0; i != priv->txqs_n; ++i) {
296 if (!(*priv->txqs)[i])
298 txq = (*priv->txqs)[i];
299 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
300 /* UAR addr form verbs used to find dup and offset in page. */
301 uar_va = (uintptr_t)txq_ctrl->bf_reg_orig;
302 off = uar_va & (page_size - 1); /* offset in page. */
303 uar_va = RTE_ALIGN_FLOOR(uar_va, page_size); /* page addr. */
305 for (j = 0; j != pages_n; ++j) {
306 if (pages[j] == uar_va) {
311 /* new address in reserved UAR address space. */
312 addr = RTE_PTR_ADD(priv->uar_base,
313 uar_va & (MLX5_UAR_SIZE - 1));
314 if (!already_mapped) {
315 pages[pages_n++] = uar_va;
316 /* fixed mmap to specified address in reserved
319 ret = mmap(addr, page_size,
320 PROT_WRITE, MAP_FIXED | MAP_SHARED, fd,
321 txq_ctrl->uar_mmap_offset);
323 /* fixed mmap have to return same address */
324 ERROR("call to mmap failed on UAR for txq %d\n",
330 if (rte_eal_process_type() == RTE_PROC_PRIMARY) /* save once */
331 txq_ctrl->txq.bf_reg = RTE_PTR_ADD((void *)addr, off);
333 assert(txq_ctrl->txq.bf_reg ==
334 RTE_PTR_ADD((void *)addr, off));
340 * Check if the burst function is using eMPW.
342 * @param tx_pkt_burst
343 * Tx burst function pointer.
346 * 1 if the burst function is using eMPW, 0 otherwise.
349 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst)
351 if (tx_pkt_burst == mlx5_tx_burst_raw_vec ||
352 tx_pkt_burst == mlx5_tx_burst_vec ||
353 tx_pkt_burst == mlx5_tx_burst_empw)
359 * Create the Tx queue Verbs object.
362 * Pointer to Ethernet device.
364 * Queue index in DPDK Rx queue array
367 * The Verbs object initialised if it can be created.
369 struct mlx5_txq_ibv *
370 mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
372 struct priv *priv = dev->data->dev_private;
373 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
374 struct mlx5_txq_ctrl *txq_ctrl =
375 container_of(txq_data, struct mlx5_txq_ctrl, txq);
376 struct mlx5_txq_ibv tmpl;
377 struct mlx5_txq_ibv *txq_ibv;
379 struct ibv_qp_init_attr_ex init;
380 struct ibv_cq_init_attr_ex cq;
381 struct ibv_qp_attr mod;
382 struct ibv_cq_ex cq_attr;
385 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
386 struct mlx5dv_cq cq_info;
387 struct mlx5dv_obj obj;
388 const int desc = 1 << txq_data->elts_n;
389 eth_tx_burst_t tx_pkt_burst = mlx5_select_tx_function(dev);
393 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
394 priv->verbs_alloc_ctx.obj = txq_ctrl;
395 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
396 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set");
399 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));
400 /* MRs will be registered in mp2mr[] later. */
401 attr.cq = (struct ibv_cq_init_attr_ex){
404 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
405 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
406 if (is_empw_burst_func(tx_pkt_burst))
407 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
408 tmpl.cq = mlx5_glue->create_cq(priv->ctx, cqe_n, NULL, NULL, 0);
409 if (tmpl.cq == NULL) {
410 ERROR("%p: CQ creation failure", (void *)txq_ctrl);
413 attr.init = (struct ibv_qp_init_attr_ex){
414 /* CQ to be associated with the send queue. */
416 /* CQ to be associated with the receive queue. */
419 /* Max number of outstanding WRs. */
421 ((priv->device_attr.orig_attr.max_qp_wr <
423 priv->device_attr.orig_attr.max_qp_wr :
426 * Max number of scatter/gather elements in a WR,
427 * must be 1 to prevent libmlx5 from trying to affect
428 * too much memory. TX gather is not impacted by the
429 * priv->device_attr.max_sge limit and will still work
434 .qp_type = IBV_QPT_RAW_PACKET,
436 * Do *NOT* enable this, completions events are managed per
441 .comp_mask = IBV_QP_INIT_ATTR_PD,
443 if (txq_data->max_inline)
444 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
445 if (txq_data->tso_en) {
446 attr.init.max_tso_header = txq_ctrl->max_tso_header;
447 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
449 tmpl.qp = mlx5_glue->create_qp_ex(priv->ctx, &attr.init);
450 if (tmpl.qp == NULL) {
451 ERROR("%p: QP creation failure", (void *)txq_ctrl);
454 attr.mod = (struct ibv_qp_attr){
455 /* Move the QP to this state. */
456 .qp_state = IBV_QPS_INIT,
457 /* Primary port number. */
458 .port_num = priv->port
460 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
461 (IBV_QP_STATE | IBV_QP_PORT));
463 ERROR("%p: QP state to IBV_QPS_INIT failed", (void *)txq_ctrl);
466 attr.mod = (struct ibv_qp_attr){
467 .qp_state = IBV_QPS_RTR
469 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
471 ERROR("%p: QP state to IBV_QPS_RTR failed", (void *)txq_ctrl);
474 attr.mod.qp_state = IBV_QPS_RTS;
475 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
477 ERROR("%p: QP state to IBV_QPS_RTS failed", (void *)txq_ctrl);
480 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,
483 ERROR("%p: cannot allocate memory", (void *)txq_ctrl);
487 obj.cq.out = &cq_info;
490 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
493 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
494 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
495 "it should be set to %u", RTE_CACHE_LINE_SIZE);
498 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
499 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
500 txq_data->wqes = qp.sq.buf;
501 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
502 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
503 txq_ctrl->bf_reg_orig = qp.bf.reg;
504 txq_data->cq_db = cq_info.dbrec;
506 (volatile struct mlx5_cqe (*)[])
507 (uintptr_t)cq_info.buf;
512 txq_data->wqe_ci = 0;
513 txq_data->wqe_pi = 0;
514 txq_ibv->qp = tmpl.qp;
515 txq_ibv->cq = tmpl.cq;
516 rte_atomic32_inc(&txq_ibv->refcnt);
517 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
518 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
520 ERROR("Failed to retrieve UAR info, invalid libmlx5.so version");
523 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)dev,
524 (void *)txq_ibv, rte_atomic32_read(&txq_ibv->refcnt));
525 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
526 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
530 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
532 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
533 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
538 * Get an Tx queue Verbs object.
541 * Pointer to Ethernet device.
543 * Queue index in DPDK Rx queue array
546 * The Verbs object if it exists.
548 struct mlx5_txq_ibv *
549 mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
551 struct priv *priv = dev->data->dev_private;
552 struct mlx5_txq_ctrl *txq_ctrl;
554 if (idx >= priv->txqs_n)
556 if (!(*priv->txqs)[idx])
558 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
560 rte_atomic32_inc(&txq_ctrl->ibv->refcnt);
561 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)dev,
562 (void *)txq_ctrl->ibv,
563 rte_atomic32_read(&txq_ctrl->ibv->refcnt));
565 return txq_ctrl->ibv;
569 * Release an Tx verbs queue object.
572 * Verbs Tx queue object.
575 * 1 while a reference on it exists, 0 when freed.
578 mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv)
581 DEBUG("Verbs Tx queue %p: refcnt %d",
582 (void *)txq_ibv, rte_atomic32_read(&txq_ibv->refcnt));
583 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {
584 claim_zero(mlx5_glue->destroy_qp(txq_ibv->qp));
585 claim_zero(mlx5_glue->destroy_cq(txq_ibv->cq));
586 LIST_REMOVE(txq_ibv, next);
594 * Return true if a single reference exists on the object.
597 * Verbs Tx queue object.
600 mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv)
603 return (rte_atomic32_read(&txq_ibv->refcnt) == 1);
607 * Verify the Verbs Tx queue list is empty
610 * Pointer to Ethernet device.
613 * The number of object not released.
616 mlx5_txq_ibv_verify(struct rte_eth_dev *dev)
618 struct priv *priv = dev->data->dev_private;
620 struct mlx5_txq_ibv *txq_ibv;
622 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) {
623 DEBUG("%p: Verbs Tx queue %p still referenced", (void *)dev,
631 * Set Tx queue parameters from device configuration.
634 * Pointer to Tx queue control structure.
637 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
639 struct priv *priv = txq_ctrl->priv;
640 struct mlx5_dev_config *config = &priv->config;
641 const unsigned int max_tso_inline =
642 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) /
643 RTE_CACHE_LINE_SIZE);
644 unsigned int txq_inline;
645 unsigned int txqs_inline;
646 unsigned int inline_max_packet_sz;
647 eth_tx_burst_t tx_pkt_burst =
648 mlx5_select_tx_function(txq_ctrl->priv->dev);
649 int is_empw_func = is_empw_burst_func(tx_pkt_burst);
650 int tso = !!(txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_TCP_TSO);
652 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ?
653 0 : config->txq_inline;
654 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ?
655 0 : config->txqs_inline;
656 inline_max_packet_sz =
657 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ?
658 0 : config->inline_max_packet_sz;
660 if (config->txq_inline == MLX5_ARG_UNSET)
661 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;
662 if (config->txqs_inline == MLX5_ARG_UNSET)
663 txqs_inline = MLX5_EMPW_MIN_TXQS;
664 if (config->inline_max_packet_sz == MLX5_ARG_UNSET)
665 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN;
666 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg;
667 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz;
669 if (txq_inline && priv->txqs_n >= txqs_inline) {
672 txq_ctrl->txq.max_inline =
673 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
674 RTE_CACHE_LINE_SIZE);
676 /* To minimize the size of data set, avoid requesting
679 txq_ctrl->max_inline_data =
680 ((RTE_MIN(txq_inline,
681 inline_max_packet_sz) +
682 (RTE_CACHE_LINE_SIZE - 1)) /
683 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
685 int inline_diff = txq_ctrl->txq.max_inline -
689 * Adjust inline value as Verbs aggregates
690 * tso_inline and txq_inline fields.
692 txq_ctrl->max_inline_data = inline_diff > 0 ?
694 RTE_CACHE_LINE_SIZE :
697 txq_ctrl->max_inline_data =
698 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE;
701 * Check if the inline size is too large in a way which
702 * can make the WQE DS to overflow.
703 * Considering in calculation:
708 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE);
709 if (ds_cnt > MLX5_DSEG_MAX) {
710 unsigned int max_inline = (MLX5_DSEG_MAX - 2) *
713 max_inline = max_inline - (max_inline %
714 RTE_CACHE_LINE_SIZE);
715 WARN("txq inline is too large (%d) setting it to "
716 "the maximum possible: %d\n",
717 txq_inline, max_inline);
718 txq_ctrl->txq.max_inline = max_inline /
723 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE;
724 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline,
726 txq_ctrl->txq.tso_en = 1;
728 txq_ctrl->txq.tunnel_en = config->tunnel_en;
732 * Create a DPDK Tx queue.
735 * Pointer to Ethernet device.
739 * Number of descriptors to configure in queue.
741 * NUMA socket on which memory must be allocated.
743 * Thresholds parameters.
746 * A DPDK queue object on success.
748 struct mlx5_txq_ctrl *
749 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
750 unsigned int socket, const struct rte_eth_txconf *conf)
752 struct priv *priv = dev->data->dev_private;
753 struct mlx5_txq_ctrl *tmpl;
755 tmpl = rte_calloc_socket("TXQ", 1,
757 desc * sizeof(struct rte_mbuf *),
761 assert(desc > MLX5_TX_COMP_THRESH);
762 tmpl->txq.offloads = conf->offloads;
764 tmpl->socket = socket;
765 tmpl->txq.elts_n = log2above(desc);
766 txq_set_params(tmpl);
767 /* MRs will be registered in mp2mr[] later. */
768 DEBUG("priv->device_attr.max_qp_wr is %d",
769 priv->device_attr.orig_attr.max_qp_wr);
770 DEBUG("priv->device_attr.max_sge is %d",
771 priv->device_attr.orig_attr.max_sge);
773 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1);
774 tmpl->txq.stats.idx = idx;
775 rte_atomic32_inc(&tmpl->refcnt);
776 DEBUG("%p: Tx queue %p: refcnt %d", (void *)dev,
777 (void *)tmpl, rte_atomic32_read(&tmpl->refcnt));
778 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
786 * Pointer to Ethernet device.
791 * A pointer to the queue if it exists.
793 struct mlx5_txq_ctrl *
794 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
796 struct priv *priv = dev->data->dev_private;
797 struct mlx5_txq_ctrl *ctrl = NULL;
799 if ((*priv->txqs)[idx]) {
800 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
804 mlx5_txq_ibv_get(dev, idx);
805 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
806 if (ctrl->txq.mp2mr[i])
809 ctrl->txq.mp2mr[i]->mp));
811 rte_atomic32_inc(&ctrl->refcnt);
812 DEBUG("%p: Tx queue %p: refcnt %d", (void *)dev,
813 (void *)ctrl, rte_atomic32_read(&ctrl->refcnt));
819 * Release a Tx queue.
822 * Pointer to Ethernet device.
827 * 1 while a reference on it exists, 0 when freed.
830 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
832 struct priv *priv = dev->data->dev_private;
834 struct mlx5_txq_ctrl *txq;
835 size_t page_size = sysconf(_SC_PAGESIZE);
837 if (!(*priv->txqs)[idx])
839 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
840 DEBUG("%p: Tx queue %p: refcnt %d", (void *)dev,
841 (void *)txq, rte_atomic32_read(&txq->refcnt));
842 if (txq->ibv && !mlx5_txq_ibv_release(txq->ibv))
844 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
845 if (txq->txq.mp2mr[i]) {
846 mlx5_mr_release(txq->txq.mp2mr[i]);
847 txq->txq.mp2mr[i] = NULL;
851 munmap((void *)RTE_ALIGN_FLOOR((uintptr_t)txq->txq.bf_reg,
852 page_size), page_size);
853 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
855 LIST_REMOVE(txq, next);
857 (*priv->txqs)[idx] = NULL;
864 * Verify if the queue can be released.
867 * Pointer to Ethernet device.
872 * 1 if the queue can be released.
875 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
877 struct priv *priv = dev->data->dev_private;
878 struct mlx5_txq_ctrl *txq;
880 if (!(*priv->txqs)[idx])
882 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
883 return (rte_atomic32_read(&txq->refcnt) == 1);
887 * Verify the Tx Queue list is empty
890 * Pointer to Ethernet device.
893 * The number of object not released.
896 mlx5_txq_verify(struct rte_eth_dev *dev)
898 struct priv *priv = dev->data->dev_private;
899 struct mlx5_txq_ctrl *txq;
902 LIST_FOREACH(txq, &priv->txqsctrl, next) {
903 DEBUG("%p: Tx Queue %p still referenced", (void *)dev,