1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <rte_malloc.h>
15 #include <ethdev_driver.h>
16 #include <rte_common.h>
17 #include <rte_eal_paging.h>
19 #include <mlx5_common.h>
20 #include <mlx5_common_mr.h>
21 #include <mlx5_malloc.h>
23 #include "mlx5_defs.h"
24 #include "mlx5_utils.h"
26 #include "mlx5_rxtx.h"
27 #include "mlx5_autoconf.h"
30 * Allocate TX queue elements.
33 * Pointer to TX queue structure.
36 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
38 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
41 for (i = 0; (i != elts_n); ++i)
42 txq_ctrl->txq.elts[i] = NULL;
43 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
44 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx, elts_n);
45 txq_ctrl->txq.elts_head = 0;
46 txq_ctrl->txq.elts_tail = 0;
47 txq_ctrl->txq.elts_comp = 0;
51 * Free TX queue elements.
54 * Pointer to TX queue structure.
57 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
59 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
60 const uint16_t elts_m = elts_n - 1;
61 uint16_t elts_head = txq_ctrl->txq.elts_head;
62 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
63 struct rte_mbuf *(*elts)[elts_n] = &txq_ctrl->txq.elts;
65 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs",
66 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx);
67 txq_ctrl->txq.elts_head = 0;
68 txq_ctrl->txq.elts_tail = 0;
69 txq_ctrl->txq.elts_comp = 0;
71 while (elts_tail != elts_head) {
72 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
74 MLX5_ASSERT(elt != NULL);
75 rte_pktmbuf_free_seg(elt);
76 #ifdef RTE_LIBRTE_MLX5_DEBUG
78 memset(&(*elts)[elts_tail & elts_m],
80 sizeof((*elts)[elts_tail & elts_m]));
87 * Returns the per-port supported offloads.
90 * Pointer to Ethernet device.
93 * Supported Tx offloads.
96 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
98 struct mlx5_priv *priv = dev->data->dev_private;
99 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
100 DEV_TX_OFFLOAD_VLAN_INSERT);
101 struct mlx5_dev_config *config = &priv->config;
104 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
105 DEV_TX_OFFLOAD_UDP_CKSUM |
106 DEV_TX_OFFLOAD_TCP_CKSUM);
108 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
110 offloads |= DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP;
113 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
115 offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
116 DEV_TX_OFFLOAD_UDP_TNL_TSO);
118 if (config->tunnel_en) {
120 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
122 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
123 DEV_TX_OFFLOAD_GRE_TNL_TSO |
124 DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
126 if (!config->mprq.enabled)
127 offloads |= DEV_TX_OFFLOAD_MBUF_FAST_FREE;
131 /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */
133 txq_sync_cq(struct mlx5_txq_data *txq)
135 volatile struct mlx5_cqe *cqe;
140 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
141 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
142 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
143 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
144 /* No new CQEs in completion queue. */
145 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
151 /* Move all CQEs to HW ownership. */
152 for (i = 0; i < txq->cqe_s; i++) {
154 cqe->op_own = MLX5_CQE_INVALIDATE;
156 /* Resync CQE and WQE (WQ in reset state). */
158 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
159 txq->cq_pi = txq->cq_ci;
164 * Tx queue stop. Device queue goes to the idle state,
165 * all involved mbufs are freed from elts/WQ.
168 * Pointer to Ethernet device structure.
173 * 0 on success, a negative errno value otherwise and rte_errno is set.
176 mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t idx)
178 struct mlx5_priv *priv = dev->data->dev_private;
179 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
180 struct mlx5_txq_ctrl *txq_ctrl =
181 container_of(txq, struct mlx5_txq_ctrl, txq);
184 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
185 /* Move QP to RESET state. */
186 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj, MLX5_TXQ_MOD_RDY2RST,
187 (uint8_t)priv->dev_port);
190 /* Handle all send completions. */
192 /* Free elts stored in the SQ. */
193 txq_free_elts(txq_ctrl);
194 /* Prevent writing new pkts to SQ by setting no free WQE.*/
195 txq->wqe_ci = txq->wqe_s;
198 /* Set the actual queue state. */
199 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
204 * Tx queue stop. Device queue goes to the idle state,
205 * all involved mbufs are freed from elts/WQ.
208 * Pointer to Ethernet device structure.
213 * 0 on success, a negative errno value otherwise and rte_errno is set.
216 mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t idx)
220 if (rte_eth_dev_is_tx_hairpin_queue(dev, idx)) {
221 DRV_LOG(ERR, "Hairpin queue can't be stopped");
225 if (dev->data->tx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STOPPED)
227 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
228 ret = mlx5_mp_os_req_queue_control(dev, idx,
229 MLX5_MP_REQ_QUEUE_TX_STOP);
231 ret = mlx5_tx_queue_stop_primary(dev, idx);
237 * Rx queue start. Device queue goes to the ready state,
238 * all required mbufs are allocated and WQ is replenished.
241 * Pointer to Ethernet device structure.
246 * 0 on success, a negative errno value otherwise and rte_errno is set.
249 mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t idx)
251 struct mlx5_priv *priv = dev->data->dev_private;
252 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
253 struct mlx5_txq_ctrl *txq_ctrl =
254 container_of(txq, struct mlx5_txq_ctrl, txq);
257 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
258 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj,
259 MLX5_TXQ_MOD_RST2RDY,
260 (uint8_t)priv->dev_port);
263 txq_ctrl->txq.wqe_ci = 0;
264 txq_ctrl->txq.wqe_pi = 0;
265 txq_ctrl->txq.elts_comp = 0;
266 /* Set the actual queue state. */
267 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
272 * Rx queue start. Device queue goes to the ready state,
273 * all required mbufs are allocated and WQ is replenished.
276 * Pointer to Ethernet device structure.
281 * 0 on success, a negative errno value otherwise and rte_errno is set.
284 mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t idx)
288 if (rte_eth_dev_is_tx_hairpin_queue(dev, idx)) {
289 DRV_LOG(ERR, "Hairpin queue can't be started");
293 if (dev->data->tx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STARTED)
295 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
296 ret = mlx5_mp_os_req_queue_control(dev, idx,
297 MLX5_MP_REQ_QUEUE_TX_START);
299 ret = mlx5_tx_queue_start_primary(dev, idx);
305 * Tx queue presetup checks.
308 * Pointer to Ethernet device structure.
312 * Number of descriptors to configure in queue.
315 * 0 on success, a negative errno value otherwise and rte_errno is set.
318 mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
320 struct mlx5_priv *priv = dev->data->dev_private;
322 if (*desc <= MLX5_TX_COMP_THRESH) {
324 "port %u number of descriptors requested for Tx queue"
325 " %u must be higher than MLX5_TX_COMP_THRESH, using %u"
326 " instead of %u", dev->data->port_id, idx,
327 MLX5_TX_COMP_THRESH + 1, *desc);
328 *desc = MLX5_TX_COMP_THRESH + 1;
330 if (!rte_is_power_of_2(*desc)) {
331 *desc = 1 << log2above(*desc);
333 "port %u increased number of descriptors in Tx queue"
334 " %u to the next power of two (%d)",
335 dev->data->port_id, idx, *desc);
337 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors",
338 dev->data->port_id, idx, *desc);
339 if (idx >= priv->txqs_n) {
340 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)",
341 dev->data->port_id, idx, priv->txqs_n);
342 rte_errno = EOVERFLOW;
345 if (!mlx5_txq_releasable(dev, idx)) {
347 DRV_LOG(ERR, "port %u unable to release queue index %u",
348 dev->data->port_id, idx);
351 mlx5_txq_release(dev, idx);
356 * DPDK callback to configure a TX queue.
359 * Pointer to Ethernet device structure.
363 * Number of descriptors to configure in queue.
365 * NUMA socket on which memory must be allocated.
367 * Thresholds parameters.
370 * 0 on success, a negative errno value otherwise and rte_errno is set.
373 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
374 unsigned int socket, const struct rte_eth_txconf *conf)
376 struct mlx5_priv *priv = dev->data->dev_private;
377 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
378 struct mlx5_txq_ctrl *txq_ctrl =
379 container_of(txq, struct mlx5_txq_ctrl, txq);
382 res = mlx5_tx_queue_pre_setup(dev, idx, &desc);
385 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
387 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
388 dev->data->port_id, idx);
391 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
392 dev->data->port_id, idx);
393 (*priv->txqs)[idx] = &txq_ctrl->txq;
398 * DPDK callback to configure a TX hairpin queue.
401 * Pointer to Ethernet device structure.
405 * Number of descriptors to configure in queue.
406 * @param[in] hairpin_conf
407 * The hairpin binding configuration.
410 * 0 on success, a negative errno value otherwise and rte_errno is set.
413 mlx5_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
415 const struct rte_eth_hairpin_conf *hairpin_conf)
417 struct mlx5_priv *priv = dev->data->dev_private;
418 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
419 struct mlx5_txq_ctrl *txq_ctrl =
420 container_of(txq, struct mlx5_txq_ctrl, txq);
423 res = mlx5_tx_queue_pre_setup(dev, idx, &desc);
426 if (hairpin_conf->peer_count != 1) {
428 DRV_LOG(ERR, "port %u unable to setup Tx hairpin queue index %u"
429 " peer count is %u", dev->data->port_id,
430 idx, hairpin_conf->peer_count);
433 if (hairpin_conf->peers[0].port == dev->data->port_id) {
434 if (hairpin_conf->peers[0].queue >= priv->rxqs_n) {
436 DRV_LOG(ERR, "port %u unable to setup Tx hairpin queue"
437 " index %u, Rx %u is larger than %u",
438 dev->data->port_id, idx,
439 hairpin_conf->peers[0].queue, priv->txqs_n);
443 if (hairpin_conf->manual_bind == 0 ||
444 hairpin_conf->tx_explicit == 0) {
446 DRV_LOG(ERR, "port %u unable to setup Tx hairpin queue"
447 " index %u peer port %u with attributes %u %u",
448 dev->data->port_id, idx,
449 hairpin_conf->peers[0].port,
450 hairpin_conf->manual_bind,
451 hairpin_conf->tx_explicit);
455 txq_ctrl = mlx5_txq_hairpin_new(dev, idx, desc, hairpin_conf);
457 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
458 dev->data->port_id, idx);
461 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
462 dev->data->port_id, idx);
463 (*priv->txqs)[idx] = &txq_ctrl->txq;
464 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;
469 * DPDK callback to release a TX queue.
472 * Generic TX queue pointer.
475 mlx5_tx_queue_release(void *dpdk_txq)
477 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
478 struct mlx5_txq_ctrl *txq_ctrl;
479 struct mlx5_priv *priv;
484 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
485 priv = txq_ctrl->priv;
486 for (i = 0; (i != priv->txqs_n); ++i)
487 if ((*priv->txqs)[i] == txq) {
488 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
489 PORT_ID(priv), txq->idx);
490 mlx5_txq_release(ETH_DEV(priv), i);
496 * Configure the doorbell register non-cached attribute.
499 * Pointer to Tx queue control structure.
504 txq_uar_ncattr_init(struct mlx5_txq_ctrl *txq_ctrl, size_t page_size)
506 struct mlx5_priv *priv = txq_ctrl->priv;
509 txq_ctrl->txq.db_heu = priv->config.dbnc == MLX5_TXDB_HEURISTIC;
510 txq_ctrl->txq.db_nc = 0;
511 /* Check the doorbell register mapping type. */
512 cmd = txq_ctrl->uar_mmap_offset / page_size;
513 cmd >>= MLX5_UAR_MMAP_CMD_SHIFT;
514 cmd &= MLX5_UAR_MMAP_CMD_MASK;
515 if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD)
516 txq_ctrl->txq.db_nc = 1;
520 * Initialize Tx UAR registers for primary process.
523 * Pointer to Tx queue control structure.
526 txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
528 struct mlx5_priv *priv = txq_ctrl->priv;
529 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
531 unsigned int lock_idx;
533 const size_t page_size = rte_mem_page_size();
534 if (page_size == (size_t)-1) {
535 DRV_LOG(ERR, "Failed to get mem page size");
539 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
541 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
543 ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
544 txq_uar_ncattr_init(txq_ctrl, page_size);
546 /* Assign an UAR lock according to UAR page number */
547 lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
548 MLX5_UAR_PAGE_NUM_MASK;
549 txq_ctrl->txq.uar_lock = &priv->sh->uar_lock[lock_idx];
554 * Remap UAR register of a Tx queue for secondary process.
556 * Remapped address is stored at the table in the process private structure of
557 * the device, indexed by queue index.
560 * Pointer to Tx queue control structure.
562 * Verbs file descriptor to map UAR pages.
565 * 0 on success, a negative errno value otherwise and rte_errno is set.
568 txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)
570 struct mlx5_priv *priv = txq_ctrl->priv;
571 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
572 struct mlx5_txq_data *txq = &txq_ctrl->txq;
576 const size_t page_size = rte_mem_page_size();
577 if (page_size == (size_t)-1) {
578 DRV_LOG(ERR, "Failed to get mem page size");
583 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
587 * As rdma-core, UARs are mapped in size of OS page
588 * size. Ref to libmlx5 function: mlx5_init_context()
590 uar_va = (uintptr_t)txq_ctrl->bf_reg;
591 offset = uar_va & (page_size - 1); /* Offset in page. */
592 addr = rte_mem_map(NULL, page_size, RTE_PROT_WRITE, RTE_MAP_SHARED,
593 fd, txq_ctrl->uar_mmap_offset);
596 "port %u mmap failed for BF reg of txq %u",
597 txq->port_id, txq->idx);
601 addr = RTE_PTR_ADD(addr, offset);
602 ppriv->uar_table[txq->idx] = addr;
603 txq_uar_ncattr_init(txq_ctrl, page_size);
608 * Unmap UAR register of a Tx queue for secondary process.
611 * Pointer to Tx queue control structure.
614 txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl)
616 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(txq_ctrl->priv));
618 const size_t page_size = rte_mem_page_size();
619 if (page_size == (size_t)-1) {
620 DRV_LOG(ERR, "Failed to get mem page size");
624 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
626 addr = ppriv->uar_table[txq_ctrl->txq.idx];
627 rte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
631 * Deinitialize Tx UAR registers for secondary process.
634 * Pointer to Ethernet device.
637 mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev)
639 struct mlx5_proc_priv *ppriv = (struct mlx5_proc_priv *)
640 dev->process_private;
641 const size_t page_size = rte_mem_page_size();
645 if (page_size == (size_t)-1) {
646 DRV_LOG(ERR, "Failed to get mem page size");
649 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);
650 for (i = 0; i != ppriv->uar_table_sz; ++i) {
651 if (!ppriv->uar_table[i])
653 addr = ppriv->uar_table[i];
654 rte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
660 * Initialize Tx UAR registers for secondary process.
663 * Pointer to Ethernet device.
665 * Verbs file descriptor to map UAR pages.
668 * 0 on success, a negative errno value otherwise and rte_errno is set.
671 mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd)
673 struct mlx5_priv *priv = dev->data->dev_private;
674 struct mlx5_txq_data *txq;
675 struct mlx5_txq_ctrl *txq_ctrl;
679 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);
680 for (i = 0; i != priv->txqs_n; ++i) {
681 if (!(*priv->txqs)[i])
683 txq = (*priv->txqs)[i];
684 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
685 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
687 MLX5_ASSERT(txq->idx == (uint16_t)i);
688 ret = txq_uar_init_secondary(txq_ctrl, fd);
696 if (!(*priv->txqs)[i])
698 txq = (*priv->txqs)[i];
699 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
700 txq_uar_uninit_secondary(txq_ctrl);
706 * Verify the Verbs Tx queue list is empty
709 * Pointer to Ethernet device.
712 * The number of object not released.
715 mlx5_txq_obj_verify(struct rte_eth_dev *dev)
717 struct mlx5_priv *priv = dev->data->dev_private;
719 struct mlx5_txq_obj *txq_obj;
721 LIST_FOREACH(txq_obj, &priv->txqsobj, next) {
722 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced",
723 dev->data->port_id, txq_obj->txq_ctrl->txq.idx);
730 * Calculate the total number of WQEBB for Tx queue.
732 * Simplified version of calc_sq_size() in rdma-core.
735 * Pointer to Tx queue control structure.
738 * The number of WQEBB.
741 txq_calc_wqebb_cnt(struct mlx5_txq_ctrl *txq_ctrl)
743 unsigned int wqe_size;
744 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
746 wqe_size = MLX5_WQE_CSEG_SIZE +
749 MLX5_ESEG_MIN_INLINE_SIZE +
750 txq_ctrl->max_inline_data;
751 return rte_align32pow2(wqe_size * desc) / MLX5_WQE_SIZE;
755 * Calculate the maximal inline data size for Tx queue.
758 * Pointer to Tx queue control structure.
761 * The maximal inline data size.
764 txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl)
766 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
767 struct mlx5_priv *priv = txq_ctrl->priv;
768 unsigned int wqe_size;
770 wqe_size = priv->sh->device_attr.max_qp_wr / desc;
774 * This calculation is derived from tthe source of
775 * mlx5_calc_send_wqe() in rdma_core library.
777 wqe_size = wqe_size * MLX5_WQE_SIZE -
782 MLX5_DSEG_MIN_INLINE_SIZE;
787 * Set Tx queue parameters from device configuration.
790 * Pointer to Tx queue control structure.
793 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
795 struct mlx5_priv *priv = txq_ctrl->priv;
796 struct mlx5_dev_config *config = &priv->config;
797 unsigned int inlen_send; /* Inline data for ordinary SEND.*/
798 unsigned int inlen_empw; /* Inline data for enhanced MPW. */
799 unsigned int inlen_mode; /* Minimal required Inline data. */
800 unsigned int txqs_inline; /* Min Tx queues to enable inline. */
801 uint64_t dev_txoff = priv->dev_data->dev_conf.txmode.offloads;
802 bool tso = txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO |
803 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
804 DEV_TX_OFFLOAD_GRE_TNL_TSO |
805 DEV_TX_OFFLOAD_IP_TNL_TSO |
806 DEV_TX_OFFLOAD_UDP_TNL_TSO);
810 txq_ctrl->txq.fast_free =
811 !!((txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
812 !(txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_MULTI_SEGS) &&
813 !config->mprq.enabled);
814 if (config->txqs_inline == MLX5_ARG_UNSET)
816 #if defined(RTE_ARCH_ARM64)
817 (priv->pci_dev->id.device_id ==
818 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) ?
819 MLX5_INLINE_MAX_TXQS_BLUEFIELD :
821 MLX5_INLINE_MAX_TXQS;
823 txqs_inline = (unsigned int)config->txqs_inline;
824 inlen_send = (config->txq_inline_max == MLX5_ARG_UNSET) ?
825 MLX5_SEND_DEF_INLINE_LEN :
826 (unsigned int)config->txq_inline_max;
827 inlen_empw = (config->txq_inline_mpw == MLX5_ARG_UNSET) ?
828 MLX5_EMPW_DEF_INLINE_LEN :
829 (unsigned int)config->txq_inline_mpw;
830 inlen_mode = (config->txq_inline_min == MLX5_ARG_UNSET) ?
831 0 : (unsigned int)config->txq_inline_min;
832 if (config->mps != MLX5_MPW_ENHANCED && config->mps != MLX5_MPW)
835 * If there is requested minimal amount of data to inline
836 * we MUST enable inlining. This is a case for ConnectX-4
837 * which usually requires L2 inlined for correct operating
838 * and ConnectX-4 Lx which requires L2-L4 inlined to
839 * support E-Switch Flows.
842 if (inlen_mode <= MLX5_ESEG_MIN_INLINE_SIZE) {
844 * Optimize minimal inlining for single
845 * segment packets to fill one WQEBB
848 temp = MLX5_ESEG_MIN_INLINE_SIZE;
850 temp = inlen_mode - MLX5_ESEG_MIN_INLINE_SIZE;
851 temp = RTE_ALIGN(temp, MLX5_WSEG_SIZE) +
852 MLX5_ESEG_MIN_INLINE_SIZE;
853 temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN);
855 if (temp != inlen_mode) {
857 "port %u minimal required inline setting"
858 " aligned from %u to %u",
859 PORT_ID(priv), inlen_mode, temp);
864 * If port is configured to support VLAN insertion and device
865 * does not support this feature by HW (for NICs before ConnectX-5
866 * or in case of wqe_vlan_insert flag is not set) we must enable
867 * data inline on all queues because it is supported by single
870 txq_ctrl->txq.vlan_en = config->hw_vlan_insert;
871 vlan_inline = (dev_txoff & DEV_TX_OFFLOAD_VLAN_INSERT) &&
872 !config->hw_vlan_insert;
874 * If there are few Tx queues it is prioritized
875 * to save CPU cycles and disable data inlining at all.
877 if (inlen_send && priv->txqs_n >= txqs_inline) {
879 * The data sent with ordinal MLX5_OPCODE_SEND
880 * may be inlined in Ethernet Segment, align the
881 * length accordingly to fit entire WQEBBs.
883 temp = RTE_MAX(inlen_send,
884 MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE);
885 temp -= MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE;
886 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE);
887 temp += MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE;
888 temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX +
889 MLX5_ESEG_MIN_INLINE_SIZE -
892 MLX5_WQE_DSEG_SIZE * 2);
893 temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN);
894 temp = RTE_MAX(temp, inlen_mode);
895 if (temp != inlen_send) {
897 "port %u ordinary send inline setting"
898 " aligned from %u to %u",
899 PORT_ID(priv), inlen_send, temp);
903 * Not aligned to cache lines, but to WQEs.
904 * First bytes of data (initial alignment)
905 * is going to be copied explicitly at the
906 * beginning of inlining buffer in Ethernet
909 MLX5_ASSERT(inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
910 MLX5_ASSERT(inlen_send <= MLX5_WQE_SIZE_MAX +
911 MLX5_ESEG_MIN_INLINE_SIZE -
914 MLX5_WQE_DSEG_SIZE * 2);
915 } else if (inlen_mode) {
917 * If minimal inlining is requested we must
918 * enable inlining in general, despite the
919 * number of configured queues. Ignore the
920 * txq_inline_max devarg, this is not
921 * full-featured inline.
923 inlen_send = inlen_mode;
925 } else if (vlan_inline) {
927 * Hardware does not report offload for
928 * VLAN insertion, we must enable data inline
929 * to implement feature by software.
931 inlen_send = MLX5_ESEG_MIN_INLINE_SIZE;
937 txq_ctrl->txq.inlen_send = inlen_send;
938 txq_ctrl->txq.inlen_mode = inlen_mode;
939 txq_ctrl->txq.inlen_empw = 0;
940 if (inlen_send && inlen_empw && priv->txqs_n >= txqs_inline) {
942 * The data sent with MLX5_OPCODE_ENHANCED_MPSW
943 * may be inlined in Data Segment, align the
944 * length accordingly to fit entire WQEBBs.
946 temp = RTE_MAX(inlen_empw,
947 MLX5_WQE_SIZE + MLX5_DSEG_MIN_INLINE_SIZE);
948 temp -= MLX5_DSEG_MIN_INLINE_SIZE;
949 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE);
950 temp += MLX5_DSEG_MIN_INLINE_SIZE;
951 temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX +
952 MLX5_DSEG_MIN_INLINE_SIZE -
956 temp = RTE_MIN(temp, MLX5_EMPW_MAX_INLINE_LEN);
957 if (temp != inlen_empw) {
959 "port %u enhanced empw inline setting"
960 " aligned from %u to %u",
961 PORT_ID(priv), inlen_empw, temp);
964 MLX5_ASSERT(inlen_empw >= MLX5_ESEG_MIN_INLINE_SIZE);
965 MLX5_ASSERT(inlen_empw <= MLX5_WQE_SIZE_MAX +
966 MLX5_DSEG_MIN_INLINE_SIZE -
970 txq_ctrl->txq.inlen_empw = inlen_empw;
972 txq_ctrl->max_inline_data = RTE_MAX(inlen_send, inlen_empw);
974 txq_ctrl->max_tso_header = MLX5_MAX_TSO_HEADER;
975 txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->max_inline_data,
976 MLX5_MAX_TSO_HEADER);
977 txq_ctrl->txq.tso_en = 1;
979 txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
980 txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
981 DEV_TX_OFFLOAD_UDP_TNL_TSO |
982 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
983 txq_ctrl->txq.offloads) && config->swp;
987 * Adjust Tx queue data inline parameters for large queue sizes.
988 * The data inline feature requires multiple WQEs to fit the packets,
989 * and if the large amount of Tx descriptors is requested by application
990 * the total WQE amount may exceed the hardware capabilities. If the
991 * default inline setting are used we can try to adjust these ones and
992 * meet the hardware requirements and not exceed the queue size.
995 * Pointer to Tx queue control structure.
998 * Zero on success, otherwise the parameters can not be adjusted.
1001 txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)
1003 struct mlx5_priv *priv = txq_ctrl->priv;
1004 struct mlx5_dev_config *config = &priv->config;
1005 unsigned int max_inline;
1007 max_inline = txq_calc_inline_max(txq_ctrl);
1008 if (!txq_ctrl->txq.inlen_send) {
1010 * Inline data feature is not engaged at all.
1011 * There is nothing to adjust.
1015 if (txq_ctrl->max_inline_data <= max_inline) {
1017 * The requested inline data length does not
1018 * exceed queue capabilities.
1022 if (txq_ctrl->txq.inlen_mode > max_inline) {
1024 "minimal data inline requirements (%u) are not"
1025 " satisfied (%u) on port %u, try the smaller"
1026 " Tx queue size (%d)",
1027 txq_ctrl->txq.inlen_mode, max_inline,
1028 priv->dev_data->port_id,
1029 priv->sh->device_attr.max_qp_wr);
1032 if (txq_ctrl->txq.inlen_send > max_inline &&
1033 config->txq_inline_max != MLX5_ARG_UNSET &&
1034 config->txq_inline_max > (int)max_inline) {
1036 "txq_inline_max requirements (%u) are not"
1037 " satisfied (%u) on port %u, try the smaller"
1038 " Tx queue size (%d)",
1039 txq_ctrl->txq.inlen_send, max_inline,
1040 priv->dev_data->port_id,
1041 priv->sh->device_attr.max_qp_wr);
1044 if (txq_ctrl->txq.inlen_empw > max_inline &&
1045 config->txq_inline_mpw != MLX5_ARG_UNSET &&
1046 config->txq_inline_mpw > (int)max_inline) {
1048 "txq_inline_mpw requirements (%u) are not"
1049 " satisfied (%u) on port %u, try the smaller"
1050 " Tx queue size (%d)",
1051 txq_ctrl->txq.inlen_empw, max_inline,
1052 priv->dev_data->port_id,
1053 priv->sh->device_attr.max_qp_wr);
1056 if (txq_ctrl->txq.tso_en && max_inline < MLX5_MAX_TSO_HEADER) {
1058 "tso header inline requirements (%u) are not"
1059 " satisfied (%u) on port %u, try the smaller"
1060 " Tx queue size (%d)",
1061 MLX5_MAX_TSO_HEADER, max_inline,
1062 priv->dev_data->port_id,
1063 priv->sh->device_attr.max_qp_wr);
1066 if (txq_ctrl->txq.inlen_send > max_inline) {
1068 "adjust txq_inline_max (%u->%u)"
1069 " due to large Tx queue on port %u",
1070 txq_ctrl->txq.inlen_send, max_inline,
1071 priv->dev_data->port_id);
1072 txq_ctrl->txq.inlen_send = max_inline;
1074 if (txq_ctrl->txq.inlen_empw > max_inline) {
1076 "adjust txq_inline_mpw (%u->%u)"
1077 "due to large Tx queue on port %u",
1078 txq_ctrl->txq.inlen_empw, max_inline,
1079 priv->dev_data->port_id);
1080 txq_ctrl->txq.inlen_empw = max_inline;
1082 txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->txq.inlen_send,
1083 txq_ctrl->txq.inlen_empw);
1084 MLX5_ASSERT(txq_ctrl->max_inline_data <= max_inline);
1085 MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= max_inline);
1086 MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send);
1087 MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw ||
1088 !txq_ctrl->txq.inlen_empw);
1096 * Create a DPDK Tx queue.
1099 * Pointer to Ethernet device.
1103 * Number of descriptors to configure in queue.
1105 * NUMA socket on which memory must be allocated.
1107 * Thresholds parameters.
1110 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1112 struct mlx5_txq_ctrl *
1113 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1114 unsigned int socket, const struct rte_eth_txconf *conf)
1116 struct mlx5_priv *priv = dev->data->dev_private;
1117 struct mlx5_txq_ctrl *tmpl;
1119 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) +
1120 desc * sizeof(struct rte_mbuf *), 0, socket);
1125 if (mlx5_mr_btree_init(&tmpl->txq.mr_ctrl.cache_bh,
1126 MLX5_MR_BTREE_CACHE_N, socket)) {
1127 /* rte_errno is already set. */
1130 /* Save pointer of global generation number to check memory event. */
1131 tmpl->txq.mr_ctrl.dev_gen_ptr = &priv->sh->share_cache.dev_gen;
1132 MLX5_ASSERT(desc > MLX5_TX_COMP_THRESH);
1133 tmpl->txq.offloads = conf->offloads |
1134 dev->data->dev_conf.txmode.offloads;
1136 tmpl->socket = socket;
1137 tmpl->txq.elts_n = log2above(desc);
1138 tmpl->txq.elts_s = desc;
1139 tmpl->txq.elts_m = desc - 1;
1140 tmpl->txq.port_id = dev->data->port_id;
1141 tmpl->txq.idx = idx;
1142 txq_set_params(tmpl);
1143 if (txq_adjust_params(tmpl))
1145 if (txq_calc_wqebb_cnt(tmpl) >
1146 priv->sh->device_attr.max_qp_wr) {
1148 "port %u Tx WQEBB count (%d) exceeds the limit (%d),"
1149 " try smaller queue size",
1150 dev->data->port_id, txq_calc_wqebb_cnt(tmpl),
1151 priv->sh->device_attr.max_qp_wr);
1155 __atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);
1156 tmpl->type = MLX5_TXQ_TYPE_STANDARD;
1157 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
1160 mlx5_mr_btree_free(&tmpl->txq.mr_ctrl.cache_bh);
1166 * Create a DPDK Tx hairpin queue.
1169 * Pointer to Ethernet device.
1173 * Number of descriptors to configure in queue.
1174 * @param hairpin_conf
1175 * The hairpin configuration.
1178 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1180 struct mlx5_txq_ctrl *
1181 mlx5_txq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1182 const struct rte_eth_hairpin_conf *hairpin_conf)
1184 struct mlx5_priv *priv = dev->data->dev_private;
1185 struct mlx5_txq_ctrl *tmpl;
1187 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1194 tmpl->socket = SOCKET_ID_ANY;
1195 tmpl->txq.elts_n = log2above(desc);
1196 tmpl->txq.port_id = dev->data->port_id;
1197 tmpl->txq.idx = idx;
1198 tmpl->hairpin_conf = *hairpin_conf;
1199 tmpl->type = MLX5_TXQ_TYPE_HAIRPIN;
1200 __atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);
1201 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
1209 * Pointer to Ethernet device.
1214 * A pointer to the queue if it exists.
1216 struct mlx5_txq_ctrl *
1217 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
1219 struct mlx5_priv *priv = dev->data->dev_private;
1220 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1221 struct mlx5_txq_ctrl *ctrl = NULL;
1224 ctrl = container_of(txq_data, struct mlx5_txq_ctrl, txq);
1225 __atomic_fetch_add(&ctrl->refcnt, 1, __ATOMIC_RELAXED);
1231 * Release a Tx queue.
1234 * Pointer to Ethernet device.
1239 * 1 while a reference on it exists, 0 when freed.
1242 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
1244 struct mlx5_priv *priv = dev->data->dev_private;
1245 struct mlx5_txq_ctrl *txq_ctrl;
1247 if (!(*priv->txqs)[idx])
1249 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
1250 if (__atomic_sub_fetch(&txq_ctrl->refcnt, 1, __ATOMIC_RELAXED) > 1)
1252 if (txq_ctrl->obj) {
1253 priv->obj_ops.txq_obj_release(txq_ctrl->obj);
1254 LIST_REMOVE(txq_ctrl->obj, next);
1255 mlx5_free(txq_ctrl->obj);
1256 txq_ctrl->obj = NULL;
1258 if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD) {
1259 if (txq_ctrl->txq.fcqs) {
1260 mlx5_free(txq_ctrl->txq.fcqs);
1261 txq_ctrl->txq.fcqs = NULL;
1263 txq_free_elts(txq_ctrl);
1264 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
1266 if (!__atomic_load_n(&txq_ctrl->refcnt, __ATOMIC_RELAXED)) {
1267 if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD)
1268 mlx5_mr_btree_free(&txq_ctrl->txq.mr_ctrl.cache_bh);
1269 LIST_REMOVE(txq_ctrl, next);
1270 mlx5_free(txq_ctrl);
1271 (*priv->txqs)[idx] = NULL;
1277 * Verify if the queue can be released.
1280 * Pointer to Ethernet device.
1285 * 1 if the queue can be released.
1288 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
1290 struct mlx5_priv *priv = dev->data->dev_private;
1291 struct mlx5_txq_ctrl *txq;
1293 if (!(*priv->txqs)[idx])
1295 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
1296 return (__atomic_load_n(&txq->refcnt, __ATOMIC_RELAXED) == 1);
1300 * Verify the Tx Queue list is empty
1303 * Pointer to Ethernet device.
1306 * The number of object not released.
1309 mlx5_txq_verify(struct rte_eth_dev *dev)
1311 struct mlx5_priv *priv = dev->data->dev_private;
1312 struct mlx5_txq_ctrl *txq_ctrl;
1315 LIST_FOREACH(txq_ctrl, &priv->txqsctrl, next) {
1316 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced",
1317 dev->data->port_id, txq_ctrl->txq.idx);
1324 * Set the Tx queue dynamic timestamp (mask and offset)
1327 * Pointer to the Ethernet device structure.
1330 mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev)
1332 struct mlx5_priv *priv = dev->data->dev_private;
1333 struct mlx5_dev_ctx_shared *sh = priv->sh;
1334 struct mlx5_txq_data *data;
1339 nbit = rte_mbuf_dynflag_lookup
1340 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
1341 off = rte_mbuf_dynfield_lookup
1342 (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL);
1343 if (nbit >= 0 && off >= 0 && sh->txpp.refcnt)
1344 mask = 1ULL << nbit;
1345 for (i = 0; i != priv->txqs_n; ++i) {
1346 data = (*priv->txqs)[i];
1350 data->ts_mask = mask;
1351 data->ts_offset = off;