1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
18 #pragma GCC diagnostic ignored "-Wpedantic"
20 #include <infiniband/verbs.h>
22 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_common.h>
30 #include "mlx5_utils.h"
31 #include "mlx5_defs.h"
33 #include "mlx5_rxtx.h"
34 #include "mlx5_autoconf.h"
35 #include "mlx5_glue.h"
38 * Allocate TX queue elements.
41 * Pointer to TX queue structure.
44 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
46 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
49 for (i = 0; (i != elts_n); ++i)
50 txq_ctrl->txq.elts[i] = NULL;
51 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
52 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx, elts_n);
53 txq_ctrl->txq.elts_head = 0;
54 txq_ctrl->txq.elts_tail = 0;
55 txq_ctrl->txq.elts_comp = 0;
59 * Free TX queue elements.
62 * Pointer to TX queue structure.
65 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
67 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
68 const uint16_t elts_m = elts_n - 1;
69 uint16_t elts_head = txq_ctrl->txq.elts_head;
70 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
71 struct rte_mbuf *(*elts)[elts_n] = &txq_ctrl->txq.elts;
73 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs",
74 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx);
75 txq_ctrl->txq.elts_head = 0;
76 txq_ctrl->txq.elts_tail = 0;
77 txq_ctrl->txq.elts_comp = 0;
79 while (elts_tail != elts_head) {
80 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
83 rte_pktmbuf_free_seg(elt);
86 memset(&(*elts)[elts_tail & elts_m],
88 sizeof((*elts)[elts_tail & elts_m]));
95 * Returns the per-port supported offloads.
98 * Pointer to Ethernet device.
101 * Supported Tx offloads.
104 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
106 struct mlx5_priv *priv = dev->data->dev_private;
107 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
108 DEV_TX_OFFLOAD_VLAN_INSERT);
109 struct mlx5_dev_config *config = &priv->config;
112 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
113 DEV_TX_OFFLOAD_UDP_CKSUM |
114 DEV_TX_OFFLOAD_TCP_CKSUM);
116 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
119 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
121 offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
122 DEV_TX_OFFLOAD_UDP_TNL_TSO);
124 if (config->tunnel_en) {
126 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
128 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
129 DEV_TX_OFFLOAD_GRE_TNL_TSO);
131 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
132 if (config->dv_flow_en)
133 offloads |= DEV_TX_OFFLOAD_MATCH_METADATA;
139 * Tx queue presetup checks.
142 * Pointer to Ethernet device structure.
146 * Number of descriptors to configure in queue.
149 * 0 on success, a negative errno value otherwise and rte_errno is set.
152 mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc)
154 struct mlx5_priv *priv = dev->data->dev_private;
156 if (desc <= MLX5_TX_COMP_THRESH) {
158 "port %u number of descriptors requested for Tx queue"
159 " %u must be higher than MLX5_TX_COMP_THRESH, using %u"
161 dev->data->port_id, idx, MLX5_TX_COMP_THRESH + 1, desc);
162 desc = MLX5_TX_COMP_THRESH + 1;
164 if (!rte_is_power_of_2(desc)) {
165 desc = 1 << log2above(desc);
167 "port %u increased number of descriptors in Tx queue"
168 " %u to the next power of two (%d)",
169 dev->data->port_id, idx, desc);
171 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors",
172 dev->data->port_id, idx, desc);
173 if (idx >= priv->txqs_n) {
174 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)",
175 dev->data->port_id, idx, priv->txqs_n);
176 rte_errno = EOVERFLOW;
179 if (!mlx5_txq_releasable(dev, idx)) {
181 DRV_LOG(ERR, "port %u unable to release queue index %u",
182 dev->data->port_id, idx);
185 mlx5_txq_release(dev, idx);
189 * DPDK callback to configure a TX queue.
192 * Pointer to Ethernet device structure.
196 * Number of descriptors to configure in queue.
198 * NUMA socket on which memory must be allocated.
200 * Thresholds parameters.
203 * 0 on success, a negative errno value otherwise and rte_errno is set.
206 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
207 unsigned int socket, const struct rte_eth_txconf *conf)
209 struct mlx5_priv *priv = dev->data->dev_private;
210 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
211 struct mlx5_txq_ctrl *txq_ctrl =
212 container_of(txq, struct mlx5_txq_ctrl, txq);
215 res = mlx5_tx_queue_pre_setup(dev, idx, desc);
218 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
220 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
221 dev->data->port_id, idx);
224 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
225 dev->data->port_id, idx);
226 (*priv->txqs)[idx] = &txq_ctrl->txq;
231 * DPDK callback to configure a TX hairpin queue.
234 * Pointer to Ethernet device structure.
238 * Number of descriptors to configure in queue.
239 * @param[in] hairpin_conf
240 * The hairpin binding configuration.
243 * 0 on success, a negative errno value otherwise and rte_errno is set.
246 mlx5_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
248 const struct rte_eth_hairpin_conf *hairpin_conf)
250 struct mlx5_priv *priv = dev->data->dev_private;
251 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
252 struct mlx5_txq_ctrl *txq_ctrl =
253 container_of(txq, struct mlx5_txq_ctrl, txq);
256 res = mlx5_tx_queue_pre_setup(dev, idx, desc);
259 if (hairpin_conf->peer_count != 1 ||
260 hairpin_conf->peers[0].port != dev->data->port_id ||
261 hairpin_conf->peers[0].queue >= priv->rxqs_n) {
262 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
263 " invalid hairpind configuration", dev->data->port_id,
268 txq_ctrl = mlx5_txq_hairpin_new(dev, idx, desc, hairpin_conf);
270 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
271 dev->data->port_id, idx);
274 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
275 dev->data->port_id, idx);
276 (*priv->txqs)[idx] = &txq_ctrl->txq;
277 txq_ctrl->type = MLX5_TXQ_TYPE_HAIRPIN;
282 * DPDK callback to release a TX queue.
285 * Generic TX queue pointer.
288 mlx5_tx_queue_release(void *dpdk_txq)
290 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
291 struct mlx5_txq_ctrl *txq_ctrl;
292 struct mlx5_priv *priv;
297 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
298 priv = txq_ctrl->priv;
299 for (i = 0; (i != priv->txqs_n); ++i)
300 if ((*priv->txqs)[i] == txq) {
301 mlx5_txq_release(ETH_DEV(priv), i);
302 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
303 PORT_ID(priv), txq->idx);
309 * Initialize Tx UAR registers for primary process.
312 * Pointer to Tx queue control structure.
315 txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
317 struct mlx5_priv *priv = txq_ctrl->priv;
318 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
320 unsigned int lock_idx;
321 const size_t page_size = sysconf(_SC_PAGESIZE);
324 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
326 assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
328 ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
330 /* Assign an UAR lock according to UAR page number */
331 lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
332 MLX5_UAR_PAGE_NUM_MASK;
333 txq_ctrl->txq.uar_lock = &priv->uar_lock[lock_idx];
338 * Remap UAR register of a Tx queue for secondary process.
340 * Remapped address is stored at the table in the process private structure of
341 * the device, indexed by queue index.
344 * Pointer to Tx queue control structure.
346 * Verbs file descriptor to map UAR pages.
349 * 0 on success, a negative errno value otherwise and rte_errno is set.
352 txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)
354 struct mlx5_priv *priv = txq_ctrl->priv;
355 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
356 struct mlx5_txq_data *txq = &txq_ctrl->txq;
360 const size_t page_size = sysconf(_SC_PAGESIZE);
362 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
366 * As rdma-core, UARs are mapped in size of OS page
367 * size. Ref to libmlx5 function: mlx5_init_context()
369 uar_va = (uintptr_t)txq_ctrl->bf_reg;
370 offset = uar_va & (page_size - 1); /* Offset in page. */
371 addr = mmap(NULL, page_size, PROT_WRITE, MAP_SHARED, fd,
372 txq_ctrl->uar_mmap_offset);
373 if (addr == MAP_FAILED) {
375 "port %u mmap failed for BF reg of txq %u",
376 txq->port_id, txq->idx);
380 addr = RTE_PTR_ADD(addr, offset);
381 ppriv->uar_table[txq->idx] = addr;
386 * Unmap UAR register of a Tx queue for secondary process.
389 * Pointer to Tx queue control structure.
392 txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl)
394 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(txq_ctrl->priv));
395 const size_t page_size = sysconf(_SC_PAGESIZE);
398 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
400 addr = ppriv->uar_table[txq_ctrl->txq.idx];
401 munmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
405 * Initialize Tx UAR registers for secondary process.
408 * Pointer to Ethernet device.
410 * Verbs file descriptor to map UAR pages.
413 * 0 on success, a negative errno value otherwise and rte_errno is set.
416 mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd)
418 struct mlx5_priv *priv = dev->data->dev_private;
419 struct mlx5_txq_data *txq;
420 struct mlx5_txq_ctrl *txq_ctrl;
424 assert(rte_eal_process_type() == RTE_PROC_SECONDARY);
425 for (i = 0; i != priv->txqs_n; ++i) {
426 if (!(*priv->txqs)[i])
428 txq = (*priv->txqs)[i];
429 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
430 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
432 assert(txq->idx == (uint16_t)i);
433 ret = txq_uar_init_secondary(txq_ctrl, fd);
441 if (!(*priv->txqs)[i])
443 txq = (*priv->txqs)[i];
444 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
445 txq_uar_uninit_secondary(txq_ctrl);
451 * Create the Tx hairpin queue object.
454 * Pointer to Ethernet device.
456 * Queue index in DPDK Tx queue array
459 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
461 static struct mlx5_txq_obj *
462 mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
464 struct mlx5_priv *priv = dev->data->dev_private;
465 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
466 struct mlx5_txq_ctrl *txq_ctrl =
467 container_of(txq_data, struct mlx5_txq_ctrl, txq);
468 struct mlx5_devx_create_sq_attr attr = { 0 };
469 struct mlx5_txq_obj *tmpl = NULL;
473 assert(!txq_ctrl->obj);
474 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
478 "port %u Tx queue %u cannot allocate memory resources",
479 dev->data->port_id, txq_data->idx);
483 tmpl->type = MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN;
484 tmpl->txq_ctrl = txq_ctrl;
487 /* Workaround for hairpin startup */
488 attr.wq_attr.log_hairpin_num_packets = log2above(32);
489 /* Workaround for packets larger than 1KB */
490 attr.wq_attr.log_hairpin_data_sz =
491 priv->config.hca_attr.log_max_hairpin_wq_data_sz;
492 attr.tis_num = priv->sh->tis->id;
493 tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->ctx, &attr);
496 "port %u tx hairpin queue %u can't create sq object",
497 dev->data->port_id, idx);
501 DRV_LOG(DEBUG, "port %u sxq %u updated with %p", dev->data->port_id,
503 rte_atomic32_inc(&tmpl->refcnt);
504 LIST_INSERT_HEAD(&priv->txqsobj, tmpl, next);
507 ret = rte_errno; /* Save rte_errno before cleanup. */
509 mlx5_devx_cmd_destroy(tmpl->tis);
511 mlx5_devx_cmd_destroy(tmpl->sq);
512 rte_errno = ret; /* Restore rte_errno. */
517 * Create the Tx queue Verbs object.
520 * Pointer to Ethernet device.
522 * Queue index in DPDK Tx queue array.
524 * Type of the Tx queue object to create.
527 * The Verbs object initialised, NULL otherwise and rte_errno is set.
529 struct mlx5_txq_obj *
530 mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
531 enum mlx5_txq_obj_type type)
533 struct mlx5_priv *priv = dev->data->dev_private;
534 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
535 struct mlx5_txq_ctrl *txq_ctrl =
536 container_of(txq_data, struct mlx5_txq_ctrl, txq);
537 struct mlx5_txq_obj tmpl;
538 struct mlx5_txq_obj *txq_obj = NULL;
540 struct ibv_qp_init_attr_ex init;
541 struct ibv_cq_init_attr_ex cq;
542 struct ibv_qp_attr mod;
545 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
546 struct mlx5dv_cq cq_info;
547 struct mlx5dv_obj obj;
548 const int desc = 1 << txq_data->elts_n;
551 if (type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN)
552 return mlx5_txq_obj_hairpin_new(dev, idx);
553 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
554 /* If using DevX, need additional mask to read tisn value. */
555 if (priv->config.devx && !priv->sh->tdn)
556 qp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;
559 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
560 priv->verbs_alloc_ctx.obj = txq_ctrl;
561 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
563 "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set",
568 memset(&tmpl, 0, sizeof(struct mlx5_txq_obj));
569 attr.cq = (struct ibv_cq_init_attr_ex){
572 cqe_n = desc / MLX5_TX_COMP_THRESH +
573 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
574 tmpl.cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);
575 if (tmpl.cq == NULL) {
576 DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
577 dev->data->port_id, idx);
581 attr.init = (struct ibv_qp_init_attr_ex){
582 /* CQ to be associated with the send queue. */
584 /* CQ to be associated with the receive queue. */
587 /* Max number of outstanding WRs. */
589 ((priv->sh->device_attr.orig_attr.max_qp_wr <
591 priv->sh->device_attr.orig_attr.max_qp_wr :
594 * Max number of scatter/gather elements in a WR,
595 * must be 1 to prevent libmlx5 from trying to affect
596 * too much memory. TX gather is not impacted by the
597 * device_attr.max_sge limit and will still work
602 .qp_type = IBV_QPT_RAW_PACKET,
604 * Do *NOT* enable this, completions events are managed per
609 .comp_mask = IBV_QP_INIT_ATTR_PD,
611 if (txq_data->inlen_send)
612 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
613 if (txq_data->tso_en) {
614 attr.init.max_tso_header = txq_ctrl->max_tso_header;
615 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
617 tmpl.qp = mlx5_glue->create_qp_ex(priv->sh->ctx, &attr.init);
618 if (tmpl.qp == NULL) {
619 DRV_LOG(ERR, "port %u Tx queue %u QP creation failure",
620 dev->data->port_id, idx);
624 attr.mod = (struct ibv_qp_attr){
625 /* Move the QP to this state. */
626 .qp_state = IBV_QPS_INIT,
627 /* IB device port number. */
628 .port_num = (uint8_t)priv->ibv_port,
630 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
631 (IBV_QP_STATE | IBV_QP_PORT));
634 "port %u Tx queue %u QP state to IBV_QPS_INIT failed",
635 dev->data->port_id, idx);
639 attr.mod = (struct ibv_qp_attr){
640 .qp_state = IBV_QPS_RTR
642 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
645 "port %u Tx queue %u QP state to IBV_QPS_RTR failed",
646 dev->data->port_id, idx);
650 attr.mod.qp_state = IBV_QPS_RTS;
651 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
654 "port %u Tx queue %u QP state to IBV_QPS_RTS failed",
655 dev->data->port_id, idx);
659 txq_obj = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_obj), 0,
662 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory",
663 dev->data->port_id, idx);
668 obj.cq.out = &cq_info;
671 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
676 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
678 "port %u wrong MLX5_CQE_SIZE environment variable"
679 " value: it should be set to %u",
680 dev->data->port_id, RTE_CACHE_LINE_SIZE);
684 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
685 txq_data->cqe_s = 1 << txq_data->cqe_n;
686 txq_data->cqe_m = txq_data->cqe_s - 1;
687 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
688 txq_data->wqes = qp.sq.buf;
689 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
690 txq_data->wqe_s = 1 << txq_data->wqe_n;
691 txq_data->wqe_m = txq_data->wqe_s - 1;
692 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
693 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
694 txq_data->cq_db = cq_info.dbrec;
695 txq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf;
700 txq_data->wqe_ci = 0;
701 txq_data->wqe_pi = 0;
702 txq_data->wqe_comp = 0;
703 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
704 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
706 * If using DevX need to query and store TIS transport domain value.
707 * This is done once per port.
708 * Will use this value on Rx, when creating matching TIR.
710 if (priv->config.devx && !priv->sh->tdn) {
711 ret = mlx5_devx_cmd_qp_query_tis_td(tmpl.qp, qp.tisn,
714 DRV_LOG(ERR, "Fail to query port %u Tx queue %u QP TIS "
715 "transport domain", dev->data->port_id, idx);
719 DRV_LOG(DEBUG, "port %u Tx queue %u TIS number %d "
720 "transport domain %d", dev->data->port_id,
721 idx, qp.tisn, priv->sh->tdn);
725 txq_obj->qp = tmpl.qp;
726 txq_obj->cq = tmpl.cq;
727 rte_atomic32_inc(&txq_obj->refcnt);
728 txq_ctrl->bf_reg = qp.bf.reg;
729 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
730 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
731 DRV_LOG(DEBUG, "port %u: uar_mmap_offset 0x%"PRIx64,
732 dev->data->port_id, txq_ctrl->uar_mmap_offset);
735 "port %u failed to retrieve UAR info, invalid"
741 txq_uar_init(txq_ctrl);
742 LIST_INSERT_HEAD(&priv->txqsobj, txq_obj, next);
743 txq_obj->txq_ctrl = txq_ctrl;
744 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
747 ret = rte_errno; /* Save rte_errno before cleanup. */
749 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
751 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
754 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
755 rte_errno = ret; /* Restore rte_errno. */
760 * Get an Tx queue Verbs object.
763 * Pointer to Ethernet device.
765 * Queue index in DPDK Tx queue array.
768 * The Verbs object if it exists.
770 struct mlx5_txq_obj *
771 mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
773 struct mlx5_priv *priv = dev->data->dev_private;
774 struct mlx5_txq_ctrl *txq_ctrl;
776 if (idx >= priv->txqs_n)
778 if (!(*priv->txqs)[idx])
780 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
782 rte_atomic32_inc(&txq_ctrl->obj->refcnt);
783 return txq_ctrl->obj;
787 * Release an Tx verbs queue object.
790 * Verbs Tx queue object.
793 * 1 while a reference on it exists, 0 when freed.
796 mlx5_txq_obj_release(struct mlx5_txq_obj *txq_obj)
799 if (rte_atomic32_dec_and_test(&txq_obj->refcnt)) {
800 if (txq_obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN) {
802 claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));
804 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
805 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
807 LIST_REMOVE(txq_obj, next);
815 * Verify the Verbs Tx queue list is empty
818 * Pointer to Ethernet device.
821 * The number of object not released.
824 mlx5_txq_obj_verify(struct rte_eth_dev *dev)
826 struct mlx5_priv *priv = dev->data->dev_private;
828 struct mlx5_txq_obj *txq_obj;
830 LIST_FOREACH(txq_obj, &priv->txqsobj, next) {
831 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced",
832 dev->data->port_id, txq_obj->txq_ctrl->txq.idx);
839 * Calculate the total number of WQEBB for Tx queue.
841 * Simplified version of calc_sq_size() in rdma-core.
844 * Pointer to Tx queue control structure.
847 * The number of WQEBB.
850 txq_calc_wqebb_cnt(struct mlx5_txq_ctrl *txq_ctrl)
852 unsigned int wqe_size;
853 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
855 wqe_size = MLX5_WQE_CSEG_SIZE +
858 MLX5_ESEG_MIN_INLINE_SIZE +
859 txq_ctrl->max_inline_data;
860 return rte_align32pow2(wqe_size * desc) / MLX5_WQE_SIZE;
864 * Calculate the maximal inline data size for Tx queue.
867 * Pointer to Tx queue control structure.
870 * The maximal inline data size.
873 txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl)
875 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
876 struct mlx5_priv *priv = txq_ctrl->priv;
877 unsigned int wqe_size;
879 wqe_size = priv->sh->device_attr.orig_attr.max_qp_wr / desc;
883 * This calculation is derived from tthe source of
884 * mlx5_calc_send_wqe() in rdma_core library.
886 wqe_size = wqe_size * MLX5_WQE_SIZE -
891 MLX5_DSEG_MIN_INLINE_SIZE;
896 * Set Tx queue parameters from device configuration.
899 * Pointer to Tx queue control structure.
902 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
904 struct mlx5_priv *priv = txq_ctrl->priv;
905 struct mlx5_dev_config *config = &priv->config;
906 unsigned int inlen_send; /* Inline data for ordinary SEND.*/
907 unsigned int inlen_empw; /* Inline data for enhanced MPW. */
908 unsigned int inlen_mode; /* Minimal required Inline data. */
909 unsigned int txqs_inline; /* Min Tx queues to enable inline. */
910 uint64_t dev_txoff = priv->dev_data->dev_conf.txmode.offloads;
911 bool tso = txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO |
912 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
913 DEV_TX_OFFLOAD_GRE_TNL_TSO |
914 DEV_TX_OFFLOAD_IP_TNL_TSO |
915 DEV_TX_OFFLOAD_UDP_TNL_TSO);
919 if (config->txqs_inline == MLX5_ARG_UNSET)
921 #if defined(RTE_ARCH_ARM64)
922 (priv->pci_dev->id.device_id ==
923 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) ?
924 MLX5_INLINE_MAX_TXQS_BLUEFIELD :
926 MLX5_INLINE_MAX_TXQS;
928 txqs_inline = (unsigned int)config->txqs_inline;
929 inlen_send = (config->txq_inline_max == MLX5_ARG_UNSET) ?
930 MLX5_SEND_DEF_INLINE_LEN :
931 (unsigned int)config->txq_inline_max;
932 inlen_empw = (config->txq_inline_mpw == MLX5_ARG_UNSET) ?
933 MLX5_EMPW_DEF_INLINE_LEN :
934 (unsigned int)config->txq_inline_mpw;
935 inlen_mode = (config->txq_inline_min == MLX5_ARG_UNSET) ?
936 0 : (unsigned int)config->txq_inline_min;
937 if (config->mps != MLX5_MPW_ENHANCED)
940 * If there is requested minimal amount of data to inline
941 * we MUST enable inlining. This is a case for ConnectX-4
942 * which usually requires L2 inlined for correct operating
943 * and ConnectX-4LX which requires L2-L4 inlined to
944 * support E-Switch Flows.
947 if (inlen_mode <= MLX5_ESEG_MIN_INLINE_SIZE) {
949 * Optimize minimal inlining for single
950 * segment packets to fill one WQEBB
953 temp = MLX5_ESEG_MIN_INLINE_SIZE;
955 temp = inlen_mode - MLX5_ESEG_MIN_INLINE_SIZE;
956 temp = RTE_ALIGN(temp, MLX5_WSEG_SIZE) +
957 MLX5_ESEG_MIN_INLINE_SIZE;
958 temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN);
960 if (temp != inlen_mode) {
962 "port %u minimal required inline setting"
963 " aligned from %u to %u",
964 PORT_ID(priv), inlen_mode, temp);
969 * If port is configured to support VLAN insertion and device
970 * does not support this feature by HW (for NICs before ConnectX-5
971 * or in case of wqe_vlan_insert flag is not set) we must enable
972 * data inline on all queues because it is supported by single
975 txq_ctrl->txq.vlan_en = config->hw_vlan_insert;
976 vlan_inline = (dev_txoff & DEV_TX_OFFLOAD_VLAN_INSERT) &&
977 !config->hw_vlan_insert;
979 * If there are few Tx queues it is prioritized
980 * to save CPU cycles and disable data inlining at all.
982 if (inlen_send && priv->txqs_n >= txqs_inline) {
984 * The data sent with ordinal MLX5_OPCODE_SEND
985 * may be inlined in Ethernet Segment, align the
986 * length accordingly to fit entire WQEBBs.
988 temp = RTE_MAX(inlen_send,
989 MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE);
990 temp -= MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE;
991 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE);
992 temp += MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE;
993 temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX +
994 MLX5_ESEG_MIN_INLINE_SIZE -
997 MLX5_WQE_DSEG_SIZE * 2);
998 temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN);
999 temp = RTE_MAX(temp, inlen_mode);
1000 if (temp != inlen_send) {
1002 "port %u ordinary send inline setting"
1003 " aligned from %u to %u",
1004 PORT_ID(priv), inlen_send, temp);
1008 * Not aligned to cache lines, but to WQEs.
1009 * First bytes of data (initial alignment)
1010 * is going to be copied explicitly at the
1011 * beginning of inlining buffer in Ethernet
1014 assert(inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
1015 assert(inlen_send <= MLX5_WQE_SIZE_MAX +
1016 MLX5_ESEG_MIN_INLINE_SIZE -
1017 MLX5_WQE_CSEG_SIZE -
1018 MLX5_WQE_ESEG_SIZE -
1019 MLX5_WQE_DSEG_SIZE * 2);
1020 } else if (inlen_mode) {
1022 * If minimal inlining is requested we must
1023 * enable inlining in general, despite the
1024 * number of configured queues. Ignore the
1025 * txq_inline_max devarg, this is not
1026 * full-featured inline.
1028 inlen_send = inlen_mode;
1030 } else if (vlan_inline) {
1032 * Hardware does not report offload for
1033 * VLAN insertion, we must enable data inline
1034 * to implement feature by software.
1036 inlen_send = MLX5_ESEG_MIN_INLINE_SIZE;
1042 txq_ctrl->txq.inlen_send = inlen_send;
1043 txq_ctrl->txq.inlen_mode = inlen_mode;
1044 txq_ctrl->txq.inlen_empw = 0;
1045 if (inlen_send && inlen_empw && priv->txqs_n >= txqs_inline) {
1047 * The data sent with MLX5_OPCODE_ENHANCED_MPSW
1048 * may be inlined in Data Segment, align the
1049 * length accordingly to fit entire WQEBBs.
1051 temp = RTE_MAX(inlen_empw,
1052 MLX5_WQE_SIZE + MLX5_DSEG_MIN_INLINE_SIZE);
1053 temp -= MLX5_DSEG_MIN_INLINE_SIZE;
1054 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE);
1055 temp += MLX5_DSEG_MIN_INLINE_SIZE;
1056 temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX +
1057 MLX5_DSEG_MIN_INLINE_SIZE -
1058 MLX5_WQE_CSEG_SIZE -
1059 MLX5_WQE_ESEG_SIZE -
1060 MLX5_WQE_DSEG_SIZE);
1061 temp = RTE_MIN(temp, MLX5_EMPW_MAX_INLINE_LEN);
1062 if (temp != inlen_empw) {
1064 "port %u enhanced empw inline setting"
1065 " aligned from %u to %u",
1066 PORT_ID(priv), inlen_empw, temp);
1069 assert(inlen_empw >= MLX5_ESEG_MIN_INLINE_SIZE);
1070 assert(inlen_empw <= MLX5_WQE_SIZE_MAX +
1071 MLX5_DSEG_MIN_INLINE_SIZE -
1072 MLX5_WQE_CSEG_SIZE -
1073 MLX5_WQE_ESEG_SIZE -
1074 MLX5_WQE_DSEG_SIZE);
1075 txq_ctrl->txq.inlen_empw = inlen_empw;
1077 txq_ctrl->max_inline_data = RTE_MAX(inlen_send, inlen_empw);
1079 txq_ctrl->max_tso_header = MLX5_MAX_TSO_HEADER;
1080 txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->max_inline_data,
1081 MLX5_MAX_TSO_HEADER);
1082 txq_ctrl->txq.tso_en = 1;
1084 txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
1085 txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
1086 DEV_TX_OFFLOAD_UDP_TNL_TSO |
1087 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
1088 txq_ctrl->txq.offloads) && config->swp;
1092 * Adjust Tx queue data inline parameters for large queue sizes.
1093 * The data inline feature requires multiple WQEs to fit the packets,
1094 * and if the large amount of Tx descriptors is requested by application
1095 * the total WQE amount may exceed the hardware capabilities. If the
1096 * default inline setting are used we can try to adjust these ones and
1097 * meet the hardware requirements and not exceed the queue size.
1100 * Pointer to Tx queue control structure.
1103 * Zero on success, otherwise the parameters can not be adjusted.
1106 txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)
1108 struct mlx5_priv *priv = txq_ctrl->priv;
1109 struct mlx5_dev_config *config = &priv->config;
1110 unsigned int max_inline;
1112 max_inline = txq_calc_inline_max(txq_ctrl);
1113 if (!txq_ctrl->txq.inlen_send) {
1115 * Inline data feature is not engaged at all.
1116 * There is nothing to adjust.
1120 if (txq_ctrl->max_inline_data <= max_inline) {
1122 * The requested inline data length does not
1123 * exceed queue capabilities.
1127 if (txq_ctrl->txq.inlen_mode > max_inline) {
1129 "minimal data inline requirements (%u) are not"
1130 " satisfied (%u) on port %u, try the smaller"
1131 " Tx queue size (%d)",
1132 txq_ctrl->txq.inlen_mode, max_inline,
1133 priv->dev_data->port_id,
1134 priv->sh->device_attr.orig_attr.max_qp_wr);
1137 if (txq_ctrl->txq.inlen_send > max_inline &&
1138 config->txq_inline_max != MLX5_ARG_UNSET &&
1139 config->txq_inline_max > (int)max_inline) {
1141 "txq_inline_max requirements (%u) are not"
1142 " satisfied (%u) on port %u, try the smaller"
1143 " Tx queue size (%d)",
1144 txq_ctrl->txq.inlen_send, max_inline,
1145 priv->dev_data->port_id,
1146 priv->sh->device_attr.orig_attr.max_qp_wr);
1149 if (txq_ctrl->txq.inlen_empw > max_inline &&
1150 config->txq_inline_mpw != MLX5_ARG_UNSET &&
1151 config->txq_inline_mpw > (int)max_inline) {
1153 "txq_inline_mpw requirements (%u) are not"
1154 " satisfied (%u) on port %u, try the smaller"
1155 " Tx queue size (%d)",
1156 txq_ctrl->txq.inlen_empw, max_inline,
1157 priv->dev_data->port_id,
1158 priv->sh->device_attr.orig_attr.max_qp_wr);
1161 if (txq_ctrl->txq.tso_en && max_inline < MLX5_MAX_TSO_HEADER) {
1163 "tso header inline requirements (%u) are not"
1164 " satisfied (%u) on port %u, try the smaller"
1165 " Tx queue size (%d)",
1166 MLX5_MAX_TSO_HEADER, max_inline,
1167 priv->dev_data->port_id,
1168 priv->sh->device_attr.orig_attr.max_qp_wr);
1171 if (txq_ctrl->txq.inlen_send > max_inline) {
1173 "adjust txq_inline_max (%u->%u)"
1174 " due to large Tx queue on port %u",
1175 txq_ctrl->txq.inlen_send, max_inline,
1176 priv->dev_data->port_id);
1177 txq_ctrl->txq.inlen_send = max_inline;
1179 if (txq_ctrl->txq.inlen_empw > max_inline) {
1181 "adjust txq_inline_mpw (%u->%u)"
1182 "due to large Tx queue on port %u",
1183 txq_ctrl->txq.inlen_empw, max_inline,
1184 priv->dev_data->port_id);
1185 txq_ctrl->txq.inlen_empw = max_inline;
1187 txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->txq.inlen_send,
1188 txq_ctrl->txq.inlen_empw);
1189 assert(txq_ctrl->max_inline_data <= max_inline);
1190 assert(txq_ctrl->txq.inlen_mode <= max_inline);
1191 assert(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send);
1192 assert(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw);
1200 * Create a DPDK Tx queue.
1203 * Pointer to Ethernet device.
1207 * Number of descriptors to configure in queue.
1209 * NUMA socket on which memory must be allocated.
1211 * Thresholds parameters.
1214 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1216 struct mlx5_txq_ctrl *
1217 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1218 unsigned int socket, const struct rte_eth_txconf *conf)
1220 struct mlx5_priv *priv = dev->data->dev_private;
1221 struct mlx5_txq_ctrl *tmpl;
1223 tmpl = rte_calloc_socket("TXQ", 1,
1225 desc * sizeof(struct rte_mbuf *),
1231 if (mlx5_mr_btree_init(&tmpl->txq.mr_ctrl.cache_bh,
1232 MLX5_MR_BTREE_CACHE_N, socket)) {
1233 /* rte_errno is already set. */
1236 /* Save pointer of global generation number to check memory event. */
1237 tmpl->txq.mr_ctrl.dev_gen_ptr = &priv->sh->mr.dev_gen;
1238 assert(desc > MLX5_TX_COMP_THRESH);
1239 tmpl->txq.offloads = conf->offloads |
1240 dev->data->dev_conf.txmode.offloads;
1242 tmpl->socket = socket;
1243 tmpl->txq.elts_n = log2above(desc);
1244 tmpl->txq.elts_s = desc;
1245 tmpl->txq.elts_m = desc - 1;
1246 tmpl->txq.port_id = dev->data->port_id;
1247 tmpl->txq.idx = idx;
1248 txq_set_params(tmpl);
1249 if (txq_adjust_params(tmpl))
1251 if (txq_calc_wqebb_cnt(tmpl) >
1252 priv->sh->device_attr.orig_attr.max_qp_wr) {
1254 "port %u Tx WQEBB count (%d) exceeds the limit (%d),"
1255 " try smaller queue size",
1256 dev->data->port_id, txq_calc_wqebb_cnt(tmpl),
1257 priv->sh->device_attr.orig_attr.max_qp_wr);
1261 rte_atomic32_inc(&tmpl->refcnt);
1262 tmpl->type = MLX5_TXQ_TYPE_STANDARD;
1263 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
1271 * Create a DPDK Tx hairpin queue.
1274 * Pointer to Ethernet device.
1278 * Number of descriptors to configure in queue.
1279 * @param hairpin_conf
1280 * The hairpin configuration.
1283 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1285 struct mlx5_txq_ctrl *
1286 mlx5_txq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1287 const struct rte_eth_hairpin_conf *hairpin_conf)
1289 struct mlx5_priv *priv = dev->data->dev_private;
1290 struct mlx5_txq_ctrl *tmpl;
1292 tmpl = rte_calloc_socket("TXQ", 1,
1293 sizeof(*tmpl), 0, SOCKET_ID_ANY);
1299 tmpl->socket = SOCKET_ID_ANY;
1300 tmpl->txq.elts_n = log2above(desc);
1301 tmpl->txq.port_id = dev->data->port_id;
1302 tmpl->txq.idx = idx;
1303 tmpl->hairpin_conf = *hairpin_conf;
1304 tmpl->type = MLX5_TXQ_TYPE_HAIRPIN;
1305 rte_atomic32_inc(&tmpl->refcnt);
1306 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
1314 * Pointer to Ethernet device.
1319 * A pointer to the queue if it exists.
1321 struct mlx5_txq_ctrl *
1322 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
1324 struct mlx5_priv *priv = dev->data->dev_private;
1325 struct mlx5_txq_ctrl *ctrl = NULL;
1327 if ((*priv->txqs)[idx]) {
1328 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
1330 mlx5_txq_obj_get(dev, idx);
1331 rte_atomic32_inc(&ctrl->refcnt);
1337 * Release a Tx queue.
1340 * Pointer to Ethernet device.
1345 * 1 while a reference on it exists, 0 when freed.
1348 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
1350 struct mlx5_priv *priv = dev->data->dev_private;
1351 struct mlx5_txq_ctrl *txq;
1353 if (!(*priv->txqs)[idx])
1355 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
1356 if (txq->obj && !mlx5_txq_obj_release(txq->obj))
1358 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
1360 mlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh);
1361 LIST_REMOVE(txq, next);
1363 (*priv->txqs)[idx] = NULL;
1370 * Verify if the queue can be released.
1373 * Pointer to Ethernet device.
1378 * 1 if the queue can be released.
1381 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
1383 struct mlx5_priv *priv = dev->data->dev_private;
1384 struct mlx5_txq_ctrl *txq;
1386 if (!(*priv->txqs)[idx])
1388 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
1389 return (rte_atomic32_read(&txq->refcnt) == 1);
1393 * Verify the Tx Queue list is empty
1396 * Pointer to Ethernet device.
1399 * The number of object not released.
1402 mlx5_txq_verify(struct rte_eth_dev *dev)
1404 struct mlx5_priv *priv = dev->data->dev_private;
1405 struct mlx5_txq_ctrl *txq_ctrl;
1408 LIST_FOREACH(txq_ctrl, &priv->txqsctrl, next) {
1409 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced",
1410 dev->data->port_id, txq_ctrl->txq.idx);