4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
47 #pragma GCC diagnostic error "-Wpedantic"
50 /* DPDK headers don't like -pedantic. */
52 #pragma GCC diagnostic ignored "-Wpedantic"
55 #include <rte_malloc.h>
56 #include <rte_ethdev.h>
57 #include <rte_common.h>
59 #pragma GCC diagnostic error "-Wpedantic"
62 #include "mlx5_utils.h"
63 #include "mlx5_defs.h"
65 #include "mlx5_rxtx.h"
66 #include "mlx5_autoconf.h"
67 #include "mlx5_defs.h"
70 * Allocate TX queue elements.
73 * Pointer to TX queue structure.
75 * Number of elements to allocate.
78 txq_alloc_elts(struct txq_ctrl *txq_ctrl, unsigned int elts_n)
82 for (i = 0; (i != elts_n); ++i)
83 (*txq_ctrl->txq.elts)[i] = NULL;
84 for (i = 0; (i != (1u << txq_ctrl->txq.wqe_n)); ++i) {
85 volatile struct mlx5_wqe64 *wqe =
86 (volatile struct mlx5_wqe64 *)
87 txq_ctrl->txq.wqes + i;
89 memset((void *)(uintptr_t)wqe, 0x0, sizeof(*wqe));
91 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
92 txq_ctrl->txq.elts_head = 0;
93 txq_ctrl->txq.elts_tail = 0;
94 txq_ctrl->txq.elts_comp = 0;
98 * Free TX queue elements.
101 * Pointer to TX queue structure.
104 txq_free_elts(struct txq_ctrl *txq_ctrl)
106 unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
107 unsigned int elts_head = txq_ctrl->txq.elts_head;
108 unsigned int elts_tail = txq_ctrl->txq.elts_tail;
109 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
111 DEBUG("%p: freeing WRs", (void *)txq_ctrl);
112 txq_ctrl->txq.elts_head = 0;
113 txq_ctrl->txq.elts_tail = 0;
114 txq_ctrl->txq.elts_comp = 0;
116 while (elts_tail != elts_head) {
117 struct rte_mbuf *elt = (*elts)[elts_tail];
120 rte_pktmbuf_free(elt);
123 memset(&(*elts)[elts_tail],
125 sizeof((*elts)[elts_tail]));
127 if (++elts_tail == elts_n)
133 * Clean up a TX queue.
135 * Destroy objects, free allocated memory and reset the structure for reuse.
138 * Pointer to TX queue structure.
141 txq_cleanup(struct txq_ctrl *txq_ctrl)
143 struct ibv_exp_release_intf_params params;
146 DEBUG("cleaning up %p", (void *)txq_ctrl);
147 txq_free_elts(txq_ctrl);
148 if (txq_ctrl->if_qp != NULL) {
149 assert(txq_ctrl->priv != NULL);
150 assert(txq_ctrl->priv->ctx != NULL);
151 assert(txq_ctrl->qp != NULL);
152 params = (struct ibv_exp_release_intf_params){
155 claim_zero(ibv_exp_release_intf(txq_ctrl->priv->ctx,
159 if (txq_ctrl->if_cq != NULL) {
160 assert(txq_ctrl->priv != NULL);
161 assert(txq_ctrl->priv->ctx != NULL);
162 assert(txq_ctrl->cq != NULL);
163 params = (struct ibv_exp_release_intf_params){
166 claim_zero(ibv_exp_release_intf(txq_ctrl->priv->ctx,
170 if (txq_ctrl->qp != NULL)
171 claim_zero(ibv_destroy_qp(txq_ctrl->qp));
172 if (txq_ctrl->cq != NULL)
173 claim_zero(ibv_destroy_cq(txq_ctrl->cq));
174 if (txq_ctrl->rd != NULL) {
175 struct ibv_exp_destroy_res_domain_attr attr = {
179 assert(txq_ctrl->priv != NULL);
180 assert(txq_ctrl->priv->ctx != NULL);
181 claim_zero(ibv_exp_destroy_res_domain(txq_ctrl->priv->ctx,
185 for (i = 0; (i != RTE_DIM(txq_ctrl->txq.mp2mr)); ++i) {
186 if (txq_ctrl->txq.mp2mr[i].mp == NULL)
188 assert(txq_ctrl->txq.mp2mr[i].mr != NULL);
189 claim_zero(ibv_dereg_mr(txq_ctrl->txq.mp2mr[i].mr));
191 memset(txq_ctrl, 0, sizeof(*txq_ctrl));
195 * Initialize TX queue.
198 * Pointer to TX queue control template.
200 * Pointer to TX queue control.
203 * 0 on success, errno value on failure.
206 txq_setup(struct txq_ctrl *tmpl, struct txq_ctrl *txq_ctrl)
208 struct mlx5_qp *qp = to_mqp(tmpl->qp);
209 struct ibv_cq *ibcq = tmpl->cq;
210 struct mlx5_cq *cq = to_mxxx(cq, cq);
212 if (cq->cqe_sz != RTE_CACHE_LINE_SIZE) {
213 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
214 "it should be set to %u", RTE_CACHE_LINE_SIZE);
217 tmpl->txq.cqe_n = log2above(ibcq->cqe);
218 tmpl->txq.qp_num_8s = qp->ctrl_seg.qp_num << 8;
219 tmpl->txq.wqes = qp->gen_data.sqstart;
220 tmpl->txq.wqe_n = log2above(qp->sq.wqe_cnt);
221 tmpl->txq.qp_db = &qp->gen_data.db[MLX5_SND_DBR];
222 tmpl->txq.bf_reg = qp->gen_data.bf->reg;
223 tmpl->txq.cq_db = cq->dbrec;
225 (volatile struct mlx5_cqe (*)[])
226 (uintptr_t)cq->active_buf->buf;
228 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])
229 ((uintptr_t)txq_ctrl + sizeof(*txq_ctrl));
234 * Configure a TX queue.
237 * Pointer to Ethernet device structure.
239 * Pointer to TX queue structure.
241 * Number of descriptors to configure in queue.
243 * NUMA socket on which memory must be allocated.
245 * Thresholds parameters.
248 * 0 on success, errno value on failure.
251 txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,
252 uint16_t desc, unsigned int socket,
253 const struct rte_eth_txconf *conf)
255 struct priv *priv = mlx5_get_priv(dev);
256 struct txq_ctrl tmpl = {
261 struct ibv_exp_query_intf_params params;
262 struct ibv_exp_qp_init_attr init;
263 struct ibv_exp_res_domain_init_attr rd;
264 struct ibv_exp_cq_init_attr cq;
265 struct ibv_exp_qp_attr mod;
266 struct ibv_exp_cq_attr cq_attr;
268 enum ibv_exp_query_intf_status status;
272 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
274 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set");
277 (void)conf; /* Thresholds configuration (ignored). */
278 assert(desc > MLX5_TX_COMP_THRESH);
279 tmpl.txq.elts_n = log2above(desc);
280 if (priv->mps == MLX5_MPW_ENHANCED)
281 tmpl.txq.mpw_hdr_dseg = priv->mpw_hdr_dseg;
282 /* MRs will be registered in mp2mr[] later. */
283 attr.rd = (struct ibv_exp_res_domain_init_attr){
284 .comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL |
285 IBV_EXP_RES_DOMAIN_MSG_MODEL),
286 .thread_model = IBV_EXP_THREAD_SINGLE,
287 .msg_model = IBV_EXP_MSG_HIGH_BW,
289 tmpl.rd = ibv_exp_create_res_domain(priv->ctx, &attr.rd);
290 if (tmpl.rd == NULL) {
292 ERROR("%p: RD creation failure: %s",
293 (void *)dev, strerror(ret));
296 attr.cq = (struct ibv_exp_cq_init_attr){
297 .comp_mask = IBV_EXP_CQ_INIT_ATTR_RES_DOMAIN,
298 .res_domain = tmpl.rd,
300 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
301 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
302 if (priv->mps == MLX5_MPW_ENHANCED)
303 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
304 tmpl.cq = ibv_exp_create_cq(priv->ctx,
306 NULL, NULL, 0, &attr.cq);
307 if (tmpl.cq == NULL) {
309 ERROR("%p: CQ creation failure: %s",
310 (void *)dev, strerror(ret));
313 DEBUG("priv->device_attr.max_qp_wr is %d",
314 priv->device_attr.max_qp_wr);
315 DEBUG("priv->device_attr.max_sge is %d",
316 priv->device_attr.max_sge);
317 attr.init = (struct ibv_exp_qp_init_attr){
318 /* CQ to be associated with the send queue. */
320 /* CQ to be associated with the receive queue. */
323 /* Max number of outstanding WRs. */
324 .max_send_wr = ((priv->device_attr.max_qp_wr < desc) ?
325 priv->device_attr.max_qp_wr :
328 * Max number of scatter/gather elements in a WR,
329 * must be 1 to prevent libmlx5 from trying to affect
330 * too much memory. TX gather is not impacted by the
331 * priv->device_attr.max_sge limit and will still work
336 .qp_type = IBV_QPT_RAW_PACKET,
337 /* Do *NOT* enable this, completions events are managed per
341 .res_domain = tmpl.rd,
342 .comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |
343 IBV_EXP_QP_INIT_ATTR_RES_DOMAIN),
345 if (priv->txq_inline && (priv->txqs_n >= priv->txqs_inline)) {
346 tmpl.txq.max_inline =
347 ((priv->txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
348 RTE_CACHE_LINE_SIZE);
349 tmpl.txq.inline_en = 1;
350 /* TSO and MPS can't be enabled concurrently. */
351 assert(!priv->tso || !priv->mps);
352 if (priv->mps == MLX5_MPW_ENHANCED) {
353 tmpl.txq.inline_max_packet_sz =
354 priv->inline_max_packet_sz;
355 /* To minimize the size of data set, avoid requesting
358 attr.init.cap.max_inline_data =
359 ((RTE_MIN(priv->txq_inline,
360 priv->inline_max_packet_sz) +
361 (RTE_CACHE_LINE_SIZE - 1)) /
362 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
364 attr.init.cap.max_inline_data =
365 tmpl.txq.max_inline * RTE_CACHE_LINE_SIZE;
369 uint16_t max_tso_inline = ((MLX5_MAX_TSO_HEADER +
370 (RTE_CACHE_LINE_SIZE - 1)) /
371 RTE_CACHE_LINE_SIZE);
373 attr.init.max_tso_header =
374 max_tso_inline * RTE_CACHE_LINE_SIZE;
375 attr.init.comp_mask |= IBV_EXP_QP_INIT_ATTR_MAX_TSO_HEADER;
376 tmpl.txq.max_inline = RTE_MAX(tmpl.txq.max_inline,
381 tmpl.txq.tunnel_en = 1;
382 tmpl.qp = ibv_exp_create_qp(priv->ctx, &attr.init);
383 if (tmpl.qp == NULL) {
384 ret = (errno ? errno : EINVAL);
385 ERROR("%p: QP creation failure: %s",
386 (void *)dev, strerror(ret));
389 DEBUG("TX queue capabilities: max_send_wr=%u, max_send_sge=%u,"
390 " max_inline_data=%u",
391 attr.init.cap.max_send_wr,
392 attr.init.cap.max_send_sge,
393 attr.init.cap.max_inline_data);
394 attr.mod = (struct ibv_exp_qp_attr){
395 /* Move the QP to this state. */
396 .qp_state = IBV_QPS_INIT,
397 /* Primary port number. */
398 .port_num = priv->port
400 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod,
401 (IBV_EXP_QP_STATE | IBV_EXP_QP_PORT));
403 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
404 (void *)dev, strerror(ret));
407 ret = txq_setup(&tmpl, txq_ctrl);
409 ERROR("%p: cannot initialize TX queue structure: %s",
410 (void *)dev, strerror(ret));
413 txq_alloc_elts(&tmpl, desc);
414 attr.mod = (struct ibv_exp_qp_attr){
415 .qp_state = IBV_QPS_RTR
417 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
419 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
420 (void *)dev, strerror(ret));
423 attr.mod.qp_state = IBV_QPS_RTS;
424 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
426 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
427 (void *)dev, strerror(ret));
430 attr.params = (struct ibv_exp_query_intf_params){
431 .intf_scope = IBV_EXP_INTF_GLOBAL,
432 .intf = IBV_EXP_INTF_CQ,
435 tmpl.if_cq = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
436 if (tmpl.if_cq == NULL) {
438 ERROR("%p: CQ interface family query failed with status %d",
439 (void *)dev, status);
442 attr.params = (struct ibv_exp_query_intf_params){
443 .intf_scope = IBV_EXP_INTF_GLOBAL,
444 .intf = IBV_EXP_INTF_QP_BURST,
447 /* Enable multi-packet send if supported. */
450 IBV_EXP_QP_BURST_CREATE_ENABLE_MULTI_PACKET_SEND_WR :
453 tmpl.if_qp = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
454 if (tmpl.if_qp == NULL) {
456 ERROR("%p: QP interface family query failed with status %d",
457 (void *)dev, status);
460 /* Clean up txq in case we're reinitializing it. */
461 DEBUG("%p: cleaning-up old txq just in case", (void *)txq_ctrl);
462 txq_cleanup(txq_ctrl);
464 DEBUG("%p: txq updated with %p", (void *)txq_ctrl, (void *)&tmpl);
465 /* Pre-register known mempools. */
466 rte_mempool_walk(txq_mp2mr_iter, txq_ctrl);
476 * DPDK callback to configure a TX queue.
479 * Pointer to Ethernet device structure.
483 * Number of descriptors to configure in queue.
485 * NUMA socket on which memory must be allocated.
487 * Thresholds parameters.
490 * 0 on success, negative errno value on failure.
493 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
494 unsigned int socket, const struct rte_eth_txconf *conf)
496 struct priv *priv = dev->data->dev_private;
497 struct txq *txq = (*priv->txqs)[idx];
498 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
501 if (mlx5_is_secondary())
502 return -E_RTE_SECONDARY;
505 if (desc <= MLX5_TX_COMP_THRESH) {
506 WARN("%p: number of descriptors requested for TX queue %u"
507 " must be higher than MLX5_TX_COMP_THRESH, using"
509 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
510 desc = MLX5_TX_COMP_THRESH + 1;
512 if (!rte_is_power_of_2(desc)) {
513 desc = 1 << log2above(desc);
514 WARN("%p: increased number of descriptors in TX queue %u"
515 " to the next power of two (%d)",
516 (void *)dev, idx, desc);
518 DEBUG("%p: configuring queue %u for %u descriptors",
519 (void *)dev, idx, desc);
520 if (idx >= priv->txqs_n) {
521 ERROR("%p: queue index out of range (%u >= %u)",
522 (void *)dev, idx, priv->txqs_n);
527 DEBUG("%p: reusing already allocated queue index %u (%p)",
528 (void *)dev, idx, (void *)txq);
533 (*priv->txqs)[idx] = NULL;
534 txq_cleanup(txq_ctrl);
535 /* Resize if txq size is changed. */
536 if (txq_ctrl->txq.elts_n != log2above(desc)) {
537 txq_ctrl = rte_realloc(txq_ctrl,
539 desc * sizeof(struct rte_mbuf *),
540 RTE_CACHE_LINE_SIZE);
542 ERROR("%p: unable to reallocate queue index %u",
550 rte_calloc_socket("TXQ", 1,
552 desc * sizeof(struct rte_mbuf *),
554 if (txq_ctrl == NULL) {
555 ERROR("%p: unable to allocate queue index %u",
561 ret = txq_ctrl_setup(dev, txq_ctrl, desc, socket, conf);
565 txq_ctrl->txq.stats.idx = idx;
566 DEBUG("%p: adding TX queue %p to list",
567 (void *)dev, (void *)txq_ctrl);
568 (*priv->txqs)[idx] = &txq_ctrl->txq;
569 /* Update send callback. */
570 priv_select_tx_function(priv);
577 * DPDK callback to release a TX queue.
580 * Generic TX queue pointer.
583 mlx5_tx_queue_release(void *dpdk_txq)
585 struct txq *txq = (struct txq *)dpdk_txq;
586 struct txq_ctrl *txq_ctrl;
590 if (mlx5_is_secondary())
595 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
596 priv = txq_ctrl->priv;
598 for (i = 0; (i != priv->txqs_n); ++i)
599 if ((*priv->txqs)[i] == txq) {
600 DEBUG("%p: removing TX queue %p from list",
601 (void *)priv->dev, (void *)txq_ctrl);
602 (*priv->txqs)[i] = NULL;
605 txq_cleanup(txq_ctrl);
611 * DPDK callback for TX in secondary processes.
613 * This function configures all queues from primary process information
614 * if necessary before reverting to the normal TX burst callback.
617 * Generic pointer to TX queue structure.
619 * Packets to transmit.
621 * Number of packets in array.
624 * Number of packets successfully transmitted (<= pkts_n).
627 mlx5_tx_burst_secondary_setup(void *dpdk_txq, struct rte_mbuf **pkts,
630 struct txq *txq = dpdk_txq;
631 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
632 struct priv *priv = mlx5_secondary_data_setup(txq_ctrl->priv);
633 struct priv *primary_priv;
639 mlx5_secondary_data[priv->dev->data->port_id].primary_priv;
640 /* Look for queue index in both private structures. */
641 for (index = 0; index != priv->txqs_n; ++index)
642 if (((*primary_priv->txqs)[index] == txq) ||
643 ((*priv->txqs)[index] == txq))
645 if (index == priv->txqs_n)
647 txq = (*priv->txqs)[index];
648 return priv->dev->tx_pkt_burst(txq, pkts, pkts_n);