4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
47 #pragma GCC diagnostic error "-Wpedantic"
50 /* DPDK headers don't like -pedantic. */
52 #pragma GCC diagnostic ignored "-Wpedantic"
55 #include <rte_malloc.h>
56 #include <rte_ethdev.h>
57 #include <rte_common.h>
59 #pragma GCC diagnostic error "-Wpedantic"
62 #include "mlx5_utils.h"
63 #include "mlx5_defs.h"
65 #include "mlx5_rxtx.h"
66 #include "mlx5_autoconf.h"
67 #include "mlx5_defs.h"
70 * Allocate TX queue elements.
73 * Pointer to TX queue structure.
75 * Number of elements to allocate.
78 txq_alloc_elts(struct txq_ctrl *txq_ctrl, unsigned int elts_n)
82 for (i = 0; (i != elts_n); ++i)
83 (*txq_ctrl->txq.elts)[i] = NULL;
84 for (i = 0; (i != (1u << txq_ctrl->txq.wqe_n)); ++i) {
85 volatile struct mlx5_wqe64 *wqe =
86 (volatile struct mlx5_wqe64 *)
87 txq_ctrl->txq.wqes + i;
89 memset((void *)(uintptr_t)wqe, 0x0, sizeof(*wqe));
91 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
92 txq_ctrl->txq.elts_head = 0;
93 txq_ctrl->txq.elts_tail = 0;
94 txq_ctrl->txq.elts_comp = 0;
98 * Free TX queue elements.
101 * Pointer to TX queue structure.
104 txq_free_elts(struct txq_ctrl *txq_ctrl)
106 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
107 const uint16_t elts_m = elts_n - 1;
108 uint16_t elts_head = txq_ctrl->txq.elts_head;
109 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
110 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
112 DEBUG("%p: freeing WRs", (void *)txq_ctrl);
113 txq_ctrl->txq.elts_head = 0;
114 txq_ctrl->txq.elts_tail = 0;
115 txq_ctrl->txq.elts_comp = 0;
117 while (elts_tail != elts_head) {
118 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
121 rte_pktmbuf_free_seg(elt);
124 memset(&(*elts)[elts_tail & elts_m],
126 sizeof((*elts)[elts_tail & elts_m]));
133 * Clean up a TX queue.
135 * Destroy objects, free allocated memory and reset the structure for reuse.
138 * Pointer to TX queue structure.
141 txq_cleanup(struct txq_ctrl *txq_ctrl)
145 DEBUG("cleaning up %p", (void *)txq_ctrl);
146 txq_free_elts(txq_ctrl);
147 if (txq_ctrl->qp != NULL)
148 claim_zero(ibv_destroy_qp(txq_ctrl->qp));
149 if (txq_ctrl->cq != NULL)
150 claim_zero(ibv_destroy_cq(txq_ctrl->cq));
151 for (i = 0; (i != RTE_DIM(txq_ctrl->txq.mp2mr)); ++i) {
152 if (txq_ctrl->txq.mp2mr[i].mp == NULL)
154 assert(txq_ctrl->txq.mp2mr[i].mr != NULL);
155 claim_zero(ibv_dereg_mr(txq_ctrl->txq.mp2mr[i].mr));
157 memset(txq_ctrl, 0, sizeof(*txq_ctrl));
161 * Initialize TX queue.
164 * Pointer to TX queue control template.
166 * Pointer to TX queue control.
169 * 0 on success, errno value on failure.
172 txq_setup(struct txq_ctrl *tmpl, struct txq_ctrl *txq_ctrl)
174 struct mlx5_qp *qp = to_mqp(tmpl->qp);
175 struct ibv_cq *ibcq = tmpl->cq;
176 struct ibv_mlx5_cq_info cq_info;
178 if (ibv_mlx5_exp_get_cq_info(ibcq, &cq_info)) {
179 ERROR("Unable to query CQ info. check your OFED.");
182 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
183 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
184 "it should be set to %u", RTE_CACHE_LINE_SIZE);
187 tmpl->txq.cqe_n = log2above(cq_info.cqe_cnt);
188 tmpl->txq.qp_num_8s = qp->ctrl_seg.qp_num << 8;
189 tmpl->txq.wqes = qp->gen_data.sqstart;
190 tmpl->txq.wqe_n = log2above(qp->sq.wqe_cnt);
191 tmpl->txq.qp_db = &qp->gen_data.db[MLX5_SND_DBR];
192 tmpl->txq.bf_reg = qp->gen_data.bf->reg;
193 tmpl->txq.cq_db = cq_info.dbrec;
195 (volatile struct mlx5_cqe (*)[])
196 (uintptr_t)cq_info.buf;
198 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])
199 ((uintptr_t)txq_ctrl + sizeof(*txq_ctrl));
204 * Configure a TX queue.
207 * Pointer to Ethernet device structure.
209 * Pointer to TX queue structure.
211 * Number of descriptors to configure in queue.
213 * NUMA socket on which memory must be allocated.
215 * Thresholds parameters.
218 * 0 on success, errno value on failure.
221 txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,
222 uint16_t desc, unsigned int socket,
223 const struct rte_eth_txconf *conf)
225 struct priv *priv = mlx5_get_priv(dev);
226 struct txq_ctrl tmpl = {
231 struct ibv_exp_qp_init_attr init;
232 struct ibv_exp_cq_init_attr cq;
233 struct ibv_exp_qp_attr mod;
234 struct ibv_exp_cq_attr cq_attr;
237 const unsigned int max_tso_inline = ((MLX5_MAX_TSO_HEADER +
238 (RTE_CACHE_LINE_SIZE - 1)) /
239 RTE_CACHE_LINE_SIZE);
242 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
244 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set");
247 (void)conf; /* Thresholds configuration (ignored). */
248 assert(desc > MLX5_TX_COMP_THRESH);
249 tmpl.txq.elts_n = log2above(desc);
250 if (priv->mps == MLX5_MPW_ENHANCED)
251 tmpl.txq.mpw_hdr_dseg = priv->mpw_hdr_dseg;
252 /* MRs will be registered in mp2mr[] later. */
253 attr.cq = (struct ibv_exp_cq_init_attr){
256 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
257 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
258 if (priv->mps == MLX5_MPW_ENHANCED)
259 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
260 tmpl.cq = ibv_exp_create_cq(priv->ctx,
262 NULL, NULL, 0, &attr.cq);
263 if (tmpl.cq == NULL) {
265 ERROR("%p: CQ creation failure: %s",
266 (void *)dev, strerror(ret));
269 DEBUG("priv->device_attr.max_qp_wr is %d",
270 priv->device_attr.max_qp_wr);
271 DEBUG("priv->device_attr.max_sge is %d",
272 priv->device_attr.max_sge);
273 attr.init = (struct ibv_exp_qp_init_attr){
274 /* CQ to be associated with the send queue. */
276 /* CQ to be associated with the receive queue. */
279 /* Max number of outstanding WRs. */
280 .max_send_wr = ((priv->device_attr.max_qp_wr < desc) ?
281 priv->device_attr.max_qp_wr :
284 * Max number of scatter/gather elements in a WR,
285 * must be 1 to prevent libmlx5 from trying to affect
286 * too much memory. TX gather is not impacted by the
287 * priv->device_attr.max_sge limit and will still work
292 .qp_type = IBV_QPT_RAW_PACKET,
293 /* Do *NOT* enable this, completions events are managed per
297 .comp_mask = IBV_EXP_QP_INIT_ATTR_PD,
299 if (priv->txq_inline && (priv->txqs_n >= priv->txqs_inline)) {
300 tmpl.txq.max_inline =
301 ((priv->txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
302 RTE_CACHE_LINE_SIZE);
303 tmpl.txq.inline_en = 1;
304 /* TSO and MPS can't be enabled concurrently. */
305 assert(!priv->tso || !priv->mps);
306 if (priv->mps == MLX5_MPW_ENHANCED) {
307 tmpl.txq.inline_max_packet_sz =
308 priv->inline_max_packet_sz;
309 /* To minimize the size of data set, avoid requesting
312 attr.init.cap.max_inline_data =
313 ((RTE_MIN(priv->txq_inline,
314 priv->inline_max_packet_sz) +
315 (RTE_CACHE_LINE_SIZE - 1)) /
316 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
317 } else if (priv->tso) {
318 int inline_diff = tmpl.txq.max_inline - max_tso_inline;
321 * Adjust inline value as Verbs aggregates
322 * tso_inline and txq_inline fields.
324 attr.init.cap.max_inline_data = inline_diff > 0 ?
326 RTE_CACHE_LINE_SIZE :
329 attr.init.cap.max_inline_data =
330 tmpl.txq.max_inline * RTE_CACHE_LINE_SIZE;
334 attr.init.max_tso_header =
335 max_tso_inline * RTE_CACHE_LINE_SIZE;
336 attr.init.comp_mask |= IBV_EXP_QP_INIT_ATTR_MAX_TSO_HEADER;
337 tmpl.txq.max_inline = RTE_MAX(tmpl.txq.max_inline,
342 tmpl.txq.tunnel_en = 1;
343 tmpl.qp = ibv_exp_create_qp(priv->ctx, &attr.init);
344 if (tmpl.qp == NULL) {
345 ret = (errno ? errno : EINVAL);
346 ERROR("%p: QP creation failure: %s",
347 (void *)dev, strerror(ret));
350 DEBUG("TX queue capabilities: max_send_wr=%u, max_send_sge=%u,"
351 " max_inline_data=%u",
352 attr.init.cap.max_send_wr,
353 attr.init.cap.max_send_sge,
354 attr.init.cap.max_inline_data);
355 attr.mod = (struct ibv_exp_qp_attr){
356 /* Move the QP to this state. */
357 .qp_state = IBV_QPS_INIT,
358 /* Primary port number. */
359 .port_num = priv->port
361 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod,
362 (IBV_EXP_QP_STATE | IBV_EXP_QP_PORT));
364 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
365 (void *)dev, strerror(ret));
368 ret = txq_setup(&tmpl, txq_ctrl);
370 ERROR("%p: cannot initialize TX queue structure: %s",
371 (void *)dev, strerror(ret));
374 txq_alloc_elts(&tmpl, desc);
375 attr.mod = (struct ibv_exp_qp_attr){
376 .qp_state = IBV_QPS_RTR
378 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
380 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
381 (void *)dev, strerror(ret));
384 attr.mod.qp_state = IBV_QPS_RTS;
385 ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);
387 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
388 (void *)dev, strerror(ret));
391 /* Clean up txq in case we're reinitializing it. */
392 DEBUG("%p: cleaning-up old txq just in case", (void *)txq_ctrl);
393 txq_cleanup(txq_ctrl);
395 DEBUG("%p: txq updated with %p", (void *)txq_ctrl, (void *)&tmpl);
396 /* Pre-register known mempools. */
397 rte_mempool_walk(txq_mp2mr_iter, txq_ctrl);
407 * DPDK callback to configure a TX queue.
410 * Pointer to Ethernet device structure.
414 * Number of descriptors to configure in queue.
416 * NUMA socket on which memory must be allocated.
418 * Thresholds parameters.
421 * 0 on success, negative errno value on failure.
424 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
425 unsigned int socket, const struct rte_eth_txconf *conf)
427 struct priv *priv = dev->data->dev_private;
428 struct txq *txq = (*priv->txqs)[idx];
429 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
432 if (mlx5_is_secondary())
433 return -E_RTE_SECONDARY;
436 if (desc <= MLX5_TX_COMP_THRESH) {
437 WARN("%p: number of descriptors requested for TX queue %u"
438 " must be higher than MLX5_TX_COMP_THRESH, using"
440 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
441 desc = MLX5_TX_COMP_THRESH + 1;
443 if (!rte_is_power_of_2(desc)) {
444 desc = 1 << log2above(desc);
445 WARN("%p: increased number of descriptors in TX queue %u"
446 " to the next power of two (%d)",
447 (void *)dev, idx, desc);
449 DEBUG("%p: configuring queue %u for %u descriptors",
450 (void *)dev, idx, desc);
451 if (idx >= priv->txqs_n) {
452 ERROR("%p: queue index out of range (%u >= %u)",
453 (void *)dev, idx, priv->txqs_n);
458 DEBUG("%p: reusing already allocated queue index %u (%p)",
459 (void *)dev, idx, (void *)txq);
464 (*priv->txqs)[idx] = NULL;
465 txq_cleanup(txq_ctrl);
466 /* Resize if txq size is changed. */
467 if (txq_ctrl->txq.elts_n != log2above(desc)) {
468 txq_ctrl = rte_realloc(txq_ctrl,
470 desc * sizeof(struct rte_mbuf *),
471 RTE_CACHE_LINE_SIZE);
473 ERROR("%p: unable to reallocate queue index %u",
481 rte_calloc_socket("TXQ", 1,
483 desc * sizeof(struct rte_mbuf *),
485 if (txq_ctrl == NULL) {
486 ERROR("%p: unable to allocate queue index %u",
492 ret = txq_ctrl_setup(dev, txq_ctrl, desc, socket, conf);
496 txq_ctrl->txq.stats.idx = idx;
497 DEBUG("%p: adding TX queue %p to list",
498 (void *)dev, (void *)txq_ctrl);
499 (*priv->txqs)[idx] = &txq_ctrl->txq;
500 /* Update send callback. */
501 priv_select_tx_function(priv);
508 * DPDK callback to release a TX queue.
511 * Generic TX queue pointer.
514 mlx5_tx_queue_release(void *dpdk_txq)
516 struct txq *txq = (struct txq *)dpdk_txq;
517 struct txq_ctrl *txq_ctrl;
521 if (mlx5_is_secondary())
526 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
527 priv = txq_ctrl->priv;
529 for (i = 0; (i != priv->txqs_n); ++i)
530 if ((*priv->txqs)[i] == txq) {
531 DEBUG("%p: removing TX queue %p from list",
532 (void *)priv->dev, (void *)txq_ctrl);
533 (*priv->txqs)[i] = NULL;
536 txq_cleanup(txq_ctrl);
542 * DPDK callback for TX in secondary processes.
544 * This function configures all queues from primary process information
545 * if necessary before reverting to the normal TX burst callback.
548 * Generic pointer to TX queue structure.
550 * Packets to transmit.
552 * Number of packets in array.
555 * Number of packets successfully transmitted (<= pkts_n).
558 mlx5_tx_burst_secondary_setup(void *dpdk_txq, struct rte_mbuf **pkts,
561 struct txq *txq = dpdk_txq;
562 struct txq_ctrl *txq_ctrl = container_of(txq, struct txq_ctrl, txq);
563 struct priv *priv = mlx5_secondary_data_setup(txq_ctrl->priv);
564 struct priv *primary_priv;
570 mlx5_secondary_data[priv->dev->data->port_id].primary_priv;
571 /* Look for queue index in both private structures. */
572 for (index = 0; index != priv->txqs_n; ++index)
573 if (((*primary_priv->txqs)[index] == txq) ||
574 ((*priv->txqs)[index] == txq))
576 if (index == priv->txqs_n)
578 txq = (*priv->txqs)[index];
579 return priv->dev->tx_pkt_burst(txq, pkts, pkts_n);