1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_malloc.h>
26 #include <rte_ethdev_driver.h>
27 #include <rte_common.h>
29 #include "mlx5_utils.h"
30 #include "mlx5_defs.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_glue.h"
37 * Allocate TX queue elements.
40 * Pointer to TX queue structure.
43 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
45 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
48 for (i = 0; (i != elts_n); ++i)
49 (*txq_ctrl->txq.elts)[i] = NULL;
50 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
51 PORT_ID(txq_ctrl->priv), txq_ctrl->idx, elts_n);
52 txq_ctrl->txq.elts_head = 0;
53 txq_ctrl->txq.elts_tail = 0;
54 txq_ctrl->txq.elts_comp = 0;
58 * Free TX queue elements.
61 * Pointer to TX queue structure.
64 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
66 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
67 const uint16_t elts_m = elts_n - 1;
68 uint16_t elts_head = txq_ctrl->txq.elts_head;
69 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
70 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
72 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs",
73 PORT_ID(txq_ctrl->priv), txq_ctrl->idx);
74 txq_ctrl->txq.elts_head = 0;
75 txq_ctrl->txq.elts_tail = 0;
76 txq_ctrl->txq.elts_comp = 0;
78 while (elts_tail != elts_head) {
79 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
82 rte_pktmbuf_free_seg(elt);
85 memset(&(*elts)[elts_tail & elts_m],
87 sizeof((*elts)[elts_tail & elts_m]));
94 * Returns the per-port supported offloads.
97 * Pointer to Ethernet device.
100 * Supported Tx offloads.
103 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
105 struct priv *priv = dev->data->dev_private;
106 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
107 DEV_TX_OFFLOAD_VLAN_INSERT);
108 struct mlx5_dev_config *config = &priv->config;
111 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
112 DEV_TX_OFFLOAD_UDP_CKSUM |
113 DEV_TX_OFFLOAD_TCP_CKSUM);
115 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
118 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
120 offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
121 DEV_TX_OFFLOAD_UDP_TNL_TSO);
124 if (config->tunnel_en) {
126 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
128 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
129 DEV_TX_OFFLOAD_GRE_TNL_TSO);
135 * DPDK callback to configure a TX queue.
138 * Pointer to Ethernet device structure.
142 * Number of descriptors to configure in queue.
144 * NUMA socket on which memory must be allocated.
146 * Thresholds parameters.
149 * 0 on success, a negative errno value otherwise and rte_errno is set.
152 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
153 unsigned int socket, const struct rte_eth_txconf *conf)
155 struct priv *priv = dev->data->dev_private;
156 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
157 struct mlx5_txq_ctrl *txq_ctrl =
158 container_of(txq, struct mlx5_txq_ctrl, txq);
160 if (desc <= MLX5_TX_COMP_THRESH) {
162 "port %u number of descriptors requested for Tx queue"
163 " %u must be higher than MLX5_TX_COMP_THRESH, using %u"
165 dev->data->port_id, idx, MLX5_TX_COMP_THRESH + 1, desc);
166 desc = MLX5_TX_COMP_THRESH + 1;
168 if (!rte_is_power_of_2(desc)) {
169 desc = 1 << log2above(desc);
171 "port %u increased number of descriptors in Tx queue"
172 " %u to the next power of two (%d)",
173 dev->data->port_id, idx, desc);
175 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors",
176 dev->data->port_id, idx, desc);
177 if (idx >= priv->txqs_n) {
178 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)",
179 dev->data->port_id, idx, priv->txqs_n);
180 rte_errno = EOVERFLOW;
183 if (!mlx5_txq_releasable(dev, idx)) {
185 DRV_LOG(ERR, "port %u unable to release queue index %u",
186 dev->data->port_id, idx);
189 mlx5_txq_release(dev, idx);
190 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
192 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
193 dev->data->port_id, idx);
196 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
197 dev->data->port_id, idx);
198 (*priv->txqs)[idx] = &txq_ctrl->txq;
203 * DPDK callback to release a TX queue.
206 * Generic TX queue pointer.
209 mlx5_tx_queue_release(void *dpdk_txq)
211 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
212 struct mlx5_txq_ctrl *txq_ctrl;
218 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
219 priv = txq_ctrl->priv;
220 for (i = 0; (i != priv->txqs_n); ++i)
221 if ((*priv->txqs)[i] == txq) {
222 mlx5_txq_release(ETH_DEV(priv), i);
223 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
224 PORT_ID(priv), txq_ctrl->idx);
231 * Mmap TX UAR(HW doorbell) pages into reserved UAR address space.
232 * Both primary and secondary process do mmap to make UAR address
236 * Pointer to Ethernet device.
238 * Verbs file descriptor to map UAR pages.
241 * 0 on success, a negative errno value otherwise and rte_errno is set.
244 mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd)
246 struct priv *priv = dev->data->dev_private;
248 uintptr_t pages[priv->txqs_n];
249 unsigned int pages_n = 0;
254 struct mlx5_txq_data *txq;
255 struct mlx5_txq_ctrl *txq_ctrl;
257 size_t page_size = sysconf(_SC_PAGESIZE);
259 unsigned int lock_idx;
262 memset(pages, 0, priv->txqs_n * sizeof(uintptr_t));
264 * As rdma-core, UARs are mapped in size of OS page size.
265 * Use aligned address to avoid duplicate mmap.
266 * Ref to libmlx5 function: mlx5_init_context()
268 for (i = 0; i != priv->txqs_n; ++i) {
269 if (!(*priv->txqs)[i])
271 txq = (*priv->txqs)[i];
272 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
273 assert(txq_ctrl->idx == (uint16_t)i);
274 /* UAR addr form verbs used to find dup and offset in page. */
275 uar_va = (uintptr_t)txq_ctrl->bf_reg_orig;
276 off = uar_va & (page_size - 1); /* offset in page. */
277 uar_va = RTE_ALIGN_FLOOR(uar_va, page_size); /* page addr. */
279 for (j = 0; j != pages_n; ++j) {
280 if (pages[j] == uar_va) {
285 /* new address in reserved UAR address space. */
286 addr = RTE_PTR_ADD(priv->uar_base,
287 uar_va & (uintptr_t)(MLX5_UAR_SIZE - 1));
288 if (!already_mapped) {
289 pages[pages_n++] = uar_va;
290 /* fixed mmap to specified address in reserved
293 ret = mmap(addr, page_size,
294 PROT_WRITE, MAP_FIXED | MAP_SHARED, fd,
295 txq_ctrl->uar_mmap_offset);
297 /* fixed mmap have to return same address */
299 "port %u call to mmap failed on UAR"
301 dev->data->port_id, txq_ctrl->idx);
306 if (rte_eal_process_type() == RTE_PROC_PRIMARY) /* save once */
307 txq_ctrl->txq.bf_reg = RTE_PTR_ADD((void *)addr, off);
309 assert(txq_ctrl->txq.bf_reg ==
310 RTE_PTR_ADD((void *)addr, off));
312 /* Assign a UAR lock according to UAR page number */
313 lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
314 MLX5_UAR_PAGE_NUM_MASK;
315 txq->uar_lock = &priv->uar_lock[lock_idx];
322 * Check if the burst function is using eMPW.
324 * @param tx_pkt_burst
325 * Tx burst function pointer.
328 * 1 if the burst function is using eMPW, 0 otherwise.
331 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst)
333 if (tx_pkt_burst == mlx5_tx_burst_raw_vec ||
334 tx_pkt_burst == mlx5_tx_burst_vec ||
335 tx_pkt_burst == mlx5_tx_burst_empw)
341 * Create the Tx queue Verbs object.
344 * Pointer to Ethernet device.
346 * Queue index in DPDK Rx queue array
349 * The Verbs object initialised, NULL otherwise and rte_errno is set.
351 struct mlx5_txq_ibv *
352 mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
354 struct priv *priv = dev->data->dev_private;
355 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
356 struct mlx5_txq_ctrl *txq_ctrl =
357 container_of(txq_data, struct mlx5_txq_ctrl, txq);
358 struct mlx5_txq_ibv tmpl;
359 struct mlx5_txq_ibv *txq_ibv;
361 struct ibv_qp_init_attr_ex init;
362 struct ibv_cq_init_attr_ex cq;
363 struct ibv_qp_attr mod;
364 struct ibv_cq_ex cq_attr;
367 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
368 struct mlx5dv_cq cq_info;
369 struct mlx5dv_obj obj;
370 const int desc = 1 << txq_data->elts_n;
371 eth_tx_burst_t tx_pkt_burst = mlx5_select_tx_function(dev);
375 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
376 priv->verbs_alloc_ctx.obj = txq_ctrl;
377 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
379 "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set",
384 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));
385 attr.cq = (struct ibv_cq_init_attr_ex){
388 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
389 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
390 if (is_empw_burst_func(tx_pkt_burst))
391 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
392 tmpl.cq = mlx5_glue->create_cq(priv->ctx, cqe_n, NULL, NULL, 0);
393 if (tmpl.cq == NULL) {
394 DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
395 dev->data->port_id, idx);
399 attr.init = (struct ibv_qp_init_attr_ex){
400 /* CQ to be associated with the send queue. */
402 /* CQ to be associated with the receive queue. */
405 /* Max number of outstanding WRs. */
407 ((priv->device_attr.orig_attr.max_qp_wr <
409 priv->device_attr.orig_attr.max_qp_wr :
412 * Max number of scatter/gather elements in a WR,
413 * must be 1 to prevent libmlx5 from trying to affect
414 * too much memory. TX gather is not impacted by the
415 * priv->device_attr.max_sge limit and will still work
420 .qp_type = IBV_QPT_RAW_PACKET,
422 * Do *NOT* enable this, completions events are managed per
427 .comp_mask = IBV_QP_INIT_ATTR_PD,
429 if (txq_data->max_inline)
430 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
431 if (txq_data->tso_en) {
432 attr.init.max_tso_header = txq_ctrl->max_tso_header;
433 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
435 tmpl.qp = mlx5_glue->create_qp_ex(priv->ctx, &attr.init);
436 if (tmpl.qp == NULL) {
437 DRV_LOG(ERR, "port %u Tx queue %u QP creation failure",
438 dev->data->port_id, idx);
442 attr.mod = (struct ibv_qp_attr){
443 /* Move the QP to this state. */
444 .qp_state = IBV_QPS_INIT,
445 /* Primary port number. */
448 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
449 (IBV_QP_STATE | IBV_QP_PORT));
452 "port %u Tx queue %u QP state to IBV_QPS_INIT failed",
453 dev->data->port_id, idx);
457 attr.mod = (struct ibv_qp_attr){
458 .qp_state = IBV_QPS_RTR
460 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
463 "port %u Tx queue %u QP state to IBV_QPS_RTR failed",
464 dev->data->port_id, idx);
468 attr.mod.qp_state = IBV_QPS_RTS;
469 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
472 "port %u Tx queue %u QP state to IBV_QPS_RTS failed",
473 dev->data->port_id, idx);
477 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,
480 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory",
481 dev->data->port_id, idx);
486 obj.cq.out = &cq_info;
489 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
494 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
496 "port %u wrong MLX5_CQE_SIZE environment variable"
497 " value: it should be set to %u",
498 dev->data->port_id, RTE_CACHE_LINE_SIZE);
502 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
503 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
504 txq_data->wqes = qp.sq.buf;
505 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
506 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
507 txq_ctrl->bf_reg_orig = qp.bf.reg;
508 txq_data->cq_db = cq_info.dbrec;
510 (volatile struct mlx5_cqe (*)[])
511 (uintptr_t)cq_info.buf;
516 txq_data->wqe_ci = 0;
517 txq_data->wqe_pi = 0;
518 txq_ibv->qp = tmpl.qp;
519 txq_ibv->cq = tmpl.cq;
520 rte_atomic32_inc(&txq_ibv->refcnt);
521 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
522 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
523 DRV_LOG(DEBUG, "port %u: uar_mmap_offset 0x%lx",
524 dev->data->port_id, txq_ctrl->uar_mmap_offset);
527 "port %u failed to retrieve UAR info, invalid"
533 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
534 txq_ibv->txq_ctrl = txq_ctrl;
535 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
538 ret = rte_errno; /* Save rte_errno before cleanup. */
540 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
542 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
543 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
544 rte_errno = ret; /* Restore rte_errno. */
549 * Get an Tx queue Verbs object.
552 * Pointer to Ethernet device.
554 * Queue index in DPDK Rx queue array
557 * The Verbs object if it exists.
559 struct mlx5_txq_ibv *
560 mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
562 struct priv *priv = dev->data->dev_private;
563 struct mlx5_txq_ctrl *txq_ctrl;
565 if (idx >= priv->txqs_n)
567 if (!(*priv->txqs)[idx])
569 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
571 rte_atomic32_inc(&txq_ctrl->ibv->refcnt);
572 return txq_ctrl->ibv;
576 * Release an Tx verbs queue object.
579 * Verbs Tx queue object.
582 * 1 while a reference on it exists, 0 when freed.
585 mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv)
588 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {
589 claim_zero(mlx5_glue->destroy_qp(txq_ibv->qp));
590 claim_zero(mlx5_glue->destroy_cq(txq_ibv->cq));
591 LIST_REMOVE(txq_ibv, next);
599 * Return true if a single reference exists on the object.
602 * Verbs Tx queue object.
605 mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv)
608 return (rte_atomic32_read(&txq_ibv->refcnt) == 1);
612 * Verify the Verbs Tx queue list is empty
615 * Pointer to Ethernet device.
618 * The number of object not released.
621 mlx5_txq_ibv_verify(struct rte_eth_dev *dev)
623 struct priv *priv = dev->data->dev_private;
625 struct mlx5_txq_ibv *txq_ibv;
627 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) {
628 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced",
629 dev->data->port_id, txq_ibv->txq_ctrl->idx);
636 * Set Tx queue parameters from device configuration.
639 * Pointer to Tx queue control structure.
642 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
644 struct priv *priv = txq_ctrl->priv;
645 struct mlx5_dev_config *config = &priv->config;
646 const unsigned int max_tso_inline =
647 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) /
648 RTE_CACHE_LINE_SIZE);
649 unsigned int txq_inline;
650 unsigned int txqs_inline;
651 unsigned int inline_max_packet_sz;
652 eth_tx_burst_t tx_pkt_burst =
653 mlx5_select_tx_function(ETH_DEV(priv));
654 int is_empw_func = is_empw_burst_func(tx_pkt_burst);
655 int tso = !!(txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO |
656 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
657 DEV_TX_OFFLOAD_GRE_TNL_TSO |
658 DEV_TX_OFFLOAD_IP_TNL_TSO |
659 DEV_TX_OFFLOAD_UDP_TNL_TSO));
661 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ?
662 0 : config->txq_inline;
663 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ?
664 0 : config->txqs_inline;
665 inline_max_packet_sz =
666 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ?
667 0 : config->inline_max_packet_sz;
669 if (config->txq_inline == MLX5_ARG_UNSET)
670 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;
671 if (config->txqs_inline == MLX5_ARG_UNSET)
672 txqs_inline = MLX5_EMPW_MIN_TXQS;
673 if (config->inline_max_packet_sz == MLX5_ARG_UNSET)
674 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN;
675 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg;
676 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz;
678 if (txq_inline && priv->txqs_n >= txqs_inline) {
681 txq_ctrl->txq.max_inline =
682 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
683 RTE_CACHE_LINE_SIZE);
685 /* To minimize the size of data set, avoid requesting
688 txq_ctrl->max_inline_data =
689 ((RTE_MIN(txq_inline,
690 inline_max_packet_sz) +
691 (RTE_CACHE_LINE_SIZE - 1)) /
692 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
694 txq_ctrl->max_inline_data =
695 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE;
698 * Check if the inline size is too large in a way which
699 * can make the WQE DS to overflow.
700 * Considering in calculation:
705 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE);
706 if (ds_cnt > MLX5_DSEG_MAX) {
707 unsigned int max_inline = (MLX5_DSEG_MAX - 2) *
710 max_inline = max_inline - (max_inline %
711 RTE_CACHE_LINE_SIZE);
713 "port %u txq inline is too large (%d) setting"
714 " it to the maximum possible: %d\n",
715 PORT_ID(priv), txq_inline, max_inline);
716 txq_ctrl->txq.max_inline = max_inline /
721 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE;
722 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline,
724 txq_ctrl->txq.tso_en = 1;
726 txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
727 txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
728 DEV_TX_OFFLOAD_UDP_TNL_TSO |
729 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
730 txq_ctrl->txq.offloads) && config->swp;
734 * Create a DPDK Tx queue.
737 * Pointer to Ethernet device.
741 * Number of descriptors to configure in queue.
743 * NUMA socket on which memory must be allocated.
745 * Thresholds parameters.
748 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
750 struct mlx5_txq_ctrl *
751 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
752 unsigned int socket, const struct rte_eth_txconf *conf)
754 struct priv *priv = dev->data->dev_private;
755 struct mlx5_txq_ctrl *tmpl;
757 tmpl = rte_calloc_socket("TXQ", 1,
759 desc * sizeof(struct rte_mbuf *),
765 if (mlx5_mr_btree_init(&tmpl->txq.mr_ctrl.cache_bh,
766 MLX5_MR_BTREE_CACHE_N, socket)) {
767 /* rte_errno is already set. */
770 /* Save pointer of global generation number to check memory event. */
771 tmpl->txq.mr_ctrl.dev_gen_ptr = &priv->mr.dev_gen;
772 assert(desc > MLX5_TX_COMP_THRESH);
773 tmpl->txq.offloads = conf->offloads |
774 dev->data->dev_conf.txmode.offloads;
776 tmpl->socket = socket;
777 tmpl->txq.elts_n = log2above(desc);
779 txq_set_params(tmpl);
780 DRV_LOG(DEBUG, "port %u priv->device_attr.max_qp_wr is %d",
781 dev->data->port_id, priv->device_attr.orig_attr.max_qp_wr);
782 DRV_LOG(DEBUG, "port %u priv->device_attr.max_sge is %d",
783 dev->data->port_id, priv->device_attr.orig_attr.max_sge);
785 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1);
786 tmpl->txq.stats.idx = idx;
787 rte_atomic32_inc(&tmpl->refcnt);
788 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
799 * Pointer to Ethernet device.
804 * A pointer to the queue if it exists.
806 struct mlx5_txq_ctrl *
807 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
809 struct priv *priv = dev->data->dev_private;
810 struct mlx5_txq_ctrl *ctrl = NULL;
812 if ((*priv->txqs)[idx]) {
813 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
815 mlx5_txq_ibv_get(dev, idx);
816 rte_atomic32_inc(&ctrl->refcnt);
822 * Release a Tx queue.
825 * Pointer to Ethernet device.
830 * 1 while a reference on it exists, 0 when freed.
833 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
835 struct priv *priv = dev->data->dev_private;
836 struct mlx5_txq_ctrl *txq;
837 size_t page_size = sysconf(_SC_PAGESIZE);
839 if (!(*priv->txqs)[idx])
841 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
842 if (txq->ibv && !mlx5_txq_ibv_release(txq->ibv))
845 munmap((void *)RTE_ALIGN_FLOOR((uintptr_t)txq->txq.bf_reg,
846 page_size), page_size);
847 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
849 mlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh);
850 LIST_REMOVE(txq, next);
852 (*priv->txqs)[idx] = NULL;
859 * Verify if the queue can be released.
862 * Pointer to Ethernet device.
867 * 1 if the queue can be released.
870 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
872 struct priv *priv = dev->data->dev_private;
873 struct mlx5_txq_ctrl *txq;
875 if (!(*priv->txqs)[idx])
877 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
878 return (rte_atomic32_read(&txq->refcnt) == 1);
882 * Verify the Tx Queue list is empty
885 * Pointer to Ethernet device.
888 * The number of object not released.
891 mlx5_txq_verify(struct rte_eth_dev *dev)
893 struct priv *priv = dev->data->dev_private;
894 struct mlx5_txq_ctrl *txq;
897 LIST_FOREACH(txq, &priv->txqsctrl, next) {
898 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced",
899 dev->data->port_id, txq->idx);